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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA3NCBTYWx0ZWRfX++G5k5gplyKe /LSfNSQYk6uovHIl+F/Xj+m0wL/wqAx4NBHYJP2z1s8b28B+JzSUEniKxbgKQeACGEDZCZuNfLJ O6TPdpUZltQShx/1bsjffhHAtx65/4Bjz1rCXUlsGW6bqxV9xHHRuQ+4pFv01nb2pNwkH7puYxw zy+fEgkEAmqsQ3dyR1robKCvVT0gUoUdFOoFGSEytxydwbBkj8KzAmZWXDIFgkpxmadLlZIoPdj VJzlN72JdSFXK0NkySj5l/FsSYTwkWdh8/mLzgNGLubMEXrtwTyjuMS8QSl2ZqB8R8AXEhjQHUD QzO7KctAiKZ9xNHnjYFHSA/1jc41pJce2y4M+s9ylNpeZCbF6kXfoM8Z2uAQfs0SoBivyZADRq8 XwyLI9/7xmXn1W33ob20CaDgTqybP8YAmaoOa4RiCgHNxfkNFF4K8TdmmZZ92J0iRFLXqcQQBFL BKlF+NIFmB/ZbIzUEng== X-Authority-Analysis: v=2.4 cv=aoyCzyZV c=1 sm=1 tr=0 ts=6a3ceb10 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TtB6gFZ535HFW_zVIisA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: labkMGg3kBo7yAfCA2tQaQGx2QaUoFfX X-Proofpoint-GUID: labkMGg3kBo7yAfCA2tQaQGx2QaUoFfX X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA3NCBTYWx0ZWRfX0ejBrvXhJm7u XF6pofzg9qsNTHdEAIXSpZE9jDJYBwLOMhihVDmvpb5kK21R0SYljXmLmJ4TzBDvRRrAIkClV0k UGZzLV1I4smGd+WfRnpo39Azpx/Tl/A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250074 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260625_014713_355586_E9744463 X-CRM114-Status: GOOD ( 27.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/19/26 12:54 PM, Bibek Kumar Patro wrote: > > > On 6/18/2026 2:58 PM, Konrad Dybcio wrote: >> On 6/17/26 4:26 PM, Bibek Kumar Patro wrote: >>> >>> >>> On 6/16/2026 5:51 AM, Dmitry Baryshkov wrote: >>>> On Mon, Jun 15, 2026 at 06:36:51PM +0530, Bibek Kumar Patro wrote: >>>>> >>>>> >>>>> On 6/8/2026 7:25 PM, Dmitry Baryshkov wrote: >>>>>> On Tue, May 26, 2026 at 08:12:03PM +0530, Bibek Kumar Patro wrote: >>>>>>> On some SoCs the SMMU registers require an active interconnect >>>>>>> bandwidth vote to be accessible. While other clients typically >>>>>>> satisfy this requirement implicitly, certain corner cases (e.g. >>>>>>> during sleep/wakeup transitions) can leave the SMMU without a >>>>>>> vote, causing intermittent register access failures. >>>>>>> >>>>>>> Add support for an optional interconnect path to the arm-smmu >>>>>>> driver and vote for bandwidth while the SMMU is active. The path >>>>>>> is acquired from DT if present and ignored otherwise. >>>>>>> >>>>>>> The bandwidth vote is enabled before accessing SMMU registers >>>>>>> during probe and runtime resume, and released during runtime >>>>>>> suspend and on error paths. >>>>>>> >>>>>>> Generally, from an architectural perspective, GEM_NOC and DDR are >>>>>>> expected to have an active vote whenever the adreno_smmu block is >>>>>>> powered on. In most common use cases, this requirement is implicitly >>>>>>> satisfied because other GPU-related clients (for example, the GMU >>>>>>> device) already hold a GEM_NOC vote when adreno_smmu is enabled. >>>>>>> >>>>>>> However, there are certain corner cases, such as during sleep/wakeup >>>>>>> transitions, where the GEM_NOC vote can be removed before adreno_smmu >>>>>>> is powered down. If adreno_smmu is then accessed while the interconnect >>>>>>> vote is missing, it can lead to the observed failures. Because of the >>>>>>> precise ordering involved, this scenario is difficult to reproduce >>>>>>> consistently. >>>>>>> (also GDSC is involved in adreno usecases can have an independent vote) >>>>>>> >>>>>>> Signed-off-by: Bibek Kumar Patro >>>>>>> --- >>>>>>>     drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++++++++++++++-- >>>>>>>     drivers/iommu/arm/arm-smmu/arm-smmu.h |  2 ++ >>>>>>>     2 files changed, 57 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> index 0bd21d206eb3e75c3b9fb1364cdc92e82c5aa499..07c7e44ec6a5bd1488f00f87d859a20495e46601 100644 >>>>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> @@ -53,6 +53,11 @@ >>>>>>>     #define MSI_IOVA_BASE            0x8000000 >>>>>>>     #define MSI_IOVA_LENGTH            0x100000 >>>>>>> +/* Interconnect bandwidth vote values for the SMMU register access path */ >>>>>>> +#define ARM_SMMU_ICC_AVG_BW        0 >>>>>>> +#define ARM_SMMU_ICC_PEAK_BW_HIGH    1000 >>>>>> >>>>>> totally random numbers, which might be different for non-Qualcomm platform. >>>>>> >>>>> >>>>> Ideally, any non-zero value would be enough to keep the path active. >>>> >>>> This is true for Qualcomm devices. However, you are adding this to a >>>> generic code. >>>> >>>>> Here 1 Would be enough to keep the path active, but might be too small to >>>>> reliably keep the bus active. >>>>> Other is UINT_MAX, which will reliably keep the bus active but might cause a >>>>> power penalty. >>>>> >>>>> #define ARM_SMMU_ICC_PEAK_BW_HIGH    UINT_MAX >>>>> >>>>> seems to be suitable here to reliably keep the bus active by BCM >>>>> for both Qualcomm and non-Qualcomm platforms (with some power penalty). >>>>> >>>>> LMK, if you feel otherwise. >>>> >>>> Shift it to the qcom instance or provide platform-specific values? (My >>>> preference would be towards the first solution). >>>> >>> >>> >>> To support platform-specific values, we may need to introduce a LUT-based approach in the driver. (Bandwidth voting values cannot be placed in device-tree property IIRC ?) >>> >>> Currently, all Qualcomm platforms use 0x1000 for SMMU ICC voting. I >> >> (you used decimal 1000) >> > > It's my bad, i meant 1000 only > (I'll check on the icc_bw calculation to get clarity on the values) > >>> can evaluate if this could be moved to a Qualcomm-specific >>> implementation. >> >> Add a vendor hook to arm_smmu_runtime_suspend/resume and handle it within >> the QC driver >> > > Just curious, wouldn't this apply for all the arm-smmu users in addition to Qualcomm devices as i mentioned here [1]. > Vendor hook would make it Qualcomm specific. You're proposing to use a Qualcomm-specific bandwidth value so that fits Konrad > > [1]: https://lore.kernel.org/all/984ff9c7-3eef-463c-a330-bf7acd063667@oss.qualcomm.com/ > > Thanks & regards, > Bibek > >> Konrad >