Re: [PATCH v5 00/13] Enable display support for STM32MP25

[Philippe CORNU <philippe.cornu@foss.st.com>]

On 8/22/25 16:34, Raphael Gallais-Pou wrote:
> This series aims to add and enable sufficient LVDS display support for
> STM32MP257F-EV1 board.
> 
> LVDS is the default use case to drive a display panel on STM32MP257F-EV,
> even though DSI panels will be supported in the near future.
> 
> The LTDC needs a pixel rate in sync with the bridge currently in use.
> For that both DSI and LVDS bridges need to declare an internal clock and
> become clock provider to the mux. The mux then selects the reference
> clock for the LTDC pixel rate generation.
> 
> For now this mux is handled internally in the LTDC, while waiting for
> the STM32 clock framework to merge a 'clk-mux' based on the SYSCFG.
> This explains the link done in the patch [7/8] between the LVDS,
> providing the reference clock for the LTDC internals.
> 
>    +----------+              |\
>    |  DSI PHY |------------->| \           +------------+
>    |          |ck_dsi_phy    |  |          |            |
>    +----------+              |  |--------->|    LTDC    |
>    +----------+              |  |pixel_clk |            |
>    | LVDS PHY |------------->|  |          +------------+
>    |          |clk_pix_lvds  |  |
>    +----------+              |  |
>                              |  |
>     ck_ker_ltdc ------------>| /
>                              |/|
>                                └- SYSCFG
> 
> Clock selection applies as follow:
> - 0b00: Selects ck_dsi_phy
> - 0b01: Selects clk_pix_lvds
> - 0b10: Selects ck_ker_ltdc (for parallel or DSI display).
> - 0b11: Reserved
> 
> The reset value of the register controlling the mux is 0b01, meaning
> that the default clock assigned is the clk_pix_lvds.  This causes two
> things:
> 
> - In order to get basic display on the LVDS encoder, like intended,
> nothing has to be done on this mux within the LTDC driver (which for now
> explains the unused syscfg phandle on the LTDC node in the device-tree).
> 
> - 'pixel_clk' is dependent from 'clk_pix_lvds' because of the LTDC clock
> domains.  They also need to be sync to get a coherent pixel rate though
> the display clock tree (which explains the LVDS phandle on the LTDC node
> in the device-tree).
> 
> Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
> ---
> Changes in v5:
> - Documentation:
>    - LTDC: Clamp correctly min/maxItems value (again)
> - Add Yannick's trailers where relevant except in patch [01/13] which
>    has been modified
> - Link to v4: https://lore.kernel.org/r/20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com
> 
> Changes in v4:
> - Documentation:
>    - LTDC: Add "st,stm32mp255-ltdc" compatible.  After internal
>      discussion, we came to the solution that the LTDC on STM32MP255 SoC
>      needs its own compatible, since it does have the same amount of
>      clocks than on STM32MP251 SoC.
> - Devicetree:
>    - Add "st,stm32mp255" compatible on corresponding dtsi
> - Drivers:
>    - LTDC: Handle "st,stm32mp255" compatible
> - Remove Rob's r-b from patch [01/13] since it was modified.
> - Link to v3: https://lore.kernel.org/r/20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com
> 
> Changes in v3:
> - Rebased on latest drm-misc-next
> - Documentation:
>    - LTDC: Clamp correctly min/maxItems value
>    - LVDS: Remove second 'items' keyword
> - Add Krzysztof's trailer where relevant
> - Link to v2: https://lore.kernel.org/r/20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com
> 
> Changes in v2:
> - Documentation:
>    - Add support for new compatible "st,stm32mp255-lvds"
>    - Change LTDC compatible for SoC compliant one
>    - Make clearer LTDC clock-names property
> - Devicetree:
>    - Change compatible according to the documentation
>    - Change clock and clock-names order to match documentation (and avoid
>      warnings)
> - Drivers:
>    - Change LTDC compatible
> - Add Rob's trailer where relevant
> - Link to v1: https://lore.kernel.org/r/20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com
> 
> ---
> Raphael Gallais-Pou (11):
>        dt-bindings: display: st: add two new compatibles to LTDC device
>        dt-bindings: display: st,stm32-ltdc: add access-controllers property
>        dt-bindings: display: st: add new compatible to LVDS device
>        dt-bindings: display: st,stm32mp25-lvds: add access-controllers property
>        dt-bindings: display: st,stm32mp25-lvds: add power-domains property
>        dt-bindings: arm: stm32: add required #clock-cells property
>        arm64: dts: st: add ltdc support on stm32mp251
>        arm64: dts: st: add ltdc support on stm32mp255
>        arm64: dts: st: add lvds support on stm32mp255
>        arm64: dts: st: add clock-cells to syscfg node on stm32mp251
>        arm64: dts: st: enable display support on stm32mp257f-ev1 board
> 
> Yannick Fertre (2):
>        drm/stm: ltdc: support new hardware version for STM32MP25 SoC
>        drm/stm: ltdc: handle lvds pixel clock
> 
>   .../bindings/arm/stm32/st,stm32-syscon.yaml        | 31 ++++++---
>   .../devicetree/bindings/display/st,stm32-ltdc.yaml | 55 ++++++++++++++-
>   .../bindings/display/st,stm32mp25-lvds.yaml        | 13 +++-
>   arch/arm64/boot/dts/st/stm32mp251.dtsi             | 19 ++++++
>   arch/arm64/boot/dts/st/stm32mp255.dtsi             | 20 +++++-
>   arch/arm64/boot/dts/st/stm32mp257f-ev1.dts         | 79 ++++++++++++++++++++++
>   drivers/gpu/drm/stm/drv.c                          | 12 +++-
>   drivers/gpu/drm/stm/ltdc.c                         | 58 +++++++++++++++-
>   drivers/gpu/drm/stm/ltdc.h                         |  6 ++
>   9 files changed, 275 insertions(+), 18 deletions(-)
> ---
> base-commit: c8cea4371e5eca30cda8660aabb337747dabc51d
> change-id: 20250617-drm-misc-next-4af406c1c45f
> 
> Best regards,

Hi Raphael,
Thank you for these great patches.

If you agree, I think you can merge 01-08 in misc.

Best regards
Philippe :-)