From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EBE6C433EF for ; Thu, 9 Jun 2022 10:36:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W1qdsYDPvllm4hPCiRdQHU3zN0JGQkXBK5D4etjnZ2s=; b=eseZBGN1WNNCo5 4hw6ugk8HSL4YTbmDCR8XAouEEXTwE9g4CKuqYPu6Pplx6bTKfMN4OhWLIPT6V+Lcc0kxh4/Yrs2r jZf6qx8YGV89gVG8p3peC2VRo/p9YuNjB/IMSFAYNlzp04GZOEFkWCFAla+QdJSHMPPGDYbyJU4fF l1Bt4QPEyurX/z5JCZ2+ucKfMilfnaDQ9WtKrvMXBoL9A+K1y9J/01u8nQM5EagjTmHPQMBiUVjyB fqVnaxP/ftQPEBSzmf73h+69HhHoPV5tod/68Ld6c37ltIKzDEkbvxKqOQt9OsXpCHmN1dX4u9tT2 tUQhNq1CdK3PvJDNeHCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzFVl-0011TG-To; Thu, 09 Jun 2022 10:35:34 +0000 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzFVj-0011Rl-4q for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2022 10:35:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1654770931; x=1686306931; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=3Znz8DrGVKl+VSTFbHf1qfRtqF/T0VJbeFWJBv2ixsA=; b=vkp2ttMwZUsm1bjFKUBdYl63hgRNdxD+SGkQOhDAuYvwtTb6tU+ULTB9 jMEex9iTyh1YtWaLasi9gTfdJlWFFWWp1I51XD0UGm3rMBPzOaajgZWxF Ydz0irTiWixdJtp5yGlMLAgRC2MkA/p3DMcz9AotfJG1GvKIebjtngWxC w=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 09 Jun 2022 03:35:28 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2022 03:35:27 -0700 Received: from [10.242.59.11] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 9 Jun 2022 03:35:23 -0700 Message-ID: <4f5dbc00-e25b-f6ff-8585-31fc50f48a21@quicinc.com> Date: Thu, 9 Jun 2022 16:05:20 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH V5] arm64: perf: Make exporting of pmu events configurable Content-Language: en-US To: Will Deacon CC: , , , , , , , , , , References: <1653306574-20946-1-git-send-email-quic_c_spathi@quicinc.com> <20220609100247.GA2187@willie-the-truck> From: Srinivasarao Pathipati In-Reply-To: <20220609100247.GA2187@willie-the-truck> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_033531_285246_9ECB70D6 X-CRM114-Status: GOOD ( 10.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On our Qualcomm platforms, The X bit is getting set by firmware at early bootup for Qualcomm use cases and non-secure world is resetting it, that causing issue. On 6/9/2022 3:32 PM, Will Deacon wrote: > On Mon, May 23, 2022 at 05:19:34PM +0530, Srinivasarao Pathipati wrote: >> The PMU export bit (PMCR_EL0.X) is getting reset during pmu reset, >> Make is configurable using sysctls to enable/disable at runtime. >> It can also be enabled at early bootup with kernel arguments. >> >> Signed-off-by: Srinivasarao Pathipati >> --- >> Changes since V4: >> - Registering sysctls dynamically for only arm64 as suggested by Will >> - Not removed the code to configure with kernel parameters >> as the sysctl's kernel parameter(sysctl.kernel.export_pmu_events) >> is not working at early bootup. pmu_reset() getting called before >> sysctl's kernel parameter is set. > Why do you need this during early bootup? Perf won't program any events > until much later and if somebody else is configuring the PMU before > entering Linux then they can also set that X bit in the PMCR. > > Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel