[PATCH 0/4] ARM: LPC32xx specific updates for next, third set

[PATCH 0/4] ARM: LPC32xx specific updates for next, third set

[Roland Stigge]

This is the third round of patches for mach-lpc32xx, for v3.6. This time,
patches from Alexandre, for PWM support and CPU ID.

If no objections surface, I'll provide pull requests for arm-soc branches
shortly.

Signed-off-by: Roland Stigge <stigge@antcom.de>

--
Alexandre Pereira da Silva (4):
 ARM: LPC32xx: Set system serial based on cpu unique id
 ARM: LPC32xx: Add PWM clock
 ARM: LPC32xx: Add PWM support
 ARM: LPC32xx: Add PWM to base dts file

 arch/arm/Kconfig               |    1 +
 arch/arm/boot/dts/lpc32xx.dtsi |   11 +++++++++++
 arch/arm/mach-lpc32xx/clock.c  |   14 ++++++++++++++
 arch/arm/mach-lpc32xx/common.c |   10 ++++++++--
 4 files changed, 34 insertions(+), 2 deletions(-)

[PATCH 1/4] ARM: LPC32xx: Set system serial based on cpu unique id

[Roland Stigge]

From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>

LPC32xx SoC has a 128 bits unique id that can be used as a system
serial number, if none has been provided by atags or dt.

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
 arch/arm/mach-lpc32xx/common.c |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.c
+++ linux-2.6/arch/arm/mach-lpc32xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const ch
 		;
 }
 
-static int __init lpc32xx_display_uid(void)
+static int __init lpc32xx_check_uid(void)
 {
 	u32 uid[4];
 
@@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(vo
 	printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
 		uid[3], uid[2], uid[1], uid[0]);
 
+	if (!system_serial_low && !system_serial_high) {
+		system_serial_low = uid[0];
+		system_serial_high = uid[1];
+	}
+
 	return 1;
 }
-arch_initcall(lpc32xx_display_uid);
+arch_initcall(lpc32xx_check_uid);

[PATCH 2/4] ARM: LPC32xx: Add PWM clock

[Roland Stigge]

From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
---

 arch/arm/mach-lpc32xx/clock.c |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -607,6 +607,19 @@ static struct clk clk_dma = {
 	.get_rate	= local_return_parent_rate,
 };
 
+static struct clk clk_pwm = {
+	.parent		= &clk_pclk,
+	.enable		= local_onoff_enable,
+	.enable_reg	= LPC32XX_CLKPWR_PWM_CLK_CTRL,
+	.enable_mask	= LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
+			  LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
+			  LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
+			  LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
+			  LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
+			  LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
+	.get_rate	= local_return_parent_rate,
+};
+
 static struct clk clk_uart3 = {
 	.parent		= &clk_pclk,
 	.enable		= local_onoff_enable,
@@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
 	CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
 	CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
+	CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
 	CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
 	CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
 	CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),

[PATCH 3/4] ARM: LPC32xx: Add PWM support

[Roland Stigge]

From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>

This SoC has two PWM channels

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
 arch/arm/Kconfig |    1 +
 1 file changed, 1 insertion(+)

--- linux-2.6.orig/arch/arm/Kconfig
+++ linux-2.6/arch/arm/Kconfig
@@ -567,6 +567,7 @@ config ARCH_LPC32XX
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select USE_OF
+	select HAVE_PWM
 	help
 	  Support for the NXP LPC32XX family of processors
 

[PATCH 4/4] ARM: LPC32xx: Add PWM to base dts file

[Roland Stigge]

From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>

Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
 arch/arm/boot/dts/lpc32xx.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -278,6 +278,17 @@
 				status = "disabled";
 			};
 
+			pwm1: pwm at 0x4005C000 {
+				compatible = "nxp,lpc3220-pwm";
+				reg = <0x4005C000 0x4>;
+				status = "disabled";
+			};
+
+			pwm2: pwm at 0x4005C004 {
+				compatible = "nxp,lpc3220-pwm";
+				reg = <0x4005C004 0x4>;
+				status = "disabled";
+			};
 		};
 	};
 };

[PATCH 4/4] ARM: LPC32xx: Add PWM to base dts file

[Roland Stigge]

On 07/18/2012 02:06 PM, Roland Stigge wrote:
> From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
> 
> Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
> ---
>  arch/arm/boot/dts/lpc32xx.dtsi |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> --- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
> +++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
> @@ -278,6 +278,17 @@
>  				status = "disabled";
>  			};
>  
> +			pwm1: pwm at 0x4005C000 {
> +				compatible = "nxp,lpc3220-pwm";
> +				reg = <0x4005C000 0x4>;
> +				status = "disabled";
> +			};
> +
> +			pwm2: pwm at 0x4005C004 {
> +				compatible = "nxp,lpc3220-pwm";
> +				reg = <0x4005C004 0x4>;
> +				status = "disabled";
> +			};
>  		};
>  	};
>  };

Sorry, grabbed old version of patch. Should have been:


			pwm: pwm at 4005C000 {
				compatible = "nxp,lpc3220-pwm";
				reg = <0x4005C000 0x8>;
				status = "disabled";
			};

... because the driver now always registers the two channels together.

Will push it this way.

Roland