Re: [PATCH v2 5/7] clk: sunxi-ng: add support for the A523/T527 MCU CCU

["Jernej Škrabec" <jernej.skrabec@gmail.com>]

Dne četrtek, 11. september 2025 ob 19:47:08 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset
> controls for the RISC-V MCU and other peripherals. There is a second
> audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main
> oscillator as the parent for all the bus clocks. But the diagram
> suggests busses from the other PRCM are used in this block as well.
> 
> Add a driver to support this part. Unlike the BSP driver, the SoC's main
> MBUS clock is chosen as the parent for the MCU MBUS clock, and the
> latter then serves as the parent of the MCU DMA controller's MBUS clock.
> The bus gate clocks also use their respective bus clocks as parents
> according to the system bus tree diagram. In cases where a block does
> not appear in that diagram, an educated guess is made.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> Changes since v1:
> - Added comment for "fixed" dividers in audio PLL clock
> - Corrected variable names for audio PLL divider clocks
> - Added comment for the reversed order of some of the DSP clock's
>   parents when compared to the manual
> - Added comments for clocks and resets only found in the BSP driver
> - Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks
> - Made "r-ahb" and new "r-apb0" external bus clocks the parents of the
>   bus gate clocks, with comments if guessed which one applies
> - Moved .num_clks to after the list of clocks, making it obvious that
>   the value needs to be added if more clocks are added to the list

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej