[PATCH 0/2] ARM ERRATA 775420 and 782773 workarounds

[PATCH 0/2] ARM ERRATA 775420 and 782773 workarounds

[Simon Horman]

Hi Russell,

I would like to request review of this series which is
comprised of the following two patches.

[PATCH 1/2] arm: Add ARM ERRATA 775420 workaround
[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[PATCH 1/2] arm: Add ARM ERRATA 775420 workaround

[Simon Horman]

From: Kouei Abe <kouei.abe.cp@rms.renesas.com>

Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
 arch/arm/Kconfig             |   10 ++++++++++
 arch/arm/kernel/entry-armv.S |   17 +++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d..74fbdf7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
 	  on systems with an outer cache, the store buffer is drained
 	  explicitly.
 
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+         operation aborts with MMU exception, it might cause the processor
+         deadlock. This workaround puts DSB before executing ISB at the
+         beginning of the abort exception handler.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..070fa62 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -989,10 +989,19 @@ __kuser_helper_end:
  * SP points to a minimal amount of processor-private memory, the address
  * of which is copied into r0 for the mode specific abort handler.
  */
+#ifdef CONFIG_ARM_ERRATA_775420
+	.macro	vector_stub, name, mode, correction=0, abort=0
+#else
 	.macro	vector_stub, name, mode, correction=0
+#endif
 	.align	5
 
 vector_\name:
+#ifdef CONFIG_ARM_ERRATA_775420
+	.if \abort
+	dsb
+	.endif
+#endif
 	.if \correction
 	sub	lr, lr, #\correction
 	.endif
@@ -1056,7 +1065,11 @@ __stubs_start:
  * Data abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
+#ifdef CONFIG_ARM_ERRATA_775420
+	vector_stub	dabt, ABT_MODE, 8, 1
+#else
 	vector_stub	dabt, ABT_MODE, 8
+#endif
 
 	.long	__dabt_usr			@  0  (USR_26 / USR_32)
 	.long	__dabt_invalid			@  1  (FIQ_26 / FIQ_32)
@@ -1079,7 +1092,11 @@ __stubs_start:
  * Prefetch abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
+#ifdef CONFIG_ARM_ERRATA_775420
+	vector_stub	pabt, ABT_MODE, 4, 1
+#else
 	vector_stub	pabt, ABT_MODE, 4
+#endif
 
 	.long	__pabt_usr			@  0 (USR_26 / USR_32)
 	.long	__pabt_invalid			@  1 (FIQ_26 / FIQ_32)
-- 
1.7.10.4

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Simon Horman]

From: Kouei Abe <kouei.abe.cp@rms.renesas.com>

Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
 arch/arm/Kconfig             |    9 +++++++++
 arch/arm/mm/proc-v7-2level.S |    8 ++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 74fbdf7..cc6bf76 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
          deadlock. This workaround puts DSB before executing ISB at the
          beginning of the abort exception handler.
 
+config ARM_ERRATA_782773
+	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
+	  ,r2 and r3 revisions) erratum. It might cause MMU exception in case
+	  page table walk happens just after updating the existing
+	  with setting page table in L1 data cache.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index fd045e7..9207b9f 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext)
 	tstne	r1, #L_PTE_PRESENT
 	moveq	r3, #0
 
+#ifdef CONFIG_ARM_ERRATA_782773
+	mrs	r2, cpsr			@ save cpsr
+	cpsid	if				@ disable interrupts
+	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
+#endif
  ARM(	str	r3, [r0, #2048]! )
  THUMB(	add	r0, r0, #2048 )
  THUMB(	str	r3, [r0] )
+#ifdef CONFIG_ARM_ERRATA_782773
+	msr	cpsr_c, r2			@ load cpsr
+#endif
 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
 #endif
 	mov	pc, lr
-- 
1.7.10.4

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Stephen Boyd]

On 09/12/12 00:14, Simon Horman wrote:
> @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
>           deadlock. This workaround puts DSB before executing ISB at the
>           beginning of the abort exception handler.
>  
> +config ARM_ERRATA_782773
> +	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> +	depends on CPU_V7
> +	help
> +	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
> +	  ,r2 and r3 revisions) erratum. It might cause MMU exception in case

Seems to be an extra comma here.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Simon Horman]

On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
> On 09/12/12 00:14, Simon Horman wrote:
> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
> >           deadlock. This workaround puts DSB before executing ISB at the
> >           beginning of the abort exception handler.
> >  
> > +config ARM_ERRATA_782773
> > +	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> > +	depends on CPU_V7
> > +	help
> > +	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
> > +	  ,r2 and r3 revisions) erratum. It might cause MMU exception in case
> 
> Seems to be an extra comma here.

Thanks, here is an updated version.

From: Kouei Abe <kouei.abe.cp@rms.renesas.com>

arm: Add ARM ERRATA 782773 workaround

Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
 arch/arm/Kconfig             |    9 +++++++++
 arch/arm/mm/proc-v7-2level.S |    8 ++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 74fbdf7..6367fd9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
          deadlock. This workaround puts DSB before executing ISB at the
          beginning of the abort exception handler.
 
+config ARM_ERRATA_782773
+	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
+	  r2 and r3 revisions) erratum. It might cause MMU exception in case
+	  page table walk happens just after updating the existing
+	  with setting page table in L1 data cache.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index fd045e7..9207b9f 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext)
 	tstne	r1, #L_PTE_PRESENT
 	moveq	r3, #0
 
+#ifdef CONFIG_ARM_ERRATA_782773
+	mrs	r2, cpsr			@ save cpsr
+	cpsid	if				@ disable interrupts
+	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
+#endif
  ARM(	str	r3, [r0, #2048]! )
  THUMB(	add	r0, r0, #2048 )
  THUMB(	str	r3, [r0] )
+#ifdef CONFIG_ARM_ERRATA_782773
+	msr	cpsr_c, r2			@ load cpsr
+#endif
 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
 #endif
 	mov	pc, lr
-- 
1.7.10.4

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Russell King - ARM Linux]

On Thu, Sep 13, 2012 at 10:00:42AM +0900, Simon Horman wrote:
> +config ARM_ERRATA_782773
> +	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> +	depends on CPU_V7
> +	help
> +	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
> +	  r2 and r3 revisions) erratum. It might cause MMU exception in case
> +	  page table walk happens just after updating the existing
> +	  with setting page table in L1 data cache.

What if we're running on a SMP system where the L1 caches are mandated
to be in write-allocate mode?  This write will immediately cause the
cache line to be brought back into the cache.

This sounds like a broken work-around to me.

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Catalin Marinas]

On 13 September 2012 18:20, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Thu, Sep 13, 2012 at 10:00:42AM +0900, Simon Horman wrote:
>> +config ARM_ERRATA_782773
>> +     bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
>> +     depends on CPU_V7
>> +     help
>> +       This option enables the workaround for the 782773 Cortex-A9 (all r0,
>> +       r2 and r3 revisions) erratum. It might cause MMU exception in case
>> +       page table walk happens just after updating the existing
>> +       with setting page table in L1 data cache.
>
> What if we're running on a SMP system where the L1 caches are mandated
> to be in write-allocate mode?  This write will immediately cause the
> cache line to be brought back into the cache.

Flushing the L1 cache line before being written (even though it will
be immediately brought back into the cache) will prevent a
micro-architectural condition that causes the erratum (the processor
writing the page table must hit in the L1 cache).

-- 
Catalin

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Catalin Marinas]

On 13 September 2012 02:00, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
>> On 09/12/12 00:14, Simon Horman wrote:
>> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
>> >           deadlock. This workaround puts DSB before executing ISB at the
>> >           beginning of the abort exception handler.
>> >
>> > +config ARM_ERRATA_782773
>> > +   bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
>> > +   depends on CPU_V7
>> > +   help
>> > +     This option enables the workaround for the 782773 Cortex-A9 (all r0,
>> > +     ,r2 and r3 revisions) erratum. It might cause MMU exception in case
>>
>> Seems to be an extra comma here.
>
> Thanks, here is an updated version.
>
> From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
>
> arm: Add ARM ERRATA 782773 workaround
>
> Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>

I would add some text to the commit log as well, even though it
matches the Kconfig entry.

Have you hit this in practice? In general the kernel shouldn't access
kernel virtual address corresponding to a page table that is being
changed. For user address space it is possible but the kernel can
handle use translation faults, even though they may be spurious.

-- 
Catalin

[PATCH 1/2] arm: Add ARM ERRATA 775420 workaround

[Catalin Marinas]

On 12 September 2012 08:14, Simon Horman <horms@verge.net.au> wrote:
> +config ARM_ERRATA_775420
> +       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
> +       depends on CPU_V7
> +       help
> +         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> +         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> +         operation aborts with MMU exception, it might cause the processor
> +         deadlock. This workaround puts DSB before executing ISB at the
> +         beginning of the abort exception handler.
> +
>  endmenu

The only case where we can get an abort on cache maintenance is
v7_coherent_user_range(). I don't think we have any ISB on the
exception handling path for this function, so we could just add the
DSB there:

--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, fail with -EFAULT.
  */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
 	mov	r0, #-EFAULT
 	mov	pc, lr
  UNWIND(.fnend		)

-- 
Catalin

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Simon Horman]

On Thu, Sep 20, 2012 at 10:35:50AM +0100, Catalin Marinas wrote:
> On 13 September 2012 02:00, Simon Horman <horms@verge.net.au> wrote:
> > On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
> >> On 09/12/12 00:14, Simon Horman wrote:
> >> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
> >> >           deadlock. This workaround puts DSB before executing ISB at the
> >> >           beginning of the abort exception handler.
> >> >
> >> > +config ARM_ERRATA_782773
> >> > +   bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> >> > +   depends on CPU_V7
> >> > +   help
> >> > +     This option enables the workaround for the 782773 Cortex-A9 (all r0,
> >> > +     ,r2 and r3 revisions) erratum. It might cause MMU exception in case
> >>
> >> Seems to be an extra comma here.
> >
> > Thanks, here is an updated version.
> >
> > From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> >
> > arm: Add ARM ERRATA 782773 workaround
> >
> > Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > Signed-off-by: Simon Horman <horms@verge.net.au>
> 
> I would add some text to the commit log as well, even though it
> matches the Kconfig entry.

Sure, an updated patch is below.
I also reworded the text to make it easier on my eyes,
I don't think the meaning has been altered.

> Have you hit this in practice? In general the kernel shouldn't access
> kernel virtual address corresponding to a page table that is being
> changed. For user address space it is possible but the kernel can
> handle use translation faults, even though they may be spurious.

I believe that Abe-san's team have come up against this,
I can confirm that if it is important.

----------------------------------------------------------------
From: Kouei Abe <kouei.abe.cp@rms.renesas.com>

arm: Add ARM ERRATA 782773 workaround

This is a workaround for Errata 782773 which effects all r0, r2 and r3
revisions.

The work-around avoids the possibility of an MMU exception in the case
where a page table walk occurs immediately after a page table update
that hasn't been flushed from the L1 data cache.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>

---

v2
* Reword Kconfig description
* Add some details to changelog entry

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 48c19d4..2b76164 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
 	 to deadlock. This workaround puts DSB before executing ISB if
 	 an abort may occur on cache maintenance.
 
+config ARM_ERRATA_782773
+	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
+	  r2 and r3 revisions) erratum. It might cause MMU exception in case
+	  page table walk happens just after updating the existing
+	  with setting page table in L1 data cache.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index fd045e7..9207b9f 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext)
 	tstne	r1, #L_PTE_PRESENT
 	moveq	r3, #0
 
+#ifdef CONFIG_ARM_ERRATA_782773
+	mrs	r2, cpsr			@ save cpsr
+	cpsid	if				@ disable interrupts
+	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
+#endif
  ARM(	str	r3, [r0, #2048]! )
  THUMB(	add	r0, r0, #2048 )
  THUMB(	str	r3, [r0] )
+#ifdef CONFIG_ARM_ERRATA_782773
+	msr	cpsr_c, r2			@ load cpsr
+#endif
 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
 #endif
 	mov	pc, lr
-- 
1.7.10.4

[PATCH 1/2] arm: Add ARM ERRATA 775420 workaround

[Simon Horman]

On Thu, Sep 20, 2012 at 10:58:53AM +0100, Catalin Marinas wrote:
> On 12 September 2012 08:14, Simon Horman <horms@verge.net.au> wrote:
> > +config ARM_ERRATA_775420
> > +       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
> > +       depends on CPU_V7
> > +       help
> > +         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> > +         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> > +         operation aborts with MMU exception, it might cause the processor
> > +         deadlock. This workaround puts DSB before executing ISB at the
> > +         beginning of the abort exception handler.
> > +
> >  endmenu
> 
> The only case where we can get an abort on cache maintenance is
> v7_coherent_user_range(). I don't think we have any ISB on the
> exception handling path for this function, so we could just add the
> DSB there:

I think that an advantage of Abe-san's implementation is that
it might to be a bit more robust. But your proposal is certainly
much cleaner and for that reason I agree it is a good option.

I've updated the patch, but since the code is now all yours
I'm unsure if the author should be changed or not.

----------------------------------------------------------------
From: Kouei Abe <kouei.abe.cp@rms.renesas.com>

arm: Add ARM ERRATA 775420 workaround

Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.

Based on work by Kouei Abe and feedback from Catalin Marinas.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>

---

v2
* Add some details to changelog entry
* Alternate implementation suggested by Catalin Marinas
  - Add the dsb directly to v7_coherent_user_range() rather
    than the exception handler
---
 arch/arm/Kconfig       |   10 ++++++++++
 arch/arm/mm/cache-v7.S |    3 +++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d..48c19d4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
 	  on systems with an outer cache, the store buffer is drained
 	  explicitly.
 
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+       depends on CPU_V7
+       help
+	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+	 operation aborts with MMU exception, it might cause the processor
+	 to deadlock. This workaround puts DSB before executing ISB if
+	 an abort may occur on cache maintenance.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 39e3fb3..3b17227 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, fail with -EFAULT.
  */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
 	mov	r0, #-EFAULT
 	mov	pc, lr
  UNWIND(.fnend		)
-- 
1.7.10.4

[PATCH 1/2] arm: Add ARM ERRATA 775420 workaround

[Catalin Marinas]

On Fri, Sep 21, 2012 at 02:04:04AM +0100, Simon Horman wrote:
> On Thu, Sep 20, 2012 at 10:58:53AM +0100, Catalin Marinas wrote:
> > On 12 September 2012 08:14, Simon Horman <horms@verge.net.au> wrote:
> > > +config ARM_ERRATA_775420
> > > +       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
> > > +       depends on CPU_V7
> > > +       help
> > > +         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> > > +         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> > > +         operation aborts with MMU exception, it might cause the processor
> > > +         deadlock. This workaround puts DSB before executing ISB at the
> > > +         beginning of the abort exception handler.
> > > +
> > >  endmenu
> > 
> > The only case where we can get an abort on cache maintenance is
> > v7_coherent_user_range(). I don't think we have any ISB on the
> > exception handling path for this function, so we could just add the
> > DSB there:
> 
> I think that an advantage of Abe-san's implementation is that
> it might to be a bit more robust. But your proposal is certainly
> much cleaner and for that reason I agree it is a good option.

It is more robust but I'm not sure it's worth putting a DSB a any data
abort.

> I've updated the patch, but since the code is now all yours
> I'm unsure if the author should be changed or not.

But the Kconfig entry is yours and it has more lines :)

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Simon Horman]

On Fri, Sep 21, 2012 at 10:00:37AM +0900, Simon Horman wrote:
> On Thu, Sep 20, 2012 at 10:35:50AM +0100, Catalin Marinas wrote:
> > On 13 September 2012 02:00, Simon Horman <horms@verge.net.au> wrote:
> > > On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
> > >> On 09/12/12 00:14, Simon Horman wrote:
> > >> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
> > >> >           deadlock. This workaround puts DSB before executing ISB at the
> > >> >           beginning of the abort exception handler.
> > >> >
> > >> > +config ARM_ERRATA_782773
> > >> > +   bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> > >> > +   depends on CPU_V7
> > >> > +   help
> > >> > +     This option enables the workaround for the 782773 Cortex-A9 (all r0,
> > >> > +     ,r2 and r3 revisions) erratum. It might cause MMU exception in case
> > >>
> > >> Seems to be an extra comma here.
> > >
> > > Thanks, here is an updated version.
> > >
> > > From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > >
> > > arm: Add ARM ERRATA 782773 workaround
> > >
> > > Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > > Signed-off-by: Simon Horman <horms@verge.net.au>
> > 
> > I would add some text to the commit log as well, even though it
> > matches the Kconfig entry.
> 
> Sure, an updated patch is below.
> I also reworded the text to make it easier on my eyes,
> I don't think the meaning has been altered.
> 
> > Have you hit this in practice? In general the kernel shouldn't access
> > kernel virtual address corresponding to a page table that is being
> > changed. For user address space it is possible but the kernel can
> > handle use translation faults, even though they may be spurious.
> 
> I believe that Abe-san's team have come up against this,
> I can confirm that if it is important.

Hi Catalin,

I was wondering if I could get an Ack on this as you indicated
in another email that you feel that the implementation is an
appropriate workaround.

> 
> ----------------------------------------------------------------
> From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> 
> arm: Add ARM ERRATA 782773 workaround
> 
> This is a workaround for Errata 782773 which effects all r0, r2 and r3
> revisions.
> 
> The work-around avoids the possibility of an MMU exception in the case
> where a page table walk occurs immediately after a page table update
> that hasn't been flushed from the L1 data cache.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> 
> ---
> 
> v2
> * Reword Kconfig description
> * Add some details to changelog entry
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 48c19d4..2b76164 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
>  	 to deadlock. This workaround puts DSB before executing ISB if
>  	 an abort may occur on cache maintenance.
>  
> +config ARM_ERRATA_782773
> +	bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> +	depends on CPU_V7
> +	help
> +	  This option enables the workaround for the 782773 Cortex-A9 (all r0,
> +	  r2 and r3 revisions) erratum. It might cause MMU exception in case
> +	  page table walk happens just after updating the existing
> +	  with setting page table in L1 data cache.
> +
>  endmenu
>  
>  source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
> index fd045e7..9207b9f 100644
> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext)
>  	tstne	r1, #L_PTE_PRESENT
>  	moveq	r3, #0
>  
> +#ifdef CONFIG_ARM_ERRATA_782773
> +	mrs	r2, cpsr			@ save cpsr
> +	cpsid	if				@ disable interrupts
> +	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
> +#endif
>   ARM(	str	r3, [r0, #2048]! )
>   THUMB(	add	r0, r0, #2048 )
>   THUMB(	str	r3, [r0] )
> +#ifdef CONFIG_ARM_ERRATA_782773
> +	msr	cpsr_c, r2			@ load cpsr
> +#endif
>  	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
>  #endif
>  	mov	pc, lr
> -- 
> 1.7.10.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Catalin Marinas]

On Fri, Sep 28, 2012 at 02:02:46AM +0100, Simon Horman wrote:
> On Fri, Sep 21, 2012 at 10:00:37AM +0900, Simon Horman wrote:
> > On Thu, Sep 20, 2012 at 10:35:50AM +0100, Catalin Marinas wrote:
> > > On 13 September 2012 02:00, Simon Horman <horms@verge.net.au> wrote:
> > > > On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
> > > >> On 09/12/12 00:14, Simon Horman wrote:
> > > >> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
> > > >> >           deadlock. This workaround puts DSB before executing ISB at the
> > > >> >           beginning of the abort exception handler.
> > > >> >
> > > >> > +config ARM_ERRATA_782773
> > > >> > +   bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> > > >> > +   depends on CPU_V7
> > > >> > +   help
> > > >> > +     This option enables the workaround for the 782773 Cortex-A9 (all r0,
> > > >> > +     ,r2 and r3 revisions) erratum. It might cause MMU exception in case
> > > >>
> > > >> Seems to be an extra comma here.
> > > >
> > > > Thanks, here is an updated version.
> > > >
> > > > From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > > >
> > > > arm: Add ARM ERRATA 782773 workaround
> > > >
> > > > Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > > > Signed-off-by: Simon Horman <horms@verge.net.au>
> > > 
> > > I would add some text to the commit log as well, even though it
> > > matches the Kconfig entry.
> > 
> > Sure, an updated patch is below.
> > I also reworded the text to make it easier on my eyes,
> > I don't think the meaning has been altered.
> > 
> > > Have you hit this in practice? In general the kernel shouldn't access
> > > kernel virtual address corresponding to a page table that is being
> > > changed. For user address space it is possible but the kernel can
> > > handle use translation faults, even though they may be spurious.
> > 
> > I believe that Abe-san's team have come up against this,
> > I can confirm that if it is important.
> 
> I was wondering if I could get an Ack on this as you indicated
> in another email that you feel that the implementation is an
> appropriate workaround.

I'd like to know whether this is actually hit in practice and the
conditions. The only time when we write live (i.e. translation that's
currently in use) kernel mappings is during boot, alloc_init_section()
replacing (though with the same value) the initial memory map. But if
that's the scenario you are getting, I would rather add another
flush_pmd_entry() call before setting the pmd in alloc_init_section().

I'm not convinced a costly run-time workaround in set_pte is needed.

-- 
Catalin

[PATCH 2/2] arm: Add ARM ERRATA 782773 workaround

[Simon Horman]

On Fri, Sep 28, 2012 at 09:38:19AM +0100, Catalin Marinas wrote:
> On Fri, Sep 28, 2012 at 02:02:46AM +0100, Simon Horman wrote:
> > On Fri, Sep 21, 2012 at 10:00:37AM +0900, Simon Horman wrote:
> > > On Thu, Sep 20, 2012 at 10:35:50AM +0100, Catalin Marinas wrote:
> > > > On 13 September 2012 02:00, Simon Horman <horms@verge.net.au> wrote:
> > > > > On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote:
> > > > >> On 09/12/12 00:14, Simon Horman wrote:
> > > > >> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420
> > > > >> >           deadlock. This workaround puts DSB before executing ISB at the
> > > > >> >           beginning of the abort exception handler.
> > > > >> >
> > > > >> > +config ARM_ERRATA_782773
> > > > >> > +   bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> > > > >> > +   depends on CPU_V7
> > > > >> > +   help
> > > > >> > +     This option enables the workaround for the 782773 Cortex-A9 (all r0,
> > > > >> > +     ,r2 and r3 revisions) erratum. It might cause MMU exception in case
> > > > >>
> > > > >> Seems to be an extra comma here.
> > > > >
> > > > > Thanks, here is an updated version.
> > > > >
> > > > > From: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > > > >
> > > > > arm: Add ARM ERRATA 782773 workaround
> > > > >
> > > > > Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
> > > > > Signed-off-by: Simon Horman <horms@verge.net.au>
> > > > 
> > > > I would add some text to the commit log as well, even though it
> > > > matches the Kconfig entry.
> > > 
> > > Sure, an updated patch is below.
> > > I also reworded the text to make it easier on my eyes,
> > > I don't think the meaning has been altered.
> > > 
> > > > Have you hit this in practice? In general the kernel shouldn't access
> > > > kernel virtual address corresponding to a page table that is being
> > > > changed. For user address space it is possible but the kernel can
> > > > handle use translation faults, even though they may be spurious.
> > > 
> > > I believe that Abe-san's team have come up against this,
> > > I can confirm that if it is important.
> > 
> > I was wondering if I could get an Ack on this as you indicated
> > in another email that you feel that the implementation is an
> > appropriate workaround.
> 
> I'd like to know whether this is actually hit in practice and the
> conditions. The only time when we write live (i.e. translation that's
> currently in use) kernel mappings is during boot, alloc_init_section()
> replacing (though with the same value) the initial memory map. But if
> that's the scenario you are getting, I would rather add another
> flush_pmd_entry() call before setting the pmd in alloc_init_section().
> 
> I'm not convinced a costly run-time workaround in set_pte is needed.

Hi Catalin,

I have discussed this the issue that you raised above with the platform
team that provided me with the workaround. Although they have not encountered a
situation in which the errata is hit they would like the workaround
considered for merging as it is needed for compliance with customer
requirements, in this case an automotive customer (I do not know which one).