[PATCH v4] gpio: mvebu: new gpio driver for mvebu platforms

[PATCH v4] gpio: mvebu: new gpio driver for mvebu platforms

[Thomas Petazzoni]

Grant,

This patch set adds a new GPIO driver for Marvell EBU SoCs, which aims
at replacing the existing GPIO driver from plat-orion/gpio.c. The
driver comes with the necessary DT changes to make it work on Armada
370 and Armada XP, and it has been tested successfully by Sebastian
Hesselbarth on Dove.

It should also work flawlessly on other Marvell EBU SoCs (Kirkwood,
Orion, Discovery), but this remains to be tested by the relevant
maintainers. This isn't however a problem, as those older platforms
need to explictly be converted over to the new pinctrl-mvebu driver
and the new gpio driver. Until that, they will happily continue to use
the old, known-working, gpio driver. So this patch set has no chance
to break any of the existing Marvell platforms. The old gpio driver is
scheduled to be removed once all Marvell SoCs have switched to the new
driver.

This new driver reuses a lot of code from the existing
plat-orion/gpio.c driver, but has a number of advantages:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

This patch set should be applied on top of the pinctrl-mvebu patch set
v4 from Sebastian Hesselbarth, as it depends on it.

Changes since v2:
 * Use inline functions for the register accessors, and rename them
   lower-case since they are functions, as suggested by
   Jean-Christophe Plagnol-Villard.
 * Use _relaxed() variants of readl/writel, as suggested by
   Jean-Christophe Plagnol-Villard.
 * Use switch() instead of long list of if() conditions in
   mvebu_gpio_irq_set_type(), as suggested by Jean-Christophe
   Plagnol-Villard.
 * Add DT aliases gpio0, gpio1, gpio2, and then use of_alias_get_id()
   to get the number of GPIO bank, and deduce the GPIO base from
   it. We don't use automatic allocation because we really want the
   internal SoC GPIOs to have 0-31, 32-63, 64-... numbers (while
   automatic allocation allocates 224... for the first bank 202... for
   the second bank, etc.). This strategy was recommended by Uwe
   Kleine-Koenig and is already used in gpio-mxs.c.
 * Use gpio-cells = <2> instead of gpio-cells = <1>, as suggested by
   Olof Johansson. This allows to re-use the default .xlate()
   function, and therefore make the GPIO DT binding actually work (it
   was broken in previous versions of this patch set).
 * Use dev_name() to fill the gpio_chip->name field, instead of
   manually computing a name. This allows to get rid of the global
   variable counting GPIO chips.
 * Rebase on top of the latest pinctrl work from Sebastian
   Hesselbarth.
 * Added the Acked-by from Linus Walleij on the DT binding
   documentation patch.

Changes since v1:
 * Added fixes for Dove from Sebastian Hesselbarth, and his Tested-by
   on the driver patch.

Thanks,

Thomas

[PATCH v3 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs

[Thomas Petazzoni]

This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
and is designed to be compatible with all Marvell EBU SoCs: Orion,
Kirkwood, Dove, Armada 370/XP and Discovery.

It has been successfully tested on Dove and Armada XP at the moment.

Compared to the plat-orion driver, this new driver has the following
added benefits:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
 drivers/gpio/Kconfig      |    6 +
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/gpio-mvebu.c |  679 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 686 insertions(+)
 create mode 100644 drivers/gpio/gpio-mvebu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..993b0c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -150,6 +150,12 @@ config GPIO_MSM_V2
 	  Qualcomm MSM chips.  Most of the pins on the MSM can be
 	  selected for GPIO, and are controlled by this driver.
 
+config GPIO_MVEBU
+	def_bool y
+	depends on ARCH_MVEBU
+	select GPIO_GENERIC
+	select GENERIC_IRQ_CHIP
+
 config GPIO_MXC
 	def_bool y
 	depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..1a33e67 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSIC)		+= gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)	+= gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2.o
+obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
 obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
new file mode 100644
index 0000000..71ff07f
--- /dev/null
+++ b/drivers/gpio/gpio-mvebu.c
@@ -0,0 +1,679 @@
+/*
+ * GPIO driver for Marvell SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This driver is a fairly straightforward GPIO driver for the
+ * complete family of Marvell EBU SoC platforms (Orion, Dove,
+ * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
+ * driver is the different register layout that exists between the
+ * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
+ * platforms (MV78200 from the Discovery family and the Armada
+ * XP). Therefore, this driver handles three variants of the GPIO
+ * block:
+ * - the basic variant, called "orion-gpio", with the simplest
+ *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
+ *   non-SMP Discovery systems
+ * - the mv78200 variant for MV78200 Discovery systems. This variant
+ *   turns the edge mask and level mask registers into CPU0 edge
+ *   mask/level mask registers, and adds CPU1 edge mask/level mask
+ *   registers.
+ * - the armadaxp variant for Armada XP systems. This variant keeps
+ *   the normal cause/edge mask/level mask registers when the global
+ *   interrupts are used, but adds per-CPU cause/edge mask/level mask
+ *   registers n a separate memory area for the per-CPU GPIO
+ *   interrupts.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF		0x0000
+#define GPIO_IO_CONF_OFF	0x0004
+#define GPIO_BLINK_EN_OFF	0x0008
+#define GPIO_IN_POL_OFF		0x000c
+#define GPIO_DATA_IN_OFF	0x0010
+#define GPIO_EDGE_CAUSE_OFF	0x0014
+#define GPIO_EDGE_MASK_OFF	0x0018
+#define GPIO_LEVEL_MASK_OFF	0x001c
+
+/* The MV78200 has per-CPU registers for edge mask and level mask */
+#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
+#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
+
+/* The Armada XP has per-CPU registers for interrupt cause, interrupt
+ * mask and interrupt level mask. Those are relative to the
+ * percpu_membase. */
+#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
+#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
+#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
+
+#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
+#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
+#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+
+#define MVEBU_MAX_GPIO_PER_BANK         32
+
+struct mvebu_gpio_chip {
+	struct gpio_chip   chip;
+	spinlock_t	   lock;
+	void __iomem	  *membase;
+	void __iomem	  *percpu_membase;
+	unsigned int       irqbase;
+	struct irq_domain *domain;
+	int                soc_variant;
+};
+
+/*
+ * Functions returning addresses of individual registers for a given
+ * GPIO controller.
+ */
+static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_OUT_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IO_CONF_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IN_POL_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_DATA_IN_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_EDGE_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_LEVEL_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+/*
+ * Functions implementing the gpio_chip methods
+ */
+
+int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+	return pinctrl_request_gpio(chip->base + pin);
+}
+
+void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
+{
+	pinctrl_free_gpio(chip->base + pin);
+}
+
+static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	u32 u;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+	if (value)
+		u |= 1 << pin;
+	else
+		u &= ~(1 << pin);
+	writel_relaxed(u, mvebu_gpioreg_out(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+}
+
+static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	u32 u;
+
+	if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
+		u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
+			readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+	} else {
+		u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+	}
+
+	return (u >> pin) & 1;
+}
+
+static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an input GPIO */
+	ret = pinctrl_gpio_direction_input(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+	u |= 1 << pin;
+	writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+				       int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an output GPIO */
+	ret = pinctrl_gpio_direction_output(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+	u &= ~(1 << pin);
+	writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	return irq_create_mapping(mvchip->domain, pin);
+}
+
+/*
+ * Functions implementing the irq_chip methods
+ */
+static void mvebu_gpio_irq_ack(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = ~(1 << (d->irq - gc->irq_base));
+
+	irq_gc_lock(gc);
+	writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+	irq_gc_unlock(gc);
+}
+
+/*****************************************************************************
+ * MVEBU GPIO IRQ
+ *
+ * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ *                     Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
+ *                     Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ *                     the polarity to catch the next line transaction.
+ *                     This is a race condition that might not perfectly
+ *                     work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ *                    EDGE  cause    mask
+ *        data-in   /--------| |-----| |----\
+ *     -----| |-----                         ---- to main cause reg
+ *           X      \----------------| |----/
+ *        polarity    LEVEL          mask
+ *
+ ****************************************************************************/
+
+static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct irq_chip_type *ct = irq_data_get_chip_type(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	int pin;
+	u32 u;
+
+	pin = d->hwirq - mvchip->irqbase;
+
+	u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
+	if (!u) {
+		return -EINVAL;
+	}
+
+	type &= IRQ_TYPE_SENSE_MASK;
+	if (type == IRQ_TYPE_NONE)
+		return -EINVAL;
+
+	/* Check if we need to change chip and handler */
+	if (!(ct->type & type))
+		if (irq_setup_alt_chip(d, type))
+			return -EINVAL;
+
+	/*
+	 * Configure interrupt polarity.
+	 */
+	switch(type) {
+	case IRQ_TYPE_EDGE_RISING:
+	case IRQ_TYPE_LEVEL_HIGH:
+		u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+		u &= ~(1 << pin);
+		writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+	case IRQ_TYPE_EDGE_FALLING:
+	case IRQ_TYPE_LEVEL_LOW:
+		u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+		u |= 1 << pin;
+		writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+	case IRQ_TYPE_EDGE_BOTH: {
+		u32 v;
+
+		v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
+			readl_relaxed(mvebu_gpioreg_data_in(mvchip));
+
+		/*
+		 * set initial polarity based on current input level
+		 */
+		u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+		if (v & (1 << pin))
+			u |= 1 << pin;		/* falling */
+		else
+			u &= ~(1 << pin);	/* rising */
+		writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+	}
+	}
+	return 0;
+}
+
+static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+	u32 cause, type;
+	int i;
+
+	if (mvchip == NULL)
+		return;
+
+	cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
+		readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
+	cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
+		readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
+
+	for (i = 0; i < mvchip->chip.ngpio; i++) {
+		int irq;
+
+		irq = mvchip->irqbase + i;
+
+		if (!(cause & (1 << i)))
+			continue;
+
+		type = irqd_get_trigger_type(irq_get_irq_data(irq));
+		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+			/* Swap polarity (race with GPIO line) */
+			u32 polarity;
+
+			polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+			polarity ^= 1 << i;
+			writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
+		}
+		generic_handle_irq(irq);
+	}
+}
+
+static struct platform_device_id mvebu_gpio_ids[] = {
+	{
+		.name = "orion-gpio",
+	}, {
+		.name = "mv78200-gpio",
+	}, {
+		.name = "armadaxp-gpio",
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
+
+static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
+	{
+		.compatible = "marvell,orion-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
+	},
+	{
+		.compatible = "marvell,mv78200-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
+	},
+	{
+		.compatible = "marvell,armadaxp-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
+	},
+	{
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
+
+static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
+{
+	struct mvebu_gpio_chip *mvchip;
+	const struct of_device_id *match;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *res;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	unsigned int ngpios;
+	int soc_variant;
+	int i, cpu, id;
+
+	match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
+	if (match)
+		soc_variant = (int) match->data;
+	else
+		soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (! res) {
+		dev_err(&pdev->dev, "Cannot get memory resource\n");
+		return -ENODEV;
+	}
+
+	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
+	if (! mvchip){
+		dev_err(&pdev->dev, "Cannot allocate memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
+		dev_err(&pdev->dev, "Missing ngpios OF property\n");
+		return -ENODEV;
+	}
+
+	id = of_alias_get_id(pdev->dev.of_node, "gpio");
+	if (id < 0) {
+		dev_err(&pdev->dev, "Couldn't get OF id\n");
+		return id;
+	}
+
+	mvchip->soc_variant = soc_variant;
+	mvchip->chip.label = dev_name(&pdev->dev);
+	mvchip->chip.dev = &pdev->dev;
+	mvchip->chip.request = mvebu_gpio_request;
+	mvchip->chip.direction_input = mvebu_gpio_direction_input;
+	mvchip->chip.get = mvebu_gpio_get;
+	mvchip->chip.direction_output = mvebu_gpio_direction_output;
+	mvchip->chip.set = mvebu_gpio_set;
+	mvchip->chip.to_irq = mvebu_gpio_to_irq;
+	mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
+	mvchip->chip.ngpio = ngpios;
+	mvchip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+	mvchip->chip.of_node = np;
+#endif
+
+	spin_lock_init(&mvchip->lock);
+	mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
+	if (! mvchip->membase) {
+		dev_err(&pdev->dev, "Cannot ioremap\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	/* The Armada XP has a second range of registers for the
+	 * per-CPU registers */
+	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (! res) {
+			dev_err(&pdev->dev, "Cannot get memory resource\n");
+			kfree(mvchip->chip.label);
+			return -ENODEV;
+		}
+
+		mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
+		if (! mvchip->percpu_membase) {
+			dev_err(&pdev->dev, "Cannot ioremap\n");
+			kfree(mvchip->chip.label);
+			return -ENOMEM;
+		}
+	}
+
+	/*
+	 * Mask and clear GPIO interrupts.
+	 */
+	switch(soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		for (cpu = 0; cpu < 2; cpu++) {
+			writel_relaxed(0, mvchip->membase +
+				       GPIO_EDGE_MASK_MV78200_OFF(cpu));
+			writel_relaxed(0, mvchip->membase +
+				       GPIO_LEVEL_MASK_MV78200_OFF(cpu));
+		}
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		for (cpu = 0; cpu < 4; cpu++) {
+			writel_relaxed(0, mvchip->percpu_membase +
+				       GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
+			writel_relaxed(0, mvchip->percpu_membase +
+				       GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
+			writel_relaxed(0, mvchip->percpu_membase +
+				       GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
+		}
+		break;
+	default:
+		BUG();
+	}
+
+	gpiochip_add(&mvchip->chip);
+
+	/* Some gpio controllers do not provide irq support */
+	if (!of_irq_count(np))
+		return 0;
+
+	/* Setup the interrupt handlers. Each chip can have up to 4
+	 * interrupt handlers, with each handler dealing with 8 GPIO
+	 * pins. */
+	for (i = 0; i < 4; i++) {
+		int irq;
+		irq = platform_get_irq(pdev, i);
+		if (irq < 0)
+			continue;
+		irq_set_handler_data(irq, mvchip);
+		irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
+	}
+
+	mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
+	if (mvchip->irqbase < 0) {
+		dev_err(&pdev->dev, "no irqs\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
+				    mvchip->membase, handle_level_irq);
+	if (! gc) {
+		dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc->private = mvchip;
+	ct = &gc->chip_types[0];
+	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->chip.name = mvchip->chip.label;
+
+	ct = &gc->chip_types[1];
+	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+	ct->chip.irq_ack = mvebu_gpio_irq_ack;
+	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->handler = handle_edge_irq;
+	ct->chip.name = mvchip->chip.label;
+
+	irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+	/* Setup irq domain on top of the generic chip. */
+	mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
+					       mvchip->irqbase, 0,
+					       &irq_domain_simple_ops,
+					       mvchip);
+	if (!mvchip->domain) {
+		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
+			mvchip->chip.label);
+		irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
+					IRQ_LEVEL | IRQ_NOPROBE);
+		kfree(gc);
+		kfree(mvchip->chip.label);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct platform_driver mvebu_gpio_driver = {
+	.driver		= {
+		.name	        = "mvebu-gpio",
+		.owner	        = THIS_MODULE,
+		.of_match_table = mvebu_gpio_of_match,
+	},
+	.probe		= mvebu_gpio_probe,
+	.id_table	= mvebu_gpio_ids,
+};
+
+static int __init mvebu_gpio_init(void)
+{
+	return platform_driver_register(&mvebu_gpio_driver);
+}
+postcore_initcall(mvebu_gpio_init);
-- 
1.7.9.5

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Thomas Petazzoni]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/gpio/gpio-mvebu.txt        |   45 ++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 0000000..595be9e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,45 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
+  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
+  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
+  370. "marvell,mv78200-gpio" should be used for the Discovery
+  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
+  SoCs (MV78230, MV78260, MV78460).
+
+- reg: Address and length of the register set for the device. Only one
+  entry is expected, except for the "marvell,armadaxp-gpio" variant
+  for which two entries are expected: one for the general registers,
+  one for the per-cpu registers.
+
+- interrupts: The list of interrupts that are used for all the pins
+  managed by this GPIO bank. There can be more than one interrupt
+  (example: 1 interrupt per 8 pins on Armada XP, which means 4
+  interrupts per bank of 32 GPIOs).
+
+- interrupt-controller: identifies the node as an interrupt controller
+
+- #interrupt-cells: specifies the number of celles needed to encode an
+   interrupt source
+
+- gpio-controller: marks the device node as a gpio controller
+
+- ngpios: number of GPIOs this controller has
+
+- #gpio-cells: Should be two. The first is the pin number. The second
+   is reserved for flags, unused at the moment.
+
+Example:
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
-- 
1.7.9.5

[PATCH v3 3/5] arm: mvebu: use GPIO support now that a driver is available

[Thomas Petazzoni]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
---
 arch/arm/Kconfig                        |    1 +
 arch/arm/mach-mvebu/include/mach/gpio.h |    1 +
 2 files changed, 2 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2eb3f6b..d00d1a3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -575,6 +575,7 @@ config ARCH_MVEBU
 	select COMMON_CLK
 	select PLAT_ORION
 	select PINCTRL
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	help
 	  Support for the Marvell SoC Family with device tree support
 
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
-- 
1.7.9.5

[PATCH v3 4/5] arm: mvebu: add DT information for GPIO banks on Armada 370 and XP

[Thomas Petazzoni]

The gpioX aliases are needed so that the driver can use
of_alias_get_id() to get a 0-based number of the GPIO bank, which we
then use to compute the base GPIO of the bank being probed. This is
similar to what gpio-mxs.c is doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-370.dtsi        |   36 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   39 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   39 ++++++++++++++++++++++++++++++
 4 files changed, 141 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 2bfb904..af34cdb 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
 
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021870 0x58>;
@@ -35,6 +41,36 @@
 		pinctrl {
 			compatible = "marvell,mv88f6710-pinctrl";
 			reg = <0xd0018000 0x38>;
+	        };
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018100 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <82>, <83>, <84>, <85>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018140 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <87>, <88>, <89>, <90>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018180 0x40>;
+			ngpios = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <91>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 38ede3d..05a1f27 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -19,10 +19,37 @@
 	model = "Marvell Armada XP MV78230 SoC";
 	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
 
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+	};
+
 	soc {
 		pinctrl {
 			compatible = "marvell,mv78230-pinctrl";
 			reg = <0xd0018000 0x38>;
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <17>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index b2eafcd..fe28ff2 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -19,10 +19,49 @@
 	model = "Marvell Armada XP MV78260 SoC";
 	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
 
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
 	soc {
 		pinctrl {
 			compatible = "marvell,mv78260-pinctrl";
 			reg = <0xd0018000 0x38>;
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index cf8624d..e55b310 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -19,10 +19,49 @@
 	model = "Marvell Armada XP MV78460 SoC";
 	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
 	soc {
 		pinctrl {
 			compatible = "marvell,mv78460-pinctrl";
 			reg = <0xd0018000 0x38>;
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
  };
-- 
1.7.9.5

[PATCH v3 5/5] arm: mvebu: add gpio support in defconfig

[Thomas Petazzoni]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
---
 arch/arm/configs/mvebu_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31..7bcf850 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-- 
1.7.9.5

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Rob Herring]

On 09/13/2012 10:54 AM, Thomas Petazzoni wrote:
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: Linus Walleij <linus.walleij@stericsson.com>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> ---

Grant is pretty much offline right now.

Acked-by: Rob Herring <rob.herring@calxeda.com>

>  .../devicetree/bindings/gpio/gpio-mvebu.txt        |   45 ++++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> new file mode 100644
> index 0000000..595be9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> @@ -0,0 +1,45 @@
> +* Marvell EBU GPIO controller
> +
> +Required properties:
> +
> +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
> +  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
> +  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
> +  370. "marvell,mv78200-gpio" should be used for the Discovery
> +  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
> +  SoCs (MV78230, MV78260, MV78460).
> +
> +- reg: Address and length of the register set for the device. Only one
> +  entry is expected, except for the "marvell,armadaxp-gpio" variant
> +  for which two entries are expected: one for the general registers,
> +  one for the per-cpu registers.
> +
> +- interrupts: The list of interrupts that are used for all the pins
> +  managed by this GPIO bank. There can be more than one interrupt
> +  (example: 1 interrupt per 8 pins on Armada XP, which means 4
> +  interrupts per bank of 32 GPIOs).
> +
> +- interrupt-controller: identifies the node as an interrupt controller
> +
> +- #interrupt-cells: specifies the number of celles needed to encode an
> +   interrupt source
> +
> +- gpio-controller: marks the device node as a gpio controller
> +
> +- ngpios: number of GPIOs this controller has
> +
> +- #gpio-cells: Should be two. The first is the pin number. The second
> +   is reserved for flags, unused at the moment.
> +
> +Example:
> +
> +		gpio0: gpio at d0018100 {
> +			compatible = "marvell,armadaxp-gpio";
> +			reg = <0xd0018100 0x40>,
> +			    <0xd0018800 0x30>;
> +			ngpios = <32>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			interrupts = <16>, <17>, <18>, <19>;
> +		};
> 

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Thomas Petazzoni]

Dear Rob Herring,

On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote:
> On 09/13/2012 10:54 AM, Thomas Petazzoni wrote:
> > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Cc: Grant Likely <grant.likely@secretlab.ca>
> > Cc: Linus Walleij <linus.walleij@stericsson.com>
> > Cc: Andrew Lunn <andrew@lunn.ch>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Gregory Clement <gregory.clement@free-electrons.com>
> > ---
> 
> Grant is pretty much offline right now.

Yes, I know, but MAINTAINERS does not mention an alternate maintainer
for the GPIO subsystem. Who is the interim maintainer that will
ultimately have to ack/nack those patches?

> Acked-by: Rob Herring <rob.herring@calxeda.com>

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Rob Herring]

On 09/13/2012 03:30 PM, Thomas Petazzoni wrote:
> Dear Rob Herring,
> 
> On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote:
>> On 09/13/2012 10:54 AM, Thomas Petazzoni wrote:
>>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>>> Cc: Grant Likely <grant.likely@secretlab.ca>
>>> Cc: Linus Walleij <linus.walleij@stericsson.com>
>>> Cc: Andrew Lunn <andrew@lunn.ch>
>>> Cc: Jason Cooper <jason@lakedaemon.net>
>>> Cc: Gregory Clement <gregory.clement@free-electrons.com>
>>> ---
>>
>> Grant is pretty much offline right now.
> 
> Yes, I know, but MAINTAINERS does not mention an alternate maintainer
> for the GPIO subsystem. Who is the interim maintainer that will
> ultimately have to ack/nack those patches?

Linus W. is.

Rob

[PATCH v3 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs

[Linus Walleij]

On Thu, Sep 13, 2012 at 5:54 PM, Thomas Petazzoni
<thomas.petazzoni@free-electrons.com> wrote:

> This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
> and is designed to be compatible with all Marvell EBU SoCs: Orion,
> Kirkwood, Dove, Armada 370/XP and Discovery.
>
> It has been successfully tested on Dove and Armada XP at the moment.
>
> Compared to the plat-orion driver, this new driver has the following
> added benefits:
>
>  *) Support for Armada 370 and Armada XP
>  *) It is integrated with the mvebu pinctrl driver so that GPIO pins
>     are properly muxed, and the GPIO driver knows which GPIO pins are
>     output-only or input-only.
>  *) Properly placed in drivers/gpio
>  *) More extensible mechanism to support platform differences. The
>     plat-orion driver uses a simple mask-offset DT property, which
>     works fine for Discovery MV78200 but not for Armada XP. The new
>     driver uses different compatible strings to identify the different
>     variants of the GPIO controllers.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: Linus Walleij <linus.walleij@stericsson.com>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This looks very good to me, I'm probably unable to see any
further mistakes at this point:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Linus Walleij]

On Thu, Sep 13, 2012 at 10:34 PM, Rob Herring <robherring2@gmail.com> wrote:
> On 09/13/2012 03:30 PM, Thomas Petazzoni wrote:
>> Dear Rob Herring,
>>
>> On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote:
>>> On 09/13/2012 10:54 AM, Thomas Petazzoni wrote:
>>>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>>>> Cc: Grant Likely <grant.likely@secretlab.ca>
>>>> Cc: Linus Walleij <linus.walleij@stericsson.com>
>>>> Cc: Andrew Lunn <andrew@lunn.ch>
>>>> Cc: Jason Cooper <jason@lakedaemon.net>
>>>> Cc: Gregory Clement <gregory.clement@free-electrons.com>
>>>> ---
>>>
>>> Grant is pretty much offline right now.
>>
>> Yes, I know, but MAINTAINERS does not mention an alternate maintainer
>> for the GPIO subsystem. Who is the interim maintainer that will
>> ultimately have to ack/nack those patches?
>
> Linus W. is.

I stated Reviewed-by: on the GPIO patch, please merge it through the
Marvell tree (I guess that's the plan?)

Acked-by: on the rest FWIW, I'm no ARM SoC nor DT maintainer...

Yours,
Linus Walleij

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Thomas Petazzoni]

Dear Linus Walleij,

On Fri, 14 Sep 2012 15:17:09 +0200, Linus Walleij wrote:

> >> Yes, I know, but MAINTAINERS does not mention an alternate maintainer
> >> for the GPIO subsystem. Who is the interim maintainer that will
> >> ultimately have to ack/nack those patches?
> >
> > Linus W. is.
> 
> I stated Reviewed-by: on the GPIO patch, please merge it through the
> Marvell tree (I guess that's the plan?)

Yes, I guess it's the easiest plan (Jason ? Andrew ?). We however need
Acks on the pinctrl patch series as well, since this one depends on it.

Thanks a lot for your review!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Stephen Warren]

On 09/13/2012 09:54 AM, Thomas Petazzoni wrote:

> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

> +- #interrupt-cells: specifies the number of celles needed to encode an
> +   interrupt source

s/celles/cells/

What value should this property contain for this driver, and what do
those cells mean?

This property is missing from the example below.

> +		gpio0: gpio at d0018100 {
> +			compatible = "marvell,armadaxp-gpio";
> +			reg = <0xd0018100 0x40>,
> +			    <0xd0018800 0x30>;
> +			ngpios = <32>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			interrupts = <16>, <17>, <18>, <19>;
> +		};

[PATCH v3 4/5] arm: mvebu: add DT information for GPIO banks on Armada 370 and XP

[Stephen Warren]

On 09/13/2012 09:54 AM, Thomas Petazzoni wrote:
> The gpioX aliases are needed so that the driver can use
> of_alias_get_id() to get a 0-based number of the GPIO bank, which we
> then use to compute the base GPIO of the bank being probed. This is
> similar to what gpio-mxs.c is doing.

#interrupt-cells is missing from all the gpio nodes here too.

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Jason Cooper]

On Fri, Sep 14, 2012 at 04:54:08PM +0200, Thomas Petazzoni wrote:
> Dear Linus Walleij,
> 
> On Fri, 14 Sep 2012 15:17:09 +0200, Linus Walleij wrote:
> 
> > >> Yes, I know, but MAINTAINERS does not mention an alternate maintainer
> > >> for the GPIO subsystem. Who is the interim maintainer that will
> > >> ultimately have to ack/nack those patches?
> > >
> > > Linus W. is.
> > 
> > I stated Reviewed-by: on the GPIO patch, please merge it through the
> > Marvell tree (I guess that's the plan?)
> 
> Yes, I guess it's the easiest plan (Jason ? Andrew ?). We however need
> Acks on the pinctrl patch series as well, since this one depends on it.

Yes, that's the plan.  I'm currently waiting for my previous series of
pull requests to get pulled before I start pulling in anything else.

thx,

Jason.

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Andrew Lunn]

> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> @@ -0,0 +1,45 @@
> +* Marvell EBU GPIO controller
> +
> +Required properties:
> +
> +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
> +  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
> +  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
> +  370. "marvell,mv78200-gpio" should be used for the Discovery
> +  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
> +  SoCs (MV78230, MV78260, MV78460).
> +
> +- reg: Address and length of the register set for the device. Only one
> +  entry is expected, except for the "marvell,armadaxp-gpio" variant
> +  for which two entries are expected: one for the general registers,
> +  one for the per-cpu registers.
> +
> +- interrupts: The list of interrupts that are used for all the pins
> +  managed by this GPIO bank. There can be more than one interrupt
> +  (example: 1 interrupt per 8 pins on Armada XP, which means 4
> +  interrupts per bank of 32 GPIOs).
> +
> +- interrupt-controller: identifies the node as an interrupt controller
> +
> +- #interrupt-cells: specifies the number of celles needed to encode an
> +   interrupt source

Hi Thomas

Should this be #gpio-cells? The example below does not have
#interrupt-cells?

	Andrew

> +
> +- gpio-controller: marks the device node as a gpio controller
> +
> +- ngpios: number of GPIOs this controller has
> +
> +- #gpio-cells: Should be two. The first is the pin number. The second
> +   is reserved for flags, unused at the moment.
> +
> +Example:
> +
> +		gpio0: gpio at d0018100 {
> +			compatible = "marvell,armadaxp-gpio";
> +			reg = <0xd0018100 0x40>,
> +			    <0xd0018800 0x30>;
> +			ngpios = <32>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			interrupts = <16>, <17>, <18>, <19>;
> +		};
> -- 
> 1.7.9.5
> 

[PATCH v3 2/5] Documentation: add description of DT binding for the gpio-mvebu driver

[Sebastian Hesselbarth]

On 09/16/2012 09:56 AM, Andrew Lunn wrote:
>> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
>> @@ -0,0 +1,45 @@
>> +* Marvell EBU GPIO controller
>> ...
>> +- interrupt-controller: identifies the node as an interrupt controller
>> +
>> +- #interrupt-cells: specifies the number of celles needed to encode an
>> +   interrupt source
>
> Hi Thomas
>
> Should this be #gpio-cells? The example below does not have
> #interrupt-cells?

It should be both. #gpio-cells to encode pin-offset within the gpio controller
and polarity, #interrupt-cells to encode irq number.

Sebastian