[PATCH 0/2] gpio: Add EIO GPIO support

[PATCH 0/2] gpio: Add EIO GPIO support

[Shubhrajyoti Datta]

Add the EIO GPIO support.
Add the dt description and the compatible to the driver.


Shubhrajyoti Datta (2):
  dt-bindings: gpio: Add eio gpio node to gpio-zynq
  gpio: zynq: Add eio gpio support

 .../devicetree/bindings/gpio/gpio-zynq.yaml        | 14 +++++++++++++-
 drivers/gpio/gpio-zynq.c                           | 12 ++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH 1/2] dt-bindings: gpio: Add eio gpio node to gpio-zynq

[Shubhrajyoti Datta]

Add the EIO gpio node to the device tree.
The EIO GPIO block exposes only bank 0 and bank 1 to
multiplexed I/O pins, providing a fixed total of 52 GPIO lines
(2 banks × 26 pins). Enforce this hardware constraint by requiring
exactly 52 entries in gpio-line-names for the EIO variant.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
---

 .../devicetree/bindings/gpio/gpio-zynq.yaml        | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
index 5e2496379a3c..b8dd279753a5 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
@@ -16,6 +16,7 @@ properties:
       - xlnx,zynqmp-gpio-1.0
       - xlnx,versal-gpio-1.0
       - xlnx,pmc-gpio-1.0
+      - xlnx,eio-gpio-1.0
 
   reg:
     maxItems: 1
@@ -30,7 +31,7 @@ properties:
 
   gpio-line-names:
     description: strings describing the names of each gpio line
-    minItems: 58
+    minItems: 52
     maxItems: 174
 
   interrupt-controller: true
@@ -89,6 +90,17 @@ allOf:
           minItems: 116
           maxItems: 116
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,eio-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 52
+          maxItems: 52
+
 required:
   - compatible
   - reg
-- 
2.34.1

[PATCH 2/2] gpio: zynq: Add eio gpio support

[Shubhrajyoti Datta]

Add support for the EIO GPIO controller found on
xa2ve3288 silicon.

The EIO GPIO block provides access to multiplexed I/O pins exposed
through the EIO interface. Only bank 0 and bank 1 are connected to
external MIO pins, with 26 GPIOs per bank (52 GPIOs total). This
change extends the Zynq GPIO driver to support the EIO GPIO
variant.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
---

 drivers/gpio/gpio-zynq.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
index 571e366624d2..8118ae3412c2 100644
--- a/drivers/gpio/gpio-zynq.c
+++ b/drivers/gpio/gpio-zynq.c
@@ -25,6 +25,7 @@
 #define VERSAL_GPIO_MAX_BANK	4
 #define PMC_GPIO_MAX_BANK	5
 #define VERSAL_UNUSED_BANKS	2
+#define EIO_GPIO_MAX_BANK	2
 
 #define ZYNQ_GPIO_BANK0_NGPIO	32
 #define ZYNQ_GPIO_BANK1_NGPIO	22
@@ -818,6 +819,16 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
 	RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, zynq_gpio_runtime_resume, NULL)
 };
 
+static const struct zynq_platform_data eio_gpio_def = {
+	.label = "eio_gpio",
+	.ngpio = 52,
+	.max_bank = EIO_GPIO_MAX_BANK,
+	.bank_min[0] = 0,
+	.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
+	.bank_min[1] = 26,
+	.bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
+};
+
 static const struct zynq_platform_data versal_gpio_def = {
 	.label = "versal_gpio",
 	.quirks = GPIO_QUIRK_VERSAL,
@@ -882,6 +893,7 @@ static const struct of_device_id zynq_gpio_of_match[] = {
 	{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
 	{ .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
 	{ .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
+	{ .compatible = "xlnx,eio-gpio-1.0", .data = &eio_gpio_def },
 	{ /* end of table */ }
 };
 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
-- 
2.34.1

Re: [PATCH 1/2] dt-bindings: gpio: Add eio gpio node to gpio-zynq

[Krzysztof Kozlowski]

On 02/04/2026 18:38, Shubhrajyoti Datta wrote:
> Add the EIO gpio node to the device tree.

What is EIO? A name of new SoC? Or you forgot to include the SoC here?


> The EIO GPIO block exposes only bank 0 and bank 1 to
> multiplexed I/O pins, providing a fixed total of 52 GPIO lines
> (2 banks × 26 pins). Enforce this hardware constraint by requiring
> exactly 52 entries in gpio-line-names for the EIO variant.

Don't describe the syntax. We can read the diff.

> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> ---
> 
>  .../devicetree/bindings/gpio/gpio-zynq.yaml        | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> index 5e2496379a3c..b8dd279753a5 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> @@ -16,6 +16,7 @@ properties:
>        - xlnx,zynqmp-gpio-1.0
>        - xlnx,versal-gpio-1.0
>        - xlnx,pmc-gpio-1.0
> +      - xlnx,eio-gpio-1.0

Please keep some sane ordering.

>  
Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: gpio: Add eio gpio node to gpio-zynq

[Krzysztof Kozlowski]

On 02/04/2026 18:46, Krzysztof Kozlowski wrote:
> On 02/04/2026 18:38, Shubhrajyoti Datta wrote:
>> Add the EIO gpio node to the device tree.
> 
> What is EIO? A name of new SoC? Or you forgot to include the SoC here?
> 
> 
>> The EIO GPIO block exposes only bank 0 and bank 1 to
>> multiplexed I/O pins, providing a fixed total of 52 GPIO lines
>> (2 banks × 26 pins). Enforce this hardware constraint by requiring
>> exactly 52 entries in gpio-line-names for the EIO variant.
> 
> Don't describe the syntax. We can read the diff.
> 

I also receive immediate Out of office bounces when replying. Please do
not cc addresses of people who cannot set up correctly their
autoresponder and send to open source Out of office messages.

Best regards,
Krzysztof