[PATCH V2 0/3] ARM: davinci: da850: add pinctrl support

[PATCH V2 0/3] ARM: davinci: da850: add pinctrl support

[Kumar, Anil]

This set of patches adds:

* Add pinctrl-single for handling Padconf registers.
* Add NAND node to export NAND functionality on da850 EVM.
* Add NAND pinctrl node to do pin mux according to pinctrl-single driver.


This series applies on top of tag next-20130107 git tree
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

This series is tested on da850 EVM.

Changes since V1:

 -Remove the binding documentation as already documented as part of
  Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
 -Enable PINCTRL Kconfig for MACH_DA8XX_DT platform only.
 -Fix the pinctrl driver node unit-address.
 -Make separate patch for da8xx_omapl_defconfig changes.  

Kumar, Anil (3):
  ARM: davinci: da850: add pinctrl driver entries
  ARM: davinci: da8xx defconfig: enable pinctrl config option
  ARM: davinci: da850: add NAND driver entries

 arch/arm/boot/dts/da850-evm.dts        |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/da850.dtsi           |   23 +++++++++++++++++++++++
 arch/arm/configs/da8xx_omapl_defconfig |    1 +
 arch/arm/mach-davinci/Kconfig          |    1 +
 4 files changed, 47 insertions(+), 0 deletions(-)

-- 
1.7.4.1

[PATCH V2 1/3] ARM: davinci: da850: add pinctrl driver entries

[Kumar, Anil]

For DT, DaVinci platform can use pinctrl-single driver for handling
padconf registers.

Enable PINCTRL Kconfig for MACH_DA8XX_DT platform. Add required
pinctrl DT entries in da850 dts file.

 Test procedure
  1)Populate DT file with NAND node information.
  2)Populate board DT file with pinmux information for NAND.
  3)Boot and confirm NAND is detected by the kernel.
  4)cat /proc/mtd to show partitions.

Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 37dc5a3... c7609d0... M	arch/arm/boot/dts/da850-evm.dts
:100644 100644 fbada87... e9c6e82... M	arch/arm/boot/dts/da850.dtsi
:100644 100644 0153950... a075b3e... M	arch/arm/mach-davinci/Kconfig
 arch/arm/boot/dts/da850-evm.dts |    3 +++
 arch/arm/boot/dts/da850.dtsi    |   10 ++++++++++
 arch/arm/mach-davinci/Kconfig   |    1 +
 3 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 37dc5a3..c7609d0 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -15,6 +15,9 @@
 	model = "DA850/AM1808/OMAP-L138 EVM";
 
 	soc {
+		pmx_core:pinmux at 1c14120 {
+			status = "okay";
+		};
 		serial0: serial at 1c42000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index fbada87..e9c6e82 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -29,6 +29,16 @@
 		#size-cells = <1>;
 		ranges = <0x0 0x01c00000 0x400000>;
 
+		pmx_core:pinmux at 1c14120 {
+			compatible = "pinctrl-single";
+			reg = <0x14120 0x50>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-single,bit-per-mux;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0xffffffff>;
+			status = "disabled";
+		};
 		serial0: serial at 1c42000 {
 			compatible = "ns16550a";
 			reg = <0x42000 0x100>;
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0153950..a075b3e 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -62,6 +62,7 @@ config MACH_DA8XX_DT
 	bool "Support DA8XX platforms using device tree"
 	default y
 	depends on ARCH_DAVINCI_DA8XX
+	select PINCTRL
 	help
 	  Say y here to include support for TI DaVinci DA850 based using
 	  Flattened Device Tree. More information at Documentation/devicetree
-- 
1.7.4.1

[PATCH V2 2/3] ARM: davinci: da8xx defconfig: enable pinctrl config option

[Kumar, Anil]

Enable pinctrl related config option in da8xx_omapl_defconfig

Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 f292239... 0892db4... M	arch/arm/configs/da8xx_omapl_defconfig
 arch/arm/configs/da8xx_omapl_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index f292239..0892db4 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -81,6 +81,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
+CONFIG_PINCTRL_SINGLE=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
-- 
1.7.4.1

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Kumar, Anil]

Add NAND driver entries to export NAND functionality on da850 EVM and
NAND pinctrl node to do pin mux according to pinctrl-single driver.

Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 c7609d0... 382a7da... M	arch/arm/boot/dts/da850-evm.dts
:100644 100644 e9c6e82... 16e2ac2... M	arch/arm/boot/dts/da850.dtsi
 arch/arm/boot/dts/da850-evm.dts |   19 +++++++++++++++++++
 arch/arm/boot/dts/da850.dtsi    |   13 +++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c7609d0..382a7da 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -28,4 +28,23 @@
 			status = "okay";
 		};
 	};
+	nand_cs3 at 62000000 {
+		status = "okay";
+	};
+};
+&pmx_core{
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&nand_cs3_pins
+	>;
+
+	nand_cs3_pins: pinmux_nand_pins {
+		pinctrl-single,bits = <
+			0x1c 0x00110000  0x00ff0000     /* EMA_OE, EMA_WE */
+			0x1c 0x00000110  0x00000ff0     /* EMA_CS[4],EMA_CS[3]*/
+			0x24 0x11111111  0xffffffff     /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3],
+							   EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */
+			0x30 0x01100000  0x0ff00000     /* EMA_A[1], EMA_A[2] */
+		>;
+	};
 };
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index e9c6e82..16e2ac2 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -67,4 +67,17 @@
 			status = "disabled";
 		};
 	};
+	nand_cs3 at 62000000 {
+		compatible = "ti,davinci-nand";
+		reg = <0x62000000 0x807ff
+			0x68000000 0x8000>;
+		ti,davinci-chipselect = <1>;
+		ti,davinci-mask-ale = <0>;
+		ti,davinci-mask-cle = <0>;
+		ti,davinci-mask-chipsel = <0>;
+		ti,davinci-ecc-mode = "hw";
+		ti,davinci-ecc-bits = <4>;
+		ti,davinci-nand-use-bbt;
+		status = "disabled";
+	};
 };
-- 
1.7.4.1

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Sekhar Nori]

On 1/8/2013 1:50 PM, Kumar, Anil wrote:
> Add NAND driver entries to export NAND functionality on da850 EVM and
> NAND pinctrl node to do pin mux according to pinctrl-single driver.

Subject line should have DT and da850 evm somewhere.
Otherwise NAND has been supported on DA850 for long.

> 
> Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
> ---
> :100644 100644 c7609d0... 382a7da... M	arch/arm/boot/dts/da850-evm.dts
> :100644 100644 e9c6e82... 16e2ac2... M	arch/arm/boot/dts/da850.dtsi
>  arch/arm/boot/dts/da850-evm.dts |   19 +++++++++++++++++++
>  arch/arm/boot/dts/da850.dtsi    |   13 +++++++++++++
>  2 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> index c7609d0..382a7da 100644
> --- a/arch/arm/boot/dts/da850-evm.dts
> +++ b/arch/arm/boot/dts/da850-evm.dts
> @@ -28,4 +28,23 @@
>  			status = "okay";
>  		};
>  	};
> +	nand_cs3 at 62000000 {
> +		status = "okay";
> +	};
> +};
> +&pmx_core{
> +	pinctrl-names = "default";
> +	pinctrl-0 = <
> +		&nand_cs3_pins
> +	>;

This means that the NAND pins are configured even if NAND is not
probed. Right? This can be moved into the nand_cs3 node to avoid that. 
And then when used with Linus Walleij's patch "drivers/pinctrl: grab 
default handles from device core" which should be accepted soon, the 
pins will be automatically setup when the NAND gets probed.

> +
> +	nand_cs3_pins: pinmux_nand_pins {
> +		pinctrl-single,bits = <
> +			0x1c 0x00110000  0x00ff0000     /* EMA_OE, EMA_WE */
> +			0x1c 0x00000110  0x00000ff0     /* EMA_CS[4],EMA_CS[3]*/
> +			0x24 0x11111111  0xffffffff     /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3],
> +							   EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */
> +			0x30 0x01100000  0x0ff00000     /* EMA_A[1], EMA_A[2] */
> +		>;
> +	};

I suspect a number of other boards using NAND on CS3 would have to 
repeat these configurations. It will be better to move them into the 
da850.dtsi file so it can be reused.

Since I am new to the DT and pinctrl stuff, I had to actually try these to 
make sure what I am suggesting isn't nonsense. I came up with this 
patch on top of your series. Please test it at your end and also see if you 
are happy with the changes.

Thanks,
Sekhar

---8<----
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 382a7da..52abb9d 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -30,21 +30,8 @@
 	};
 	nand_cs3@62000000 {
 		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&nand_cs3_pins>;
 	};
 };
-&pmx_core{
-	pinctrl-names = "default";
-	pinctrl-0 = <
-		&nand_cs3_pins
-	>;
 
-	nand_cs3_pins: pinmux_nand_pins {
-		pinctrl-single,bits = <
-			0x1c 0x00110000  0x00ff0000     /* EMA_OE, EMA_WE */
-			0x1c 0x00000110  0x00000ff0     /* EMA_CS[4],EMA_CS[3]*/
-			0x24 0x11111111  0xffffffff     /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3],
-							   EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */
-			0x30 0x01100000  0x0ff00000     /* EMA_A[1], EMA_A[2] */
-		>;
-	};
-};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 6ab9730..c4b21a8 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -38,7 +38,25 @@
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0xffffffff>;
 			status = "disabled";
+
+			nand_cs3_pins: pinmux_nand_pins {
+				pinctrl-single,bits = <
+					/* EMA_OE, EMA_WE */
+					0x1c 0x00110000  0x00ff0000
+					/* EMA_CS[4],EMA_CS[3]*/
+					0x1c 0x00000110  0x00000ff0
+					/*
+					 * EMA_D[0], EMA_D[1], EMA_D[2],
+					 * EMA_D[3], EMA_D[4], EMA_D[5],
+					 * EMA_D[6], EMA_D[7]
+					 */
+					0x24 0x11111111  0xffffffff
+					/* EMA_A[1], EMA_A[2] */
+					0x30 0x01100000  0x0ff00000
+				>;
+			};
 		};
+
 		serial0: serial at 1c42000 {
 			compatible = "ns16550a";
 			reg = <0x42000 0x100>;

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Kumar, Anil]

On Wed, Jan 09, 2013 at 18:17:46, Nori, Sekhar wrote:
> On 1/8/2013 1:50 PM, Kumar, Anil wrote:
> > Add NAND driver entries to export NAND functionality on da850 EVM and
> > NAND pinctrl node to do pin mux according to pinctrl-single driver.
> 
> Subject line should have DT and da850 evm somewhere.
> Otherwise NAND has been supported on DA850 for long.

I will update it in V3 of this patch series.

> 
> > 
> > Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
> > ---
> > :100644 100644 c7609d0... 382a7da... M	arch/arm/boot/dts/da850-evm.dts
> > :100644 100644 e9c6e82... 16e2ac2... M	arch/arm/boot/dts/da850.dtsi
> >  arch/arm/boot/dts/da850-evm.dts |   19 +++++++++++++++++++
> >  arch/arm/boot/dts/da850.dtsi    |   13 +++++++++++++
> >  2 files changed, 32 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> > index c7609d0..382a7da 100644
> > --- a/arch/arm/boot/dts/da850-evm.dts
> > +++ b/arch/arm/boot/dts/da850-evm.dts
> > @@ -28,4 +28,23 @@
> >  			status = "okay";
> >  		};
> >  	};
> > +	nand_cs3 at 62000000 {
> > +		status = "okay";
> > +	};
> > +};
> > +&pmx_core{
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <
> > +		&nand_cs3_pins
> > +	>;
> 
> This means that the NAND pins are configured even if NAND is not
> probed. Right?

Right 

> This can be moved into the nand_cs3 node to avoid that. 
> And then when used with Linus Walleij's patch "drivers/pinctrl: grab 
> default handles from device core" which should be accepted soon, the 
> pins will be automatically setup when the NAND gets probed.

It is better. I will do it in V3 of this patch series.

> 
> > +
> > +	nand_cs3_pins: pinmux_nand_pins {
> > +		pinctrl-single,bits = <
> > +			0x1c 0x00110000  0x00ff0000     /* EMA_OE, EMA_WE */
> > +			0x1c 0x00000110  0x00000ff0     /* EMA_CS[4],EMA_CS[3]*/
> > +			0x24 0x11111111  0xffffffff     /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3],
> > +							   EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */
> > +			0x30 0x01100000  0x0ff00000     /* EMA_A[1], EMA_A[2] */
> > +		>;
> > +	};
> 
> I suspect a number of other boards using NAND on CS3 would have to 
> repeat these configurations. It will be better to move them into the 
> da850.dtsi file so it can be reused.

> 
> Since I am new to the DT and pinctrl stuff, I had to actually try these to 
> make sure what I am suggesting isn't nonsense. I came up with this 
> patch on top of your series. Please test it at your end

Tested. It is working. 

> and also see if you 
> are happy with the changes.

I do not think that it is good idea to move NAND pin mux information
into da850.dtsi because this information is evm specific.
if we will use this approach then we must use the same approach for
other modules also as ASoC etc.   

Thanks,
Anil

> ---8<----
> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> index 382a7da..52abb9d 100644
> --- a/arch/arm/boot/dts/da850-evm.dts
> +++ b/arch/arm/boot/dts/da850-evm.dts
> @@ -30,21 +30,8 @@
>  	};
>  	nand_cs3 at 62000000 {
>  		status = "okay";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&nand_cs3_pins>;
>  	};
>  };
> -&pmx_core{
> -	pinctrl-names = "default";
> -	pinctrl-0 = <
> -		&nand_cs3_pins
> -	>;
>  
> -	nand_cs3_pins: pinmux_nand_pins {
> -		pinctrl-single,bits = <
> -			0x1c 0x00110000  0x00ff0000     /* EMA_OE, EMA_WE */
> -			0x1c 0x00000110  0x00000ff0     /* EMA_CS[4],EMA_CS[3]*/
> -			0x24 0x11111111  0xffffffff     /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3],
> -							   EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */
> -			0x30 0x01100000  0x0ff00000     /* EMA_A[1], EMA_A[2] */
> -		>;
> -	};
> -};
> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
> index 6ab9730..c4b21a8 100644
> --- a/arch/arm/boot/dts/da850.dtsi
> +++ b/arch/arm/boot/dts/da850.dtsi
> @@ -38,7 +38,25 @@
>  			pinctrl-single,register-width = <32>;
>  			pinctrl-single,function-mask = <0xffffffff>;
>  			status = "disabled";
> +
> +			nand_cs3_pins: pinmux_nand_pins {
> +				pinctrl-single,bits = <
> +					/* EMA_OE, EMA_WE */
> +					0x1c 0x00110000  0x00ff0000
> +					/* EMA_CS[4],EMA_CS[3]*/
> +					0x1c 0x00000110  0x00000ff0
> +					/*
> +					 * EMA_D[0], EMA_D[1], EMA_D[2],
> +					 * EMA_D[3], EMA_D[4], EMA_D[5],
> +					 * EMA_D[6], EMA_D[7]
> +					 */
> +					0x24 0x11111111  0xffffffff
> +					/* EMA_A[1], EMA_A[2] */
> +					0x30 0x01100000  0x0ff00000
> +				>;
> +			};
>  		};
> +
>  		serial0: serial at 1c42000 {
>  			compatible = "ns16550a";
>  			reg = <0x42000 0x100>;
> 

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Sekhar Nori]

On 1/10/2013 1:07 PM, Kumar, Anil wrote:
> On Wed, Jan 09, 2013 at 18:17:46, Nori, Sekhar wrote:

> I do not think that it is good idea to move NAND pin mux information
> into da850.dtsi because this information is evm specific.
> if we will use this approach then we must use the same approach for
> other modules also as ASoC etc.   

Why do you consider this EVM specific. IOW, which pins do you see
changing on another board? BTW, if there are additional pins needed than
what are listed, we can always add more pinux entries in the .dts files.
The pins present in dtsi file should the base case.

Thanks,
Sekhar

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Kumar, Anil]

On Thu, Jan 10, 2013 at 17:49:13, Nori, Sekhar wrote:
> On 1/10/2013 1:07 PM, Kumar, Anil wrote:
> > On Wed, Jan 09, 2013 at 18:17:46, Nori, Sekhar wrote:
> 
> > I do not think that it is good idea to move NAND pin mux information
> > into da850.dtsi because this information is evm specific.
> > if we will use this approach then we must use the same approach for
> > other modules also as ASoC etc.   
> 
> Why do you consider this EVM specific. IOW, which pins do you see
> changing on another board? BTW, if there are additional pins needed than
> what are listed, we can always add more pinux entries in the .dts files.
> The pins present in dtsi file should the base case.
 
Ok, we can use this approach for DaVinci as its SoC modules do not
have multiple pin configuration option. I will do the changes in 
next patch series.

Thanks,
Anil

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Sekhar Nori]

On 1/15/2013 4:06 PM, Kumar, Anil wrote:
> On Thu, Jan 10, 2013 at 17:49:13, Nori, Sekhar wrote:
>> On 1/10/2013 1:07 PM, Kumar, Anil wrote:
>>> On Wed, Jan 09, 2013 at 18:17:46, Nori, Sekhar wrote:
>>
>>> I do not think that it is good idea to move NAND pin mux information
>>> into da850.dtsi because this information is evm specific.
>>> if we will use this approach then we must use the same approach for
>>> other modules also as ASoC etc.   
>>
>> Why do you consider this EVM specific. IOW, which pins do you see
>> changing on another board? BTW, if there are additional pins needed than
>> what are listed, we can always add more pinux entries in the .dts files.
>> The pins present in dtsi file should the base case.
>  
> Ok, we can use this approach for DaVinci as its SoC modules do not
> have multiple pin configuration option. I will do the changes in 
> next patch series.

You could do this even if this was the case by defining multiple pin groups.

Thanks,
Sekhar

[PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries

[Linus Walleij]

On Wed, Jan 9, 2013 at 1:47 PM, Sekhar Nori <nsekhar@ti.com> wrote:
> On 1/8/2013 1:50 PM, Kumar, Anil wrote:

>> +&pmx_core{
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <
>> +             &nand_cs3_pins
>> +     >;
>
> This means that the NAND pins are configured even if NAND is not
> probed. Right? This can be moved into the nand_cs3 node to avoid that.
> And then when used with Linus Walleij's patch "drivers/pinctrl: grab
> default handles from device core" which should be accepted soon, the
> pins will be automatically setup when the NAND gets probed.

That is correct, I am waiting for Greg's ACK on the core grab patch
(maybe it's higher up in my mailbox) and some indication from Stephen
Warren that it doesn't break the Tegra, and I'll put it into linux-next.

Yours,
Linus Walleij