[PATCHv2 1/3] ARM: Orion: Hoist bridge interrupt handling out of the timer

[PATCHv2 1/3] ARM: Orion: Hoist bridge interrupt handling out of the timer

[Jason Gunthorpe]

The intent of this patch is to expose the other bridge cause
interrupts to users in the kernel.

- Add orion_bridge_irq_init to create a new edge triggered interrupt
  chip based on the bridge cause register
- Remove all interrupt register code from time.c and use normal
  interrupt functions instead
- Update the machines that use orion_time_init to call
  orion_bridge_irq_init and use the new signature

Tested on a Kirkwood platform.

I'm skeptical that MV78xx0 has a bridge interrupt cause/mask register,
it was setup so the timer code would touch those registers, so I've
preserved that, but prior to this patch the 'bridge cause register'
was only written to, never read. If it is wired-to-zero because it
doesn't exist then the timer will fail to function.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
 arch/arm/mach-dove/common.c                       |    7 ++-
 arch/arm/mach-dove/include/mach/bridge-regs.h     |    2 +-
 arch/arm/mach-dove/include/mach/irqs.h            |    9 +++-
 arch/arm/mach-kirkwood/common.c                   |    8 ++-
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    2 -
 arch/arm/mach-kirkwood/include/mach/irqs.h        |   14 ++++-
 arch/arm/mach-mv78xx0/common.c                    |   12 +++-
 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h  |    2 +-
 arch/arm/mach-mv78xx0/include/mach/irqs.h         |    9 +++-
 arch/arm/mach-orion5x/common.c                    |    8 ++-
 arch/arm/mach-orion5x/include/mach/bridge-regs.h  |    2 -
 arch/arm/mach-orion5x/include/mach/irqs.h         |    9 +++-
 arch/arm/plat-orion/include/plat/irq.h            |    3 +
 arch/arm/plat-orion/include/plat/time.h           |    4 +-
 arch/arm/plat-orion/irq.c                         |   70 +++++++++++++++++++++
 arch/arm/plat-orion/time.c                        |   46 +++-----------
 16 files changed, 149 insertions(+), 58 deletions(-)

v2 changes
- Defines for BRIDGE registers
- Re-order the bridge IRQs to follow the GPIO irqs, otherwise there
  will be problems when switching to DT
- Make orion_bridge_irq_init suitable for being DT bound, call
  irq_alloc_descs to get a dynamic range allocation.
- Use "orion_bridge" as the chip name
- I left orion_bridge_irq_init in the timer_init functions.
  For the DT boards there is no better place for it at this
  point, putting it in eg, kirkwood_init_irq, will not call
  it on the DT case and the board won't boot. The next patch
  provides a solution for the DT case so then we can safely
  move it.

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index f723fe1..6bad21b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -243,8 +243,11 @@ static int __init dove_find_tclk(void)
 static void __init dove_timer_init(void)
 {
 	dove_tclk = dove_find_tclk();
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_DOVE_BRIDGE, dove_tclk);
+	if (orion_bridge_irq_init(IRQ_DOVE_BRIDGE,
+				  IRQ_DOVE_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
+	orion_time_init(IRQ_DOVE_BRIDGE_TIMER1, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 99f259e..3bd4656 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,7 +26,7 @@
 #define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET		0x00000001
 
-#define  BRIDGE_INT_TIMER1_CLR	(~0x0004)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 
 #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF	0x0000
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 03d401d..f153de0 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -90,7 +90,14 @@
 #define NR_PMU_IRQS		7
 #define IRQ_DOVE_RTC		(IRQ_DOVE_PMU_START + 5)
 
-#define NR_IRQS			(IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+/*
+ * Bridge Interrupt Controller
+ */
+#define IRQ_DOVE_BRIDGE_START   (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+#define IRQ_DOVE_BRIDGE_TIMER1  (IRQ_DOVE_BRIDGE_START + 2)
+#define NR_BRIDGE_IRQS          6
+
+#define NR_IRQS			(IRQ_DOVE_BRIDGE_START + NR_BRIDGE_IRQS)
 
 
 #endif
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 906c22e..ccd3ed5 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -35,6 +35,7 @@
 #include <plat/time.h>
 #include <plat/addr-map.h>
 #include <linux/platform_data/dma-mv_xor.h>
+#include <plat/irq.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -534,8 +535,11 @@ static void __init kirkwood_timer_init(void)
 {
 	kirkwood_tclk = kirkwood_find_tclk();
 
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+	if (orion_bridge_irq_init(IRQ_KIRKWOOD_BRIDGE,
+				  IRQ_KIRKWOOD_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
+	orion_time_init(IRQ_KIRKWOOD_BRIDGE_TIMER1, kirkwood_tclk);
 }
 
 struct sys_timer kirkwood_timer = {
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 5c82b7d..fd66a56 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -29,8 +29,6 @@
 #define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ		0x0008
 
-#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
-
 #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF	0x0000
 #define IRQ_MASK_LOW_OFF	0x0004
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 2bf8161..82c5984 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -59,7 +59,19 @@
 #define IRQ_KIRKWOOD_GPIO_START	64
 #define NR_GPIO_IRQS		50
 
-#define NR_IRQS			(IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+/*
+ * Bridge Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_BRIDGE_START (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+#define IRQ_KIRKWOOD_BRIDGE_SELFINT   (IRQ_KIRKWOOD_BRIDGE_START + 0)
+#define IRQ_KIRKWOOD_BRIDGE_TIMER0    (IRQ_KIRKWOOD_BRIDGE_START + 1)
+#define IRQ_KIRKWOOD_BRIDGE_TIMER1    (IRQ_KIRKWOOD_BRIDGE_START + 2)
+#define IRQ_KIRKWOOD_BRIDGE_TIMERWD   (IRQ_KIRKWOOD_BRIDGE_START + 3)
+#define IRQ_KIRKWOOD_BRIDGE_ACCESSERR (IRQ_KIRKWOOD_BRIDGE_START + 4)
+#define IRQ_KIRKWOOD_BRIDGE_BIT64ERR  (IRQ_KIRKWOOD_BRIDGE_START + 5)
+#define NR_BRIDGE_IRQS          6
+
+#define NR_IRQS			(IRQ_KIRKWOOD_BRIDGE_START + NR_BRIDGE_IRQS)
 
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index d0cb485..e9c9ef7 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -25,6 +25,7 @@
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
+#include <plat/irq.h>
 #include "common.h"
 
 static int get_tclk(void);
@@ -338,8 +339,15 @@ void __init mv78xx0_init_early(void)
 
 static void __init_refok mv78xx0_timer_init(void)
 {
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_MV78XX0_TIMER_1, get_tclk());
+	/*
+	 * FIXME: MV78XX0 may not have a bridge cause register, in which case
+	 * the timer should run directly from IRQ_MV78XX0_TIMER_1
+	 */
+	if (orion_bridge_irq_init(IRQ_MV78XX0_TIMER_1,
+				  IRQ_MV78XX0_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
+	orion_time_init(IRQ_MV78XX0_BRIDGE_TIMER1, get_tclk());
 }
 
 struct sys_timer mv78xx0_timer = {
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 5f03484..787bd2a 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -20,7 +20,7 @@
 #define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET		0x00000001
 
-#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 
 #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF	0x0000
diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h
index fa1d422..1d70936 100644
--- a/arch/arm/mach-mv78xx0/include/mach/irqs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h
@@ -88,7 +88,14 @@
 #define IRQ_MV78XX0_GPIO_START	96
 #define NR_GPIO_IRQS		32
 
-#define NR_IRQS			(IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+/*
+ * Bridge Interrupt Controller
+ */
+#define IRQ_MV78XX0_BRIDGE_START   (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+#define IRQ_MV78XX0_BRIDGE_TIMER1  (IRQ_MV78XX0_BRIDGE_START + 2)
+#define NR_BRIDGE_IRQS             6
+
+#define NR_IRQS			(IRQ_MV78XX0_BRIDGE_START + NR_BRIDGE_IRQS)
 
 
 #endif
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b3eb3da..c95c6c1 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -35,6 +35,7 @@
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
+#include <plat/irq.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -221,8 +222,11 @@ static void __init orion5x_timer_init(void)
 {
 	orion5x_tclk = orion5x_find_tclk();
 
-	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_ORION5X_BRIDGE, orion5x_tclk);
+	if (orion_bridge_irq_init(IRQ_ORION5X_BRIDGE,
+				  IRQ_ORION5X_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
+	orion_time_init(IRQ_ORION5X_BRIDGE_TIMER1, orion5x_tclk);
 }
 
 struct sys_timer orion5x_timer = {
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 461fd69..0847182 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -28,8 +28,6 @@
 
 #define WDT_INT_REQ		0x0008
 
-#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
-
 #define MAIN_IRQ_CAUSE		(ORION5X_BRIDGE_VIRT_BASE + 0x200)
 
 #define MAIN_IRQ_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x204)
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h
index a6fa9d8..b8d53e6 100644
--- a/arch/arm/mach-orion5x/include/mach/irqs.h
+++ b/arch/arm/mach-orion5x/include/mach/irqs.h
@@ -54,7 +54,14 @@
 #define IRQ_ORION5X_GPIO_START	32
 #define NR_GPIO_IRQS		32
 
-#define NR_IRQS			(IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+/*
+ * Bridge Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE_START   (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+#define IRQ_ORION5X_BRIDGE_TIMER1  (IRQ_ORION5X_BRIDGE_START + 2)
+#define NR_BRIDGE_IRQS          6
+
+#define NR_IRQS			(IRQ_ORION5X_BRIDGE_START + NR_BRIDGE_IRQS)
 
 
 #endif
diff --git a/arch/arm/plat-orion/include/plat/irq.h b/arch/arm/plat-orion/include/plat/irq.h
index 50547e4..d86ae85 100644
--- a/arch/arm/plat-orion/include/plat/irq.h
+++ b/arch/arm/plat-orion/include/plat/irq.h
@@ -12,5 +12,8 @@
 #define __PLAT_IRQ_H
 
 void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
+int __init orion_bridge_irq_init(unsigned int bridge_irq, int irq_start,
+				 void __iomem *causeaddr,
+				 struct device_node *np);
 void __init orion_dt_init_irq(void);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 07527e4..c5ccc0a 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -13,8 +13,6 @@
 
 void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
-		     unsigned int irq, unsigned int tclk);
-
+void orion_time_init(unsigned int irq, unsigned int tclk);
 
 #endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 1867944..a903012 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
@@ -18,6 +19,75 @@
 #include <plat/irq.h>
 #include <plat/orion-gpio.h>
 
+#define BRIDGE_CAUSE_OFF 0
+#define BRIDGE_MASK_OFF  4
+#define BRIDGE_NUM_IRQS 6
+
+static void bridge_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	u32 cause;
+	int i;
+
+	cause = readl(gc->reg_base) & readl(gc->reg_base + BRIDGE_MASK_OFF);
+	for (i = 0; i < BRIDGE_NUM_IRQS; i++)
+		if ((cause & (1 << i)))
+			generic_handle_irq(i + gc->irq_base);
+}
+
+static void irq_gc_eoi_inv(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	u32 mask = 1 << (d->irq - gc->irq_base);
+	struct irq_chip_regs *regs;
+
+	regs = &container_of(d->chip, struct irq_chip_type, chip)->regs;
+	irq_gc_lock(gc);
+	irq_reg_writel(~mask, gc->reg_base + regs->eoi);
+	irq_gc_unlock(gc);
+}
+
+int __init orion_bridge_irq_init(unsigned int bridge_irq, int irq_start,
+				 void __iomem *causeaddr,
+				 struct device_node *np)
+{
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	int rc;
+
+	irq_start = irq_alloc_descs(irq_start, 0, BRIDGE_NUM_IRQS,
+				    NUMA_NO_NODE);
+	if (irq_start < 0)
+		return irq_start;
+	gc = irq_alloc_generic_chip("orion_bridge", 1, irq_start,
+				    causeaddr, handle_fasteoi_irq);
+	if (!gc)
+		return -ENOMEM;
+
+	ct = gc->chip_types;
+	ct->regs.mask = BRIDGE_MASK_OFF;
+	ct->regs.eoi = BRIDGE_CAUSE_OFF;
+	/* ACK and mask all interrupts */
+	writel(0, causeaddr);
+	writel(0, causeaddr + ct->regs.mask);
+	ct->chip.irq_eoi = irq_gc_eoi_inv;
+	ct->chip.irq_mask = irq_gc_mask_clr_bit;
+	ct->chip.irq_unmask = irq_gc_mask_set_bit;
+	irq_setup_generic_chip(gc, IRQ_MSK(BRIDGE_NUM_IRQS),
+			       IRQ_GC_INIT_MASK_CACHE,
+			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+	rc = irq_set_handler_data(bridge_irq, gc);
+	if (rc)
+		return rc;
+	irq_set_chained_handler(bridge_irq, bridge_irq_handler);
+
+	if (np)
+		irq_domain_add_legacy(np, gc->irq_cnt, gc->irq_base,
+				      0, &irq_domain_simple_ops, NULL);
+
+	return 0;
+}
+
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
 	struct irq_chip_generic *gc;
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 0f4fa86..da22aa4 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -17,15 +17,8 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/sched_clock.h>
-
-/*
- * MBus bridge block registers.
- */
-#define BRIDGE_CAUSE_OFF	0x0110
-#define BRIDGE_MASK_OFF		0x0114
-#define  BRIDGE_INT_TIMER0	 0x0002
-#define  BRIDGE_INT_TIMER1	 0x0004
-
+#include <linux/sched.h>
+#include <plat/time.h>
 
 /*
  * Timer block registers.
@@ -44,9 +37,8 @@
 /*
  * SoC-specific data.
  */
-static void __iomem *bridge_base;
-static u32 bridge_timer1_clr_mask;
 static void __iomem *timer_base;
+static unsigned int timer_irq;
 
 
 /*
@@ -82,11 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
 	/*
 	 * Clear and enable clockevent timer interrupt.
 	 */
-	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
-
-	u = readl(bridge_base + BRIDGE_MASK_OFF);
-	u |= BRIDGE_INT_TIMER1;
-	writel(u, bridge_base + BRIDGE_MASK_OFF);
+	enable_irq(timer_irq);
 
 	/*
 	 * Setup new clockevent timer value.
@@ -122,8 +110,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 		/*
 		 * Enable timer interrupt.
 		 */
-		u = readl(bridge_base + BRIDGE_MASK_OFF);
-		writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
+		enable_irq(timer_irq);
 
 		/*
 		 * Enable timer.
@@ -141,14 +128,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 		/*
 		 * Disable timer interrupt.
 		 */
-		u = readl(bridge_base + BRIDGE_MASK_OFF);
-		writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
-
-		/*
-		 * ACK pending timer interrupt.
-		 */
-		writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
-
+		disable_irq(timer_irq);
 	}
 	local_irq_restore(flags);
 }
@@ -164,10 +144,6 @@ static struct clock_event_device orion_clkevt = {
 
 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
 {
-	/*
-	 * ACK timer interrupt and call event handler.
-	 */
-	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 	orion_clkevt.event_handler(&orion_clkevt);
 
 	return IRQ_HANDLED;
@@ -186,16 +162,14 @@ orion_time_set_base(void __iomem *_timer_base)
 }
 
 void __init
-orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
-		unsigned int irq, unsigned int tclk)
+orion_time_init(unsigned int irq, unsigned int tclk)
 {
 	u32 u;
 
 	/*
 	 * Set SoC-specific data.
 	 */
-	bridge_base = _bridge_base;
-	bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
+	timer_irq = irq;
 
 	ticks_per_jiffy = (tclk + HZ/2) / HZ;
 
@@ -210,8 +184,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
 	 */
 	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
-	u = readl(bridge_base + BRIDGE_MASK_OFF);
-	writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
 	u = readl(timer_base + TIMER_CTRL_OFF);
 	writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
 	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
@@ -220,7 +192,7 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
 	/*
 	 * Setup clockevent timer (interrupt-driven).
 	 */
-	setup_irq(irq, &orion_timer_irq);
+	setup_irq(timer_irq, &orion_timer_irq);
 	orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
 	orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
 	orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
-- 
1.7.5.4

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Gunthorpe]

This adds the common DT code and board support for kirkwood and dove

- Add the marvell,orion-bridge-intc DT node to the DTSI file
- Make the call to orion_bridge_irq_init happen only in the non-DT
  case

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
 .../devicetree/bindings/arm/mrvl/intc.txt          |   21 ++++++++++++++++++++
 arch/arm/boot/dts/dove.dtsi                        |   10 +++++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   12 +++++++++++
 arch/arm/mach-dove/common.c                        |    4 ---
 arch/arm/mach-dove/irq.c                           |    5 ++++
 arch/arm/mach-kirkwood/common.c                    |    4 ---
 arch/arm/mach-kirkwood/irq.c                       |    5 ++++
 arch/arm/plat-orion/irq.c                          |   20 +++++++++++++++++++
 8 files changed, 73 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
index 8b53273..cf633f1 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/intc.txt
+++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
@@ -58,3 +58,24 @@ Example:
                 reg = <0xfed20204 0x04>,
 		      <0xfed20214 0x04>;
         };
+
+* Marvell Orion Bridge Interrupt controller
+
+Required properties
+- compatible :  Should be "marvell,orion-bridge-intc".
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. Supported value is <1>.
+- interrupt-controller : Declare this node to be an interrupt controller.
+- interrupts: The interrupt number the bridge is attached to on the main
+              controller.
+- reg : Interrupt cause address.
+
+Example:
+
+	bridge_intc: bridge_intc at 20110 {
+		compatible = "marvell,orion-bridge-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupts = <1>;
+		reg = <0x20110 0x08>;
+        };
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 5a00022..b726ba8 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -67,6 +67,8 @@
 			status = "disabled";
 		};
 
+		/* The interrupt controller stanzas are in an
+		 * order that matches irqs.h */
 		gpio0: gpio at d0400 {
 			compatible = "marvell,orion-gpio";
 			#gpio-cells = <2>;
@@ -93,6 +95,14 @@
 			ngpio = <8>;
 		};
 
+		bridge_intc: bridge_intc at 20110 {
+			compatible = "marvell,orion-bridge-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts = <0>;
+			reg = <0x20110 0x08>;
+		};
+
 		spi0: spi at 10600 {
 			compatible = "marvell,orion-spi";
 			#address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 4e5b815..854e532 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -19,6 +19,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		/* The interrupt controller stanzas are in an
+		 * order that matches irqs.h */
 		gpio0: gpio at 10100 {
 			compatible = "marvell,orion-gpio";
 			#gpio-cells = <2>;
@@ -37,6 +39,14 @@
 			interrupts = <39>, <40>, <41>;
 		};
 
+		bridge_intc: bridge_intc at 20110 {
+			compatible = "marvell,orion-bridge-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupts = <1>;
+			reg = <0x20110 0x08>;
+		};
+
 		serial at 12000 {
 			compatible = "ns16550a";
 			reg = <0x12000 0x100>;
@@ -73,6 +83,8 @@
 
 		wdt at 20300 {
 			compatible = "marvell,orion-wdt";
+			interrupt-parent = <&bridge_intc>;
+			interrupts = <3>;
 			reg = <0x20300 0x28>;
 			status = "okay";
 		};
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 6bad21b..b570211 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -243,10 +243,6 @@ static int __init dove_find_tclk(void)
 static void __init dove_timer_init(void)
 {
 	dove_tclk = dove_find_tclk();
-	if (orion_bridge_irq_init(IRQ_DOVE_BRIDGE,
-				  IRQ_DOVE_BRIDGE_START,
-				  BRIDGE_CAUSE, NULL))
-		panic("Unable to setup bridge irqs");
 	orion_time_init(IRQ_DOVE_BRIDGE_TIMER1, dove_tclk);
 }
 
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index bc4344a..bcb193f 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -139,4 +139,9 @@ void __init dove_init_irq(void)
 		set_irq_flags(i, IRQF_VALID);
 	}
 	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
+
+	if (orion_bridge_irq_init(IRQ_DOVE_BRIDGE,
+				  IRQ_DOVE_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index ccd3ed5..7398f8b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -535,10 +535,6 @@ static void __init kirkwood_timer_init(void)
 {
 	kirkwood_tclk = kirkwood_find_tclk();
 
-	if (orion_bridge_irq_init(IRQ_KIRKWOOD_BRIDGE,
-				  IRQ_KIRKWOOD_BRIDGE_START,
-				  BRIDGE_CAUSE, NULL))
-		panic("Unable to setup bridge irqs");
 	orion_time_init(IRQ_KIRKWOOD_BRIDGE_TIMER1, kirkwood_tclk);
 }
 
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 8847035..a1388ef 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -41,4 +41,9 @@ void __init kirkwood_init_irq(void)
 			IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
 	orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
 			IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
+
+	if (orion_bridge_irq_init(IRQ_KIRKWOOD_BRIDGE,
+				  IRQ_KIRKWOOD_BRIDGE_START,
+				  BRIDGE_CAUSE, NULL))
+		panic("Unable to setup bridge irqs");
 }
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index a903012..2dcccda 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -131,9 +131,29 @@ static int __init orion_add_irq_domain(struct device_node *np,
 	return 0;
 }
 
+static int __init orion_add_bridge_irq_domain(
+	struct device_node *np, struct device_node *interrupt_parent)
+{
+	void __iomem *base;
+	int bridge_irq;
+
+	base = of_iomap(np, 0);
+	if (!base)
+		return -ENODEV;
+	bridge_irq = irq_of_parse_and_map(np, 0);
+	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
+	 * bridge IRQ is 0.
+	if (!bridge_irq)
+		return -ENODEV;*/
+
+	return orion_bridge_irq_init(bridge_irq, -1, base, np);
+}
+
 static const struct of_device_id orion_irq_match[] = {
 	{ .compatible = "marvell,orion-intc",
 	  .data = orion_add_irq_domain, },
+	{ .compatible = "marvell,orion-bridge-intc",
+	  .data = orion_add_bridge_irq_domain, },
 	{},
 };
 
-- 
1.7.5.4

[PATCH 3/3] ARM: Orion: Bind the orion timer through DT

[Jason Gunthorpe]

This adds the common DT code and board support for
kirkwood and dove

- Add the marvell,orion-timer DT node to the DTSI file
- Adjust the call paths for dove/kirkwood_timer_init so it only
  happens on non-dt
- Eliminate redundant logging calls of kirkwood_tclk for simplicity.
  These days the tclk frequency is logged here:
sched_clock: 32 bits at 200MHz, resolution 5ns, wraps every 21474ms
- The DT stanza was choosen to simplify future merging with
  time-armada-370-xp.c

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
 arch/arm/boot/dts/dove.dtsi             |    8 ++++++
 arch/arm/boot/dts/kirkwood-dns320.dts   |    3 ++
 arch/arm/boot/dts/kirkwood-lschlv2.dts  |    3 ++
 arch/arm/boot/dts/kirkwood.dtsi         |    9 ++++++
 arch/arm/mach-dove/common.c             |   30 +++++++++++-----------
 arch/arm/mach-kirkwood/board-dt.c       |   10 ++++++-
 arch/arm/mach-kirkwood/common.c         |   42 ++++++++++++++-----------------
 arch/arm/mach-kirkwood/common.h         |    1 -
 arch/arm/plat-orion/include/plat/time.h |    1 +
 arch/arm/plat-orion/time.c              |   32 +++++++++++++++++++++++
 10 files changed, 98 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index b726ba8..da6539b 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -31,6 +31,14 @@
 			reg = <0x20204 0x04>, <0x20214 0x04>;
 		};
 
+		timer at 20300 {
+			compatible = "marvell,orion-timer";
+			reg = <0x20300 0x20>;
+			interrupt-parent = <&bridge_intc>;
+			interrupts = <1>, <2>;
+			clock-frequency = <166666667>;
+                };
+
 		uart0: serial at 12000 {
 			compatible = "ns16550a";
 			reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 5bb0bf3..5bffd7c 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -41,6 +41,9 @@
 	};
 
 	ocp at f1000000 {
+		timer at 20300 {
+			clock-frequency = <166666667>;
+		};
 		serial at 12000 {
 			clock-frequency = <166666667>;
 			status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
index 9510c9e..3b68d92 100644
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -12,6 +12,9 @@
 	};
 
 	ocp at f1000000 {
+		timer at 20300 {
+			clock-frequency = <166666667>;
+		};
 		serial at 12000 {
 			clock-frequency = <166666667>;
 			status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 854e532..278f8ac 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -47,6 +47,15 @@
 			reg = <0x20110 0x08>;
 		};
 
+		timer at 20300 {
+			compatible = "marvell,orion-timer";
+			reg = <0x20300 0x20>;
+			interrupt-parent = <&bridge_intc>;
+			interrupts = <1>, <2>;
+			/* override clock-frequency in board dts */
+			clock-frequency = <200000000>;
+                };
+
 		serial at 12000 {
 			compatible = "ns16550a";
 			reg = <0x12000 0x100>;
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index b570211..43062ea 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -62,7 +62,6 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
-static int dove_tclk;
 
 static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
@@ -75,6 +74,11 @@ static struct clk __init *dove_register_gate(const char *name,
 				 bit_idx, 0, &gating_lock);
 }
 
+static int __init dove_find_tclk(void)
+{
+	return 166666667;
+}
+
 static void __init dove_clk_init(void)
 {
 	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
@@ -82,7 +86,7 @@ static void __init dove_clk_init(void)
 	struct clk *xor0, *xor1, *ge, *gephy;
 
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-				       dove_tclk);
+				       dove_find_tclk());
 
 	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
 	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
@@ -232,18 +236,12 @@ void __init dove_i2c_init(void)
  ****************************************************************************/
 void __init dove_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
-}
-
-static int __init dove_find_tclk(void)
-{
-	return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
-	dove_tclk = dove_find_tclk();
-	orion_time_init(IRQ_DOVE_BRIDGE_TIMER1, dove_tclk);
+	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_init(IRQ_DOVE_BRIDGE_TIMER1, dove_find_tclk());
 }
 
 struct sys_timer dove_timer = {
@@ -340,8 +338,7 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
-		(dove_tclk + 499999) / 1000000);
+	pr_info("Dove 88AP510 SoC\n");
 
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init(0);
@@ -395,8 +392,7 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
 
 static void __init dove_dt_init(void)
 {
-	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
-		(dove_tclk + 499999) / 1000000);
+	pr_info("Dove 88AP510 SoC\n");
 
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init(0);
@@ -425,11 +421,15 @@ static const char * const dove_dt_board_compat[] = {
 	NULL
 };
 
+static struct sys_timer dove_dt_timer = {
+	.init = orion_time_init_dt,
+};
+
 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 	.map_io		= dove_map_io,
 	.init_early	= dove_init_early,
 	.init_irq	= orion_dt_init_irq,
-	.timer		= &dove_timer,
+	.timer		= &dove_dt_timer,
 	.init_machine	= dove_dt_init,
 	.restart	= dove_restart,
 	.dt_compat	= dove_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index ecbb26f..c49146c 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -17,8 +17,10 @@
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 
 static struct of_device_id kirkwood_dt_match_table[] __initdata = {
@@ -41,7 +43,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
 
 static void __init kirkwood_dt_init(void)
 {
-	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+	pr_info("Kirkwood: %s\n", kirkwood_id());
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
@@ -115,12 +117,16 @@ static const char *kirkwood_dt_board_compat[] = {
 	NULL
 };
 
+static struct sys_timer kirkwood_dt_timer = {
+	.init           = orion_time_init_dt,
+};
+
 DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
 	/* Maintainer: Jason Cooper <jason@lakedaemon.net> */
 	.map_io		= kirkwood_map_io,
 	.init_early	= kirkwood_init_early,
 	.init_irq	= orion_dt_init_irq,
-	.timer		= &kirkwood_timer,
+	.timer		= &kirkwood_dt_timer,
 	.init_machine	= kirkwood_dt_init,
 	.restart	= kirkwood_restart,
 	.dt_compat	= kirkwood_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 7398f8b..aeb0458 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -221,13 +221,28 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
 
 static struct clk *ge0, *ge1;
 
+/* FIXME: The tclk frequency is in the DT now, this should fetch it from
+ * there. */
+static int __init kirkwood_find_tclk(void)
+{
+	u32 dev, rev;
+
+	kirkwood_pcie_id(&dev, &rev);
+
+	if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
+		if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
+			return 200000000;
+
+	return 166666667;
+}
+
 void __init kirkwood_clk_init(void)
 {
 	struct clk *runit, *sata0, *sata1, *usb0, *sdio;
 	struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
 
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
-				       CLK_IS_ROOT, kirkwood_tclk);
+				       CLK_IS_ROOT,  kirkwood_find_tclk());
 
 	runit = kirkwood_register_gate("runit",  CGC_BIT_RUNIT);
 	ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
@@ -506,8 +521,6 @@ void __init kirkwood_wdt_init(void)
  ****************************************************************************/
 void __init kirkwood_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
-
 	/*
 	 * Some Kirkwood devices allocate their coherent buffers from atomic
 	 * context. Increase size of atomic coherent pool to make sure such
@@ -516,26 +529,10 @@ void __init kirkwood_init_early(void)
 	init_dma_coherent_pool_size(SZ_1M);
 }
 
-int kirkwood_tclk;
-
-static int __init kirkwood_find_tclk(void)
-{
-	u32 dev, rev;
-
-	kirkwood_pcie_id(&dev, &rev);
-
-	if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
-		if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
-			return 200000000;
-
-	return 166666667;
-}
-
 static void __init kirkwood_timer_init(void)
 {
-	kirkwood_tclk = kirkwood_find_tclk();
-
-	orion_time_init(IRQ_KIRKWOOD_BRIDGE_TIMER1, kirkwood_tclk);
+	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_init(IRQ_KIRKWOOD_BRIDGE_TIMER1, kirkwood_find_tclk());
 }
 
 struct sys_timer kirkwood_timer = {
@@ -647,8 +644,7 @@ void __init kirkwood_l2_init(void)
 
 void __init kirkwood_init(void)
 {
-	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
-		kirkwood_id(), kirkwood_tclk);
+	pr_info("Kirkwood: %s\n", kirkwood_id());
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index bcffd7c..a92fde9 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -120,7 +120,6 @@ void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
 void kirkwood_crypto_init(void);
 
-extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
 #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c5ccc0a..9a4b142 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -14,5 +14,6 @@
 void orion_time_set_base(void __iomem *timer_base);
 
 void orion_time_init(unsigned int irq, unsigned int tclk);
+void __init orion_time_init_dt(void);
 
 #endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index da22aa4..600e8ee 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -16,6 +16,8 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/sched_clock.h>
 #include <linux/sched.h>
 #include <plat/time.h>
@@ -199,3 +201,33 @@ orion_time_init(unsigned int irq, unsigned int tclk)
 	orion_clkevt.cpumask = cpumask_of(0);
 	clockevents_register_device(&orion_clkevt);
 }
+
+#ifdef CONFIG_OF
+void __init
+orion_time_init_dt(void)
+{
+	struct device_node *np;
+	int ret;
+	int irq;
+	u32 clk;
+
+	np = of_find_compatible_node(NULL, NULL, "marvell,orion-timer");
+	if (!np)
+		panic("Bad marvell,orion-timer DT block");
+
+	timer_base = of_iomap(np, 0);
+	if (!timer_base)
+		panic("Bad marvell,orion-timer DT block");
+
+	/* We use timer 0 as clocksource, and timer 1 for clockevents */
+	irq = irq_of_parse_and_map(np, 1);
+	if (!irq)
+		panic("Bad marvell,orion-timer DT block");
+
+	ret = of_property_read_u32(np, "clock-frequency", &clk);
+	if (ret < 0 || clk == 0)
+		panic("Bad marvell,orion-timer DT block");
+
+	orion_time_init(irq, clk);
+}
+#endif
-- 
1.7.5.4

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Andrew Lunn]

On Mon, Dec 10, 2012 at 06:18:02PM -0700, Jason Gunthorpe wrote:
> This adds the common DT code and board support for kirkwood and dove
> 
> - Add the marvell,orion-bridge-intc DT node to the DTSI file
> - Make the call to orion_bridge_irq_init happen only in the non-DT
>   case
> 
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> ---
>  .../devicetree/bindings/arm/mrvl/intc.txt          |   21 ++++++++++++++++++++
>  arch/arm/boot/dts/dove.dtsi                        |   10 +++++++++
>  arch/arm/boot/dts/kirkwood.dtsi                    |   12 +++++++++++
>  arch/arm/mach-dove/common.c                        |    4 ---
>  arch/arm/mach-dove/irq.c                           |    5 ++++
>  arch/arm/mach-kirkwood/common.c                    |    4 ---
>  arch/arm/mach-kirkwood/irq.c                       |    5 ++++
>  arch/arm/plat-orion/irq.c                          |   20 +++++++++++++++++++
>  8 files changed, 73 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
> index 8b53273..cf633f1 100644
> --- a/Documentation/devicetree/bindings/arm/mrvl/intc.txt
> +++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
> @@ -58,3 +58,24 @@ Example:
>                  reg = <0xfed20204 0x04>,
>  		      <0xfed20214 0x04>;
>          };
> +
> +* Marvell Orion Bridge Interrupt controller
> +
> +Required properties
> +- compatible :  Should be "marvell,orion-bridge-intc".
> +- #interrupt-cells: Specifies the number of cells needed to encode an
> +  interrupt source. Supported value is <1>.
> +- interrupt-controller : Declare this node to be an interrupt controller.
> +- interrupts: The interrupt number the bridge is attached to on the main
> +              controller.
> +- reg : Interrupt cause address.
> +
> +Example:
> +
> +	bridge_intc: bridge_intc at 20110 {
> +		compatible = "marvell,orion-bridge-intc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		interrupts = <1>;
> +		reg = <0x20110 0x08>;
> +        };
> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
> index 5a00022..b726ba8 100644
> --- a/arch/arm/boot/dts/dove.dtsi
> +++ b/arch/arm/boot/dts/dove.dtsi
> @@ -67,6 +67,8 @@
>  			status = "disabled";
>  		};
>  
> +		/* The interrupt controller stanzas are in an
> +		 * order that matches irqs.h */
>  		gpio0: gpio at d0400 {
>  			compatible = "marvell,orion-gpio";
>  			#gpio-cells = <2>;
> @@ -93,6 +95,14 @@
>  			ngpio = <8>;
>  		};
>  
> +		bridge_intc: bridge_intc at 20110 {
> +			compatible = "marvell,orion-bridge-intc";
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			interrupts = <0>;
> +			reg = <0x20110 0x08>;
> +		};
> +
>  		spi0: spi at 10600 {
>  			compatible = "marvell,orion-spi";
>  			#address-cells = <1>;
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 4e5b815..854e532 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -19,6 +19,8 @@
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  
> +		/* The interrupt controller stanzas are in an
> +		 * order that matches irqs.h */
>  		gpio0: gpio at 10100 {
>  			compatible = "marvell,orion-gpio";
>  			#gpio-cells = <2>;
> @@ -37,6 +39,14 @@
>  			interrupts = <39>, <40>, <41>;
>  		};
>  
> +		bridge_intc: bridge_intc at 20110 {
> +			compatible = "marvell,orion-bridge-intc";
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			interrupts = <1>;
> +			reg = <0x20110 0x08>;
> +		};
> +
>  		serial at 12000 {
>  			compatible = "ns16550a";
>  			reg = <0x12000 0x100>;
> @@ -73,6 +83,8 @@
>  
>  		wdt at 20300 {
>  			compatible = "marvell,orion-wdt";
> +			interrupt-parent = <&bridge_intc>;
> +			interrupts = <3>;
>  			reg = <0x20300 0x28>;
>  			status = "okay";
>  		};
> diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
> index 6bad21b..b570211 100644
> --- a/arch/arm/mach-dove/common.c
> +++ b/arch/arm/mach-dove/common.c
> @@ -243,10 +243,6 @@ static int __init dove_find_tclk(void)
>  static void __init dove_timer_init(void)
>  {
>  	dove_tclk = dove_find_tclk();
> -	if (orion_bridge_irq_init(IRQ_DOVE_BRIDGE,
> -				  IRQ_DOVE_BRIDGE_START,
> -				  BRIDGE_CAUSE, NULL))
> -		panic("Unable to setup bridge irqs");
>  	orion_time_init(IRQ_DOVE_BRIDGE_TIMER1, dove_tclk);
>  }
>  
> diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
> index bc4344a..bcb193f 100644
> --- a/arch/arm/mach-dove/irq.c
> +++ b/arch/arm/mach-dove/irq.c
> @@ -139,4 +139,9 @@ void __init dove_init_irq(void)
>  		set_irq_flags(i, IRQF_VALID);
>  	}
>  	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
> +
> +	if (orion_bridge_irq_init(IRQ_DOVE_BRIDGE,
> +				  IRQ_DOVE_BRIDGE_START,
> +				  BRIDGE_CAUSE, NULL))
> +		panic("Unable to setup bridge irqs");
>  }
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index ccd3ed5..7398f8b 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -535,10 +535,6 @@ static void __init kirkwood_timer_init(void)
>  {
>  	kirkwood_tclk = kirkwood_find_tclk();
>  
> -	if (orion_bridge_irq_init(IRQ_KIRKWOOD_BRIDGE,
> -				  IRQ_KIRKWOOD_BRIDGE_START,
> -				  BRIDGE_CAUSE, NULL))
> -		panic("Unable to setup bridge irqs");
>  	orion_time_init(IRQ_KIRKWOOD_BRIDGE_TIMER1, kirkwood_tclk);
>  }
>  
> diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
> index 8847035..a1388ef 100644
> --- a/arch/arm/mach-kirkwood/irq.c
> +++ b/arch/arm/mach-kirkwood/irq.c
> @@ -41,4 +41,9 @@ void __init kirkwood_init_irq(void)
>  			IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
>  	orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
>  			IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
> +
> +	if (orion_bridge_irq_init(IRQ_KIRKWOOD_BRIDGE,
> +				  IRQ_KIRKWOOD_BRIDGE_START,
> +				  BRIDGE_CAUSE, NULL))
> +		panic("Unable to setup bridge irqs");
>  }
> diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
> index a903012..2dcccda 100644
> --- a/arch/arm/plat-orion/irq.c
> +++ b/arch/arm/plat-orion/irq.c
> @@ -131,9 +131,29 @@ static int __init orion_add_irq_domain(struct device_node *np,
>  	return 0;
>  }
>  
> +static int __init orion_add_bridge_irq_domain(
> +	struct device_node *np, struct device_node *interrupt_parent)
> +{
> +	void __iomem *base;
> +	int bridge_irq;
> +
> +	base = of_iomap(np, 0);
> +	if (!base)
> +		return -ENODEV;
> +	bridge_irq = irq_of_parse_and_map(np, 0);
> +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> +	 * bridge IRQ is 0.
> +	if (!bridge_irq)
> +		return -ENODEV;*/
> +
> +	return orion_bridge_irq_init(bridge_irq, -1, base, np);

Hi Jason

So does this mean for Dove it will currently always fail?

   Thanks
	Andrew

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Gunthorpe]

> > +	bridge_irq = irq_of_parse_and_map(np, 0);
> > +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> > +	 * bridge IRQ is 0.
> > +	if (!bridge_irq)
> > +		return -ENODEV;*/
> > +
> > +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
> 
> So does this mean for Dove it will currently always fail?

I guess that is hard to read without syntax hi-lighting, the 'if' is
also commented out.

I was hopefull it would work as is, but looking deeper at
irq_of_parse_and_map and its call tree makes me doubtfull now..

Fixing irq_of_parse_and_map is way to big a job for me :(

What to do from here? Add a dummy 0 interrupt to dove? Take dove out
of this patch series?

Jason

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Andrew Lunn]

On Mon, Dec 10, 2012 at 11:58:13PM -0700, Jason Gunthorpe wrote:
> > > +	bridge_irq = irq_of_parse_and_map(np, 0);
> > > +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> > > +	 * bridge IRQ is 0.
> > > +	if (!bridge_irq)
> > > +		return -ENODEV;*/
> > > +
> > > +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
> > 
> > So does this mean for Dove it will currently always fail?
> 
> I guess that is hard to read without syntax hi-lighting, the 'if' is
> also commented out.
> 
> I was hopefull it would work as is, but looking deeper at
> irq_of_parse_and_map and its call tree makes me doubtfull now..
> 
> Fixing irq_of_parse_and_map is way to big a job for me :(

Hi Jason

https://lwn.net/Articles/470820/

I don't think its fixable. 

> What to do from here? Add a dummy 0 interrupt to dove? Take dove out
> of this patch series?

We need to see how other machine remap 0 to some other value and
implement that for Dove.

	  Andrew

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Gunthorpe]

On Tue, Dec 11, 2012 at 08:13:33AM +0100, Andrew Lunn wrote:
> On Mon, Dec 10, 2012 at 11:58:13PM -0700, Jason Gunthorpe wrote:
> > > > +	bridge_irq = irq_of_parse_and_map(np, 0);
> > > > +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> > > > +	 * bridge IRQ is 0.
> > > > +	if (!bridge_irq)
> > > > +		return -ENODEV;*/
> > > > +
> > > > +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
> > > 
> > > So does this mean for Dove it will currently always fail?
> > 
> > I guess that is hard to read without syntax hi-lighting, the 'if' is
> > also commented out.
> > 
> > I was hopefull it would work as is, but looking deeper at
> > irq_of_parse_and_map and its call tree makes me doubtfull now..
> > 
> > Fixing irq_of_parse_and_map is way to big a job for me :(
> 
> Hi Jason
> 
> https://lwn.net/Articles/470820/
> 
> I don't think its fixable. 

Oh right. That.

Looking at this some more, I think it should work, but not for very
good reasons.. irq_of_parse_and_map will return 0 on dove. It returns
0 because it is going through its error paths because it saw a 0 deep
inside, but it still returns 0.

orion_bridge_irq_init will work with 0 as a bridge_irq, we know this
because the timer code was using those code paths for a long time

> We need to see how other machine remap 0 to some other value and
> implement that for Dove.

It looks like it is straightforward to adjust Dove's
get_irqnr_and_base to add 1 to all the interrupt numbers, adjust
irqs.h to add 1, and adjust the irq setup. There would be no
performance penalty to doing this, but testing would be need to be
sure 100% of changes were made. If the above works it would be better
to do that sort of change after, or maybe after the non-DT code is
purged...

Kirkwood is already OK WRT the 0 IRQ, it is handled internally to
get_irqnr_and_base.

So, I will suggest to please test on dove as-is...

Did the other patches look OK?

I threw together an interrupt panic patch for the wdt, and that works
OK as well, so the kirkwood configuration is tested with this
series.

116:    4995890  orion_bridge  orion_tick
117:          0  orion_bridge  orion_wdt

Thanks,
Jason

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Cooper]

Sebastian,

On Tue, Dec 11, 2012 at 11:55:35AM -0700, Jason Gunthorpe wrote:
> On Tue, Dec 11, 2012 at 08:13:33AM +0100, Andrew Lunn wrote:
> > On Mon, Dec 10, 2012 at 11:58:13PM -0700, Jason Gunthorpe wrote:
> > > > > +	bridge_irq = irq_of_parse_and_map(np, 0);
> > > > > +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> > > > > +	 * bridge IRQ is 0.
> > > > > +	if (!bridge_irq)
> > > > > +		return -ENODEV;*/
> > > > > +
> > > > > +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
> > > > 
> > > > So does this mean for Dove it will currently always fail?
> > > 
> > > I guess that is hard to read without syntax hi-lighting, the 'if' is
> > > also commented out.
> > > 
> > > I was hopefull it would work as is, but looking deeper at
> > > irq_of_parse_and_map and its call tree makes me doubtfull now..
> > > 
> > > Fixing irq_of_parse_and_map is way to big a job for me :(
> > 
> > Hi Jason
> > 
> > https://lwn.net/Articles/470820/
> > 
> > I don't think its fixable. 
> 
> Oh right. That.
> 
> Looking at this some more, I think it should work, but not for very
> good reasons.. irq_of_parse_and_map will return 0 on dove. It returns
> 0 because it is going through its error paths because it saw a 0 deep
> inside, but it still returns 0.
> 
> orion_bridge_irq_init will work with 0 as a bridge_irq, we know this
> because the timer code was using those code paths for a long time
> 
> > We need to see how other machine remap 0 to some other value and
> > implement that for Dove.
> 
> It looks like it is straightforward to adjust Dove's
> get_irqnr_and_base to add 1 to all the interrupt numbers, adjust
> irqs.h to add 1, and adjust the irq setup. There would be no
> performance penalty to doing this, but testing would be need to be
> sure 100% of changes were made. If the above works it would be better
> to do that sort of change after, or maybe after the non-DT code is
> purged...
> 
> Kirkwood is already OK WRT the 0 IRQ, it is handled internally to
> get_irqnr_and_base.
> 
> So, I will suggest to please test on dove as-is...

Did you have a chance to test this on dove?

thx,

Jason.

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Andrew Lunn]

On Wed, Jan 09, 2013 at 08:47:34PM -0500, Jason Cooper wrote:
> Sebastian,
> 
> On Tue, Dec 11, 2012 at 11:55:35AM -0700, Jason Gunthorpe wrote:
> > On Tue, Dec 11, 2012 at 08:13:33AM +0100, Andrew Lunn wrote:
> > > On Mon, Dec 10, 2012 at 11:58:13PM -0700, Jason Gunthorpe wrote:
> > > > > > +	bridge_irq = irq_of_parse_and_map(np, 0);
> > > > > > +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
> > > > > > +	 * bridge IRQ is 0.
> > > > > > +	if (!bridge_irq)
> > > > > > +		return -ENODEV;*/
> > > > > > +
> > > > > > +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
> > > > > 
> > > > > So does this mean for Dove it will currently always fail?
> > > > 
> > > > I guess that is hard to read without syntax hi-lighting, the 'if' is
> > > > also commented out.
> > > > 
> > > > I was hopefull it would work as is, but looking deeper at
> > > > irq_of_parse_and_map and its call tree makes me doubtfull now..
> > > > 
> > > > Fixing irq_of_parse_and_map is way to big a job for me :(
> > > 
> > > Hi Jason
> > > 
> > > https://lwn.net/Articles/470820/
> > > 
> > > I don't think its fixable. 
> > 
> > Oh right. That.
> > 
> > Looking at this some more, I think it should work, but not for very
> > good reasons.. irq_of_parse_and_map will return 0 on dove. It returns
> > 0 because it is going through its error paths because it saw a 0 deep
> > inside, but it still returns 0.
> > 
> > orion_bridge_irq_init will work with 0 as a bridge_irq, we know this
> > because the timer code was using those code paths for a long time
> > 
> > > We need to see how other machine remap 0 to some other value and
> > > implement that for Dove.
> > 
> > It looks like it is straightforward to adjust Dove's
> > get_irqnr_and_base to add 1 to all the interrupt numbers, adjust
> > irqs.h to add 1, and adjust the irq setup. There would be no
> > performance penalty to doing this, but testing would be need to be
> > sure 100% of changes were made. If the above works it would be better
> > to do that sort of change after, or maybe after the non-DT code is
> > purged...
> > 
> > Kirkwood is already OK WRT the 0 IRQ, it is handled internally to
> > get_irqnr_and_base.
> > 
> > So, I will suggest to please test on dove as-is...
> 
> Did you have a chance to test this on dove?

Hi Jason

We discussed this a little and I prefer Sebastians implementation.

Sebastian, do you have time to work on your code and get it ready?

Thanks
	Andrew

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Sebastian Hesselbarth]

On 01/10/2013 07:07 AM, Andrew Lunn wrote:
> On Wed, Jan 09, 2013 at 08:47:34PM -0500, Jason Cooper wrote:
>> Sebastian,
>>
>> On Tue, Dec 11, 2012 at 11:55:35AM -0700, Jason Gunthorpe wrote:
>>> On Tue, Dec 11, 2012 at 08:13:33AM +0100, Andrew Lunn wrote:
>>>> On Mon, Dec 10, 2012 at 11:58:13PM -0700, Jason Gunthorpe wrote:
>>>>>>> +	bridge_irq = irq_of_parse_and_map(np, 0);
>>>>>>> +	/* FIXME: irq_of_parse_and_map returns 0 on error, but on Dove the
>>>>>>> +	 * bridge IRQ is 0.
>>>>>>> +	if (!bridge_irq)
>>>>>>> +		return -ENODEV;*/
>>>>>>> +
>>>>>>> +	return orion_bridge_irq_init(bridge_irq, -1, base, np);
>>>>>>
>>>>>> So does this mean for Dove it will currently always fail?
>>>>>
>>>>> I guess that is hard to read without syntax hi-lighting, the 'if' is
>>>>> also commented out.
>>>>>
>>>>> I was hopefull it would work as is, but looking deeper at
>>>>> irq_of_parse_and_map and its call tree makes me doubtfull now..
>>>>>
>>>>> Fixing irq_of_parse_and_map is way to big a job for me :(
>>>>
>>>> Hi Jason
>>>>
>>>> https://lwn.net/Articles/470820/
>>>>
>>>> I don't think its fixable.
>>>
>>> Oh right. That.
>>>
>>> Looking at this some more, I think it should work, but not for very
>>> good reasons.. irq_of_parse_and_map will return 0 on dove. It returns
>>> 0 because it is going through its error paths because it saw a 0 deep
>>> inside, but it still returns 0.
>>>
>>> orion_bridge_irq_init will work with 0 as a bridge_irq, we know this
>>> because the timer code was using those code paths for a long time
>>>
>>>> We need to see how other machine remap 0 to some other value and
>>>> implement that for Dove.
>>>
>>> It looks like it is straightforward to adjust Dove's
>>> get_irqnr_and_base to add 1 to all the interrupt numbers, adjust
>>> irqs.h to add 1, and adjust the irq setup. There would be no
>>> performance penalty to doing this, but testing would be need to be
>>> sure 100% of changes were made. If the above works it would be better
>>> to do that sort of change after, or maybe after the non-DT code is
>>> purged...
>>>
>>> Kirkwood is already OK WRT the 0 IRQ, it is handled internally to
>>> get_irqnr_and_base.
>>>
>>> So, I will suggest to please test on dove as-is...
>>
>> Did you have a chance to test this on dove?
>
> Hi Jason
>
> We discussed this a little and I prefer Sebastians implementation.
>
> Sebastian, do you have time to work on your code and get it ready?

Jason, Andrew,

we chose to jump to irqchip instead of fixing old code. I thought
Jason Gunthorpe volunteered to get it ready? Moving to irqchip also
requires clksrc-orion or reimplementing orion into clksrc-mvebu.

I can do it but it depends on when it should be ready?

Sebastian

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Gunthorpe]

On Thu, Jan 10, 2013 at 10:54:13AM +0100, Sebastian Hesselbarth wrote:

> >>>Kirkwood is already OK WRT the 0 IRQ, it is handled internally to
> >>>get_irqnr_and_base.
> >>>
> >>>So, I will suggest to please test on dove as-is...
> >>
> >>Did you have a chance to test this on dove?
> >
> >Hi Jason
> >
> >We discussed this a little and I prefer Sebastians implementation.
> >
> >Sebastian, do you have time to work on your code and get it ready?
> 
> Jason, Andrew,
> 
> we chose to jump to irqchip instead of fixing old code. I thought
> Jason Gunthorpe volunteered to get it ready? Moving to irqchip also
> requires clksrc-orion or reimplementing orion into clksrc-mvebu.

I looked into it, but at the time there was so much churn going into
the merge window that it was too much to tackle, then there was/is
holidays for me :) Feburary would probably be the soonest I could
actually get my systems running the latest kernels and do any work on
this subject.

The drivers Sebastian posted looked close to what I posted, a few
things like edge interrupts should be copied over from my patches
though..

The irqchip can be done prior to the timer, if the bridge cause
decoding is left disabled in the DT then the existing timer should
still work..

There is a bunch of prep stuff that may still be pending:
 - Fixup remaining drivers (usb? ethernet?) to have DT bindings and
   get the IRQ number through DT
 - Fixup the GPIO driver to dynamically allocate IRQs rather than
   having a hardwired start (did the pinctl change fix this?)
 - Separate the non-DT and DT IRQ related stuff, the IRQ numbering
   changes with the irqchip driver's dynamic allocation. This solves
   the 0 IRQ problem..
 - Remove non-DT code? Andrew was talking about this..

Jason

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Cooper]

Jason,

On Thu, Jan 10, 2013 at 11:48:32AM -0700, Jason Gunthorpe wrote:
> There is a bunch of prep stuff that may still be pending:
>  - Fixup remaining drivers (usb? ethernet?) to have DT bindings and
>    get the IRQ number through DT

any chance I could get you post your changes to the ethernet driver (DT
bindings)?  iirc, you said you had based them off of Ian Molton's work.
Even if you posted them RFC, it'd be a good place to start from,
reignite conversation and so forth.

thx,

Jason.

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Gunthorpe]

On Thu, Jan 10, 2013 at 01:57:37PM -0500, Jason Cooper wrote:
> Jason,
> 
> On Thu, Jan 10, 2013 at 11:48:32AM -0700, Jason Gunthorpe wrote:
> > There is a bunch of prep stuff that may still be pending:
> >  - Fixup remaining drivers (usb? ethernet?) to have DT bindings and
> >    get the IRQ number through DT
> 
> any chance I could get you post your changes to the ethernet driver (DT
> bindings)?  iirc, you said you had based them off of Ian Molton's work.
> Even if you posted them RFC, it'd be a good place to start from,
> reignite conversation and so forth.

I've attached the main mv dt patch as a MIME, sorry for the
awkwardness, I am travelling and won't be available... Please feel free
to re-post/alter as necessary. As I said before, I'm not happy with
it because it doesn't follow the standard convention for MDIO phys.

Jason
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[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Thomas Petazzoni]

Dear Jason Gunthorpe,

On Thu, 10 Jan 2013 21:02:19 -0700, Jason Gunthorpe wrote:

> I've attached the main mv dt patch as a MIME, sorry for the
> awkwardness, I am travelling and won't be available... Please feel
> free to re-post/alter as necessary. As I said before, I'm not happy
> with it because it doesn't follow the standard convention for MDIO
> phys.

The MDIO registers for the mv643xx_eth hardware are the same as the
ones for the mvneta hardware. Therefore, I've splitted this into the
mvmdio driver (available in mainline since 3.8,
drivers/net/ethernet/marvell). This allows to have a nicely separated
driver for the MDIO interface.

My plan was ultimately to modify the mv643xx_eth driver to use the
mvmdio driver, and then do a nice DT binding on top of that.

Does this sounds like a good plan?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT

[Jason Cooper]

On Fri, Jan 11, 2013 at 09:13:49AM +0100, Thomas Petazzoni wrote:
> Dear Jason Gunthorpe,
> 
> On Thu, 10 Jan 2013 21:02:19 -0700, Jason Gunthorpe wrote:
> 
> > I've attached the main mv dt patch as a MIME, sorry for the
> > awkwardness, I am travelling and won't be available... Please feel
> > free to re-post/alter as necessary. As I said before, I'm not happy
> > with it because it doesn't follow the standard convention for MDIO
> > phys.
> 
> The MDIO registers for the mv643xx_eth hardware are the same as the
> ones for the mvneta hardware. Therefore, I've splitted this into the
> mvmdio driver (available in mainline since 3.8,
> drivers/net/ethernet/marvell). This allows to have a nicely separated
> driver for the MDIO interface.
> 
> My plan was ultimately to modify the mv643xx_eth driver to use the
> mvmdio driver, and then do a nice DT binding on top of that.
> 
> Does this sounds like a good plan?

I like it.  If you haven't already, please review the thread at

http://www.spinics.net/lists/arm-kernel/msg186742.html

to see some of the concerns already raised.

thx,

Jason.