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Wed, 26 Jun 2024 06:31:04 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id af79cd13be357-79bce89a369sm502329085a.20.2024.06.26.06.31.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Jun 2024 06:31:04 -0700 (PDT) Message-ID: <50c85e1a-c2ea-4c9f-b91b-97040665c40e@sifive.com> Date: Wed, 26 Jun 2024 08:31:01 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/3] Assorted fixes in RISC-V PMU driver To: Atish Patra , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Andrew Jones , Conor Dooley , Palmer Dabbelt , Alexandre Ghiti , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, garthlei@pku.edu.cn References: <20240626-misc_perf_fixes-v3-0-de3f8ed88dab@rivosinc.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20240626-misc_perf_fixes-v3-0-de3f8ed88dab@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240626_063105_832601_606D0806 X-CRM114-Status: GOOD ( 23.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Atish, On 2024-06-26 2:23 AM, Atish Patra wrote: > This series contains 3 fixes out of which the first one is a new fix > for invalid event data reported in lkml[2]. The last two are v3 of Samuel's > patch[1]. I added the RB/TB/Fixes tag and moved 1 unrelated change > to its own patch. I also changed a error message in kvm vcpu_pmu from > pr_err to pr_debug to avoid redundant failure error messages generated > due to the boot time quering of events implemented in the patch[1] Thanks for picking this up! The change in patch 2 isn't quite unrelated. pmu_sbi_check_std_events() depends on pmu_sbi_stop_all() to ensure all counters are free at the beginning of the function. Compare v1 of the patch where the function contains an additional call to SBI_EXT_PMU_COUNTER_STOP. With the current patch ordering, everything works out, so it all looks good to me. Regards, Samuel > Here is the original cover letter for the patch[1] > > Before this patch: > $ perf list hw > > List of pre-defined events (to be used in -e or -M): > > branch-instructions OR branches [Hardware event] > branch-misses [Hardware event] > bus-cycles [Hardware event] > cache-misses [Hardware event] > cache-references [Hardware event] > cpu-cycles OR cycles [Hardware event] > instructions [Hardware event] > ref-cycles [Hardware event] > stalled-cycles-backend OR idle-cycles-backend [Hardware event] > stalled-cycles-frontend OR idle-cycles-frontend [Hardware event] > > $ perf stat -ddd true > > Performance counter stats for 'true': > > 4.36 msec task-clock # 0.744 CPUs utilized > 1 context-switches # 229.325 /sec > 0 cpu-migrations # 0.000 /sec > 38 page-faults # 8.714 K/sec > 4,375,694 cycles # 1.003 GHz (60.64%) > 728,945 instructions # 0.17 insn per cycle > 79,199 branches # 18.162 M/sec > 17,709 branch-misses # 22.36% of all branches > 181,734 L1-dcache-loads # 41.676 M/sec > 5,547 L1-dcache-load-misses # 3.05% of all L1-dcache accesses > LLC-loads (0.00%) > LLC-load-misses (0.00%) > L1-icache-loads (0.00%) > L1-icache-load-misses (0.00%) > dTLB-loads (0.00%) > dTLB-load-misses (0.00%) > iTLB-loads (0.00%) > iTLB-load-misses (0.00%) > L1-dcache-prefetches (0.00%) > L1-dcache-prefetch-misses (0.00%) > > 0.005860375 seconds time elapsed > > 0.000000000 seconds user > 0.010383000 seconds sys > > After this patch: > $ perf list hw > > List of pre-defined events (to be used in -e or -M): > > branch-instructions OR branches [Hardware event] > branch-misses [Hardware event] > cache-misses [Hardware event] > cache-references [Hardware event] > cpu-cycles OR cycles [Hardware event] > instructions [Hardware event] > > $ perf stat -ddd true > > Performance counter stats for 'true': > > 5.16 msec task-clock # 0.848 CPUs utilized > 1 context-switches # 193.817 /sec > 0 cpu-migrations # 0.000 /sec > 37 page-faults # 7.171 K/sec > 5,183,625 cycles # 1.005 GHz > 961,696 instructions # 0.19 insn per cycle > 85,853 branches # 16.640 M/sec > 20,462 branch-misses # 23.83% of all branches > 243,545 L1-dcache-loads # 47.203 M/sec > 5,974 L1-dcache-load-misses # 2.45% of all L1-dcache accesses > LLC-loads > LLC-load-misses > L1-icache-loads > L1-icache-load-misses > dTLB-loads > 19,619 dTLB-load-misses > iTLB-loads > 6,831 iTLB-load-misses > L1-dcache-prefetches > L1-dcache-prefetch-misses > > 0.006085625 seconds time elapsed > > 0.000000000 seconds user > 0.013022000 seconds sys > > Changes in v3: > - Added one more fix > - Separated an unrelated change to its own patch. > - Rebase and Added RB/TB/Fixes tag. > - Changed a error message in kvm code to avoid unnecessary failures > at guest booting. > Changes in v2: > - Move the event checking to a workqueue to make it asynchronous > - Add more details to the commit message based on the v1 discussion > > [1] https://lore.kernel.org/linux-riscv/20240418014652.1143466-1-samuel.holland@sifive.com/ > [2] https://lore.kernel.org/all/CC51D53B-846C-4D81-86FC-FBF969D0A0D6@pku.edu.cn/ > > Signed-off-by: Atish Patra > --- > Atish Patra (1): > drivers/perf: riscv: Do not update the event data if uptodate > > Samuel Holland (2): > drivers/perf: riscv: Reset the counter to hpmevent mapping while starting cpus > perf: RISC-V: Check standard event availability > > arch/riscv/kvm/vcpu_pmu.c | 2 +- > drivers/perf/riscv_pmu.c | 2 +- > drivers/perf/riscv_pmu_sbi.c | 44 +++++++++++++++++++++++++++++++++++++++++--- > 3 files changed, 43 insertions(+), 5 deletions(-) > --- > base-commit: 55027e689933ba2e64f3d245fb1ff185b3e7fc81 > change-id: 20240625-misc_perf_fixes-5c57f555d828 > -- > Regards, > Atish patra >