From: ldewangan@nvidia.com (Laxman Dewangan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB
Date: Fri, 8 Mar 2013 23:30:42 +0530 [thread overview]
Message-ID: <513A274A.4030709@nvidia.com> (raw)
In-Reply-To: <513A2433.2080002@wwwdotorg.org>
On Friday 08 March 2013 11:17 PM, Stephen Warren wrote:
> On 03/08/2013 07:00 AM, Laxman Dewangan wrote:
>> UARTB clock bit in CAR register is 7. Correcting this
>> in DTS file.
> The register bit is 7, but the clock ID in the Tegra CAR DT binding is
> 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and
> 2 separate IP block reset bits, or the other way around, so we highlight
> the issue by assigning different clock IDs. See the comment before the
> list of clock IDs in the binding document.
Aaha, I missed the Documentation part. I was looking for DT entry only
found this.
prev parent reply other threads:[~2013-03-08 18:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-08 14:00 [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB Laxman Dewangan
2013-03-08 17:47 ` Stephen Warren
2013-03-08 18:00 ` Laxman Dewangan [this message]
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