[PATCH v2 00/11] ARM: dts: OMAP5: ocp address space and few updates for 3.10

[PATCH v2 00/11] ARM: dts: OMAP5: ocp address space and few updates for 3.10

[Santosh Shilimkar]

Benoit,

Here is the branch rebased and updated against your 'for_3.10/dt' branch.
Few minor updates about ocp/l3 node after our discussion at connect from
last version. The series also contains couple of hwmod patches to deal
with ocp address space from dt blob and avoiding iormap for some of
the hwmods.

It has been tested on OMAP4 and OMAP5 devices. Though for OMAP5 testing, data
files and other patches are needed which are also targeted for 3.10 merge
window.

The following changes since commit 44fab7a60d4c3929a04b7dc882ac1143b3f21b0f:

  ARM: dts: omap3-devkit8000: Add NAND DT node (2013-03-18 15:01:23 +0100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux.git for_3.10/omap_dt_update

for you to fetch changes up to c0c153b52b9ed4965b7496e462b2effa3e4fa9ce:

  ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc (2013-03-19 17:11:39 +0530)

----------------------------------------------------------------

Lokesh Vutla (1):
  ARM: dts: OMAP5: Add watchdog timer node

Rajendra Nayak (1):
  ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

Santosh Shilimkar (9):
  ARM: dts: omap5-evm: Update available memory to 2032 MB
  ARM: dts: OMAP5: Align the local timer dt node as per the current
    binding code
  ARM: dts: OMAP5: Move the gic node out of ocp space
  ARM: dts: OMAP5: Update the timer and gic nodes for HYP kernel
    support
  ARM: dts: OMAP5: Update keypad reg property
  Documentation: dt: OMAP: l3-noc: Add *reg* in required properties
  ARM: dts: OMAP4/5: Update l3-noc dt nodes
  ARM: OMAP2+: hwmod: extract module address space from DT blob
  ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc

 .../devicetree/bindings/arm/omap/l3-noc.txt        |    1 +
 arch/arm/boot/dts/omap4.dtsi                       |    5 ++
 arch/arm/boot/dts/omap5-evm.dts                    |    2 +-
 arch/arm/boot/dts/omap5.dtsi                       |   56 +++++++++++++-------
 arch/arm/mach-omap2/omap_hwmod.c                   |   48 +++++++++++++++--
 5 files changed, 87 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[PATCH v2 01/11] ARM: dts: omap5-evm: Update available memory to 2032 MB

[Santosh Shilimkar]

On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 64edd51..982acd1 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -16,7 +16,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x80000000>; /* 2 GB */
+		reg = <0x80000000 0x7F000000>; /* 2032 MB */
 	};
 
 	vmmcsd_fixed: fixedregulator-mmcsd {
-- 
1.7.9.5

[PATCH v2 02/11] ARM: dts: OMAP5: Align the local timer dt node as per the current binding code

[Santosh Shilimkar]

It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.

Update the OMAP5 dt file accordingly.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b760c11..aefecf7 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,24 +33,19 @@
 	cpus {
 		cpu at 0 {
 			compatible = "arm,cortex-a15";
-			timer {
-				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
-				clock-frequency = <6144000>;
-			};
 		};
 		cpu at 1 {
 			compatible = "arm,cortex-a15";
-			timer {
-				compatible = "arm,armv7-timer";
-				/* 14th PPI IRQ, active low level-sensitive */
-				interrupts = <1 14 0x308>;
-				clock-frequency = <6144000>;
-			};
 		};
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		/* 14th PPI IRQ, active low level-sensitive */
+		interrupts = <1 14 0x308>;
+		clock-frequency = <6144000>;
+	};
+
 	/*
 	 * The soc node represents the soc top level view. It is uses for IPs
 	 * that are not memory mapped in the MPU view or for the MPU itself.
-- 
1.7.9.5

[PATCH v2 03/11] ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer

[Santosh Shilimkar]

From: Rajendra Nayak <rnayak@ti.com>

Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..

[    0.000000] arch_timer: No interrupt available, giving up

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index aefecf7..71be239 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -41,8 +41,9 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		/* 14th PPI IRQ, active low level-sensitive */
-		interrupts = <1 14 0x308>;
+		/* PPI secure/nonsecure IRQ, active low level-sensitive */
+		interrupts = <1 13 0x308>,
+			     <1 14 0x308>;
 		clock-frequency = <6144000>;
 	};
 
-- 
1.7.9.5

[PATCH v2 04/11] ARM: dts: OMAP5: Move the gic node out of ocp space

[Santosh Shilimkar]

GIC is not part of OCP space so move the gic dt node out of ocp
dt address space.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 71be239..4701244 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -18,6 +18,9 @@
 /include/ "skeleton.dtsi"
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	compatible = "ti,omap5";
 	interrupt-parent = <&gic>;
 
@@ -47,6 +50,14 @@
 		clock-frequency = <6144000>;
 	};
 
+	gic: interrupt-controller at 48211000 {
+		compatible = "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x48211000 0x1000>,
+		      <0x48212000 0x1000>;
+	};
+
 	/*
 	 * The soc node represents the soc top level view. It is uses for IPs
 	 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -96,14 +107,6 @@
 			pinctrl-single,function-mask = <0x7fff>;
 		};
 
-		gic: interrupt-controller at 48211000 {
-			compatible = "arm,cortex-a15-gic";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x48211000 0x1000>,
-			      <0x48212000 0x1000>;
-		};
-
 		sdma: dma-controller at 4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-- 
1.7.9.5

[PATCH v2 05/11] ARM: dts: OMAP5: Update the timer and gic nodes for HYP kernel support

[Santosh Shilimkar]

To be able to run kernel in HYP mode, virtual timer and gic node information
needs to be popullated.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 4701244..ff09720 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -46,7 +46,9 @@
 		compatible = "arm,armv7-timer";
 		/* PPI secure/nonsecure IRQ, active low level-sensitive */
 		interrupts = <1 13 0x308>,
-			     <1 14 0x308>;
+			     <1 14 0x308>,
+			     <1 11 0x308>,
+			     <1 10 0x308>;
 		clock-frequency = <6144000>;
 	};
 
@@ -55,7 +57,9 @@
 		interrupt-controller;
 		#interrupt-cells = <3>;
 		reg = <0x48211000 0x1000>,
-		      <0x48212000 0x1000>;
+		      <0x48212000 0x1000>,
+		      <0x48214000 0x2000>,
+		      <0x48216000 0x2000>;
 	};
 
 	/*
-- 
1.7.9.5

[PATCH v2 06/11] ARM: dts: OMAP5: Update keypad reg property

[Santosh Shilimkar]

Add missing OMAP keypad reg property information.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ff09720..e539258 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -427,6 +427,7 @@
 
 		keypad: keypad at 4ae1c000 {
 			compatible = "ti,omap4-keypad";
+			reg = <0x4ae1c000 0x400>;
 			ti,hwmods = "kbd";
 		};
 
-- 
1.7.9.5

[PATCH v2 07/11] Documentation: dt: OMAP: l3-noc: Add *reg* in required properties

[Santosh Shilimkar]

OMAP L3 driver needs reg address space for its operation and
hence its a required property.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 .../devicetree/bindings/arm/omap/l3-noc.txt        |    1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
index 6888a5e..c0105de 100644
--- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
@@ -6,6 +6,7 @@ provided by Arteris.
 Required properties:
 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
                Should be "ti,omap4-l3-noc" for OMAP4 family
+- reg:	Contains L3 register address range for each noc domain.
 - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
 
 Examples:
-- 
1.7.9.5

[PATCH v2 08/11] ARM: dts: OMAP4/5: Update l3-noc dt nodes

[Santosh Shilimkar]

Add l3-noc node for OMAP4 and OMAP5 devices.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    5 +++++
 arch/arm/boot/dts/omap5.dtsi |    5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index ddfc54a..3329140 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -94,6 +94,11 @@
 		#size-cells = <1>;
 		ranges;
 		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+		reg = <0x44000000 0x1000>,
+		      <0x44800000 0x2000>,
+		      <0x45000000 0x1000>;
+		interrupts = <0 41 0x4>,
+			     <0 42 0x4>;
 
 		counter32k: counter at 4a304000 {
 			compatible = "ti,omap-counter32k";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e539258..59e05c5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -87,6 +87,11 @@
 		#size-cells = <1>;
 		ranges;
 		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+		reg = <0x44000000 0x2000>,
+		      <0x44800000 0x3000>,
+		      <0x45000000 0x4000>;
+		interrupts = <0 41 0x4>,
+			     <0 42 0x4>;
 
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
-- 
1.7.9.5

[PATCH v2 09/11] ARM: dts: OMAP5: Add watchdog timer node

[Santosh Shilimkar]

From: Lokesh Vutla <lokeshvutla@ti.com>

Add watchdog timer dt node for OMAP5 devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 59e05c5..f4c71d9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -590,6 +590,13 @@
 			ti,timer-pwm;
 		};
 
+		wdt2: wdt at 4ae14000 {
+			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
+			reg = <0x4ae14000 0x80>;
+			interrupts = <0 80 0x4>;
+			ti,hwmods = "wd_timer2";
+		};
+
 		emif1: emif at 0x4c000000 {
 			compatible	= "ti,emif-4d5";
 			ti,hwmods	= "emif1";
-- 
1.7.9.5

[PATCH v2 10/11] ARM: OMAP2+: hwmod: extract module address space from DT blob

[Santosh Shilimkar]

Patch adds the code for extracting the module ocp address space from device
tree blob in case the hwmod address space look up fails.

The idea is to remove the address space data from hwmod and extract it from
DT blob.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   45 +++++++++++++++++++++++++++++++++++---
 1 file changed, 42 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c..4501038 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -138,6 +138,8 @@
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/bootmem.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/system_misc.h>
 
@@ -2350,6 +2352,34 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 
 /**
+ * of_dev_hwmod_lookup - look up needed hwmod from dt blob
+ * @np: struct device_node *
+ * @oh: struct omap_hwmod *
+ *
+ * Parse the dt blob and find out needed hwmod. Recursive function is
+ * implemented to take care hierarchical dt blob parsing.
+ * Return: The device node on success or NULL on failure.
+ */
+static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
+						struct omap_hwmod *oh)
+{
+	struct device_node *np0 = NULL, *np1 = NULL;
+	const char *p;
+
+	for_each_child_of_node(np, np0) {
+		if (of_find_property(np0, "ti,hwmods", NULL)) {
+			p = of_get_property(np0, "ti,hwmods", NULL);
+			if (!strcmp(p, oh->name))
+				return np0;
+			np1 = of_dev_hwmod_lookup(np0, oh);
+			if (np1)
+				return np1;
+		}
+	}
+	return NULL;
+}
+
+/**
  * _init_mpu_rt_base - populate the virtual address for a hwmod
  * @oh: struct omap_hwmod * to locate the virtual address
  *
@@ -2361,7 +2391,8 @@ static int _shutdown(struct omap_hwmod *oh)
 static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 {
 	struct omap_hwmod_addr_space *mem;
-	void __iomem *va_start;
+	void __iomem *va_start = NULL;
+	struct device_node *np;
 
 	if (!oh)
 		return;
@@ -2375,10 +2406,18 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 	if (!mem) {
 		pr_debug("omap_hwmod: %s: no MPU register target found\n",
 			 oh->name);
-		return;
+
+		/* Extract the IO space from device tree blob */
+		if (!of_have_populated_dt())
+			return;
+
+		np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
+		if (np)
+			va_start = of_iomap(np, 0);
+	} else {
+		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
 	}
 
-	va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
 	if (!va_start) {
 		pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
 		return;
-- 
1.7.9.5

[PATCH v2 11/11] ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc

[Santosh Shilimkar]

OMAP hwmod layer does the reset of the IPs in early code so that
we have SOC in sane state. To do the soft-reset, it needs to ioremap()
the ip address space to be able to write to sysconfig registers.

But there are few hwmod which doesn't have sysconfig registers and hence
no need to ioremap() them in early init code.

So this patch makes prevet calling the _init_mpu_rt_base() conditional
based on sysc availability.

Cc: Benoit Cousson <b-cousson@ti.com>

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 4501038..1a1f0a4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2449,7 +2449,8 @@ static int __init _init(struct omap_hwmod *oh, void *data)
 	if (oh->_state != _HWMOD_STATE_REGISTERED)
 		return 0;
 
-	_init_mpu_rt_base(oh, NULL);
+	if (oh->class->sysc)
+		_init_mpu_rt_base(oh, NULL);
 
 	r = _init_clocks(oh, NULL);
 	if (IS_ERR_VALUE(r)) {
-- 
1.7.9.5

[PATCH v2 11/11] ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc

[Jon Hunter]

On 03/19/2013 08:30 AM, Santosh Shilimkar wrote:
> OMAP hwmod layer does the reset of the IPs in early code so that
> we have SOC in sane state. To do the soft-reset, it needs to ioremap()
> the ip address space to be able to write to sysconfig registers.
> 
> But there are few hwmod which doesn't have sysconfig registers and hence
> no need to ioremap() them in early init code.
> 
> So this patch makes prevet calling the _init_mpu_rt_base() conditional
> based on sysc availability.
> 
> Cc: Benoit Cousson <b-cousson@ti.com>
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 4501038..1a1f0a4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -2449,7 +2449,8 @@ static int __init _init(struct omap_hwmod *oh, void *data)
>  	if (oh->_state != _HWMOD_STATE_REGISTERED)
>  		return 0;
>  
> -	_init_mpu_rt_base(oh, NULL);
> +	if (oh->class->sysc)
> +		_init_mpu_rt_base(oh, NULL);
>  
>  	r = _init_clocks(oh, NULL);
>  	if (IS_ERR_VALUE(r)) {

I have not looked into why, but this commit is triggering the following
panic on am335x-evm. I don't see this on the omap platforms only am335x. 

Adding Vaibhav ...

Jon

[    2.059957] Unhandled fault: external abort on non-linefetch (0x1028) at 0xf9e35034
[    2.068067] Internal error: : 1028 [#1] SMP ARM
[    2.072856] Modules linked in:
[    2.076102] CPU: 0    Not tainted  (3.9.0-rc3-00051-g4a98c2d #774)
[    2.082651] PC is at omap_wdt_disable.isra.5+0xc/0x60
[    2.087988] LR is at omap_wdt_probe+0x170/0x200
[    2.092774] pc : [<c04447b8>]    lr : [<c0444b00>]    psr: 60000113
[    2.092774] sp : de05de68  ip : 00000001  fp : 00000000
[    2.104888] r10: dd2243c0  r9 : 00000000  r8 : c1312c38
[    2.110404] r7 : dd2403d0  r6 : de0ae3c0  r5 : de0e7c10  r4 : dd181210
[    2.117293] r3 : f9e35034  r2 : 00000000  r1 : 04a00000  r0 : f9e35000
[    2.124185] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    2.131901] Control: 10c5387d  Table: 80004019  DAC: 00000017
[    2.137967] Process swapper/0 (pid: 1, stack limit = 0xde05c240)
[    2.144308] Stack: (0xde05de68 to 0xde05e000)
[    2.148915] de60:   
[    2.151231] de80: c0db1f98 c07afe40 c07893f8 c0364284 c036426c c0362ef4 de0e7c10 c0db1f98
[    2.159870] dea0: de0e7c44 00000000 00000000 c036309c c0db1f98 c0363008 00000000 c03615e4
[    2.168509] dec0: de01e2a8 de0cdb10 c0db1f98 c0da0b38 dd240440 c036256c c069606c 00000000
[    2.177148] dee0: de051d40 c0db1f98 de05c000 c0dbdd00 00000000 00000000 c07afe40 c07893f8
[    2.185786] df00: 00000000 c0363568 c03642ac c0793ec4 de05c000 c0dbdd00 00000000 000000a3
[    2.194424] df20: c07893f8 c00086a4 c07306d8 c0731108 c1722d6b c07893f8 00000001 c1722d77
[    2.203061] df40: c06f1144 00000000 00000006 00000006 00000001 c0793ec4 00000006 c0793ea4
[    2.211699] df60: c0dbdd00 000000a3 c07afe40 c075f1c4 00000000 c075f8f8 00000006 00000006
[    2.220338] df80: c075f1c4 00000000 00000000 c0547dec 00000000 00000000 00000000 00000000
[    2.228975] dfa0: 00000000 c0547df4 00000000 c0013e50 00000000 00000000 00000000 00000000
[    2.237615] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[    2.246252] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 fbffffeb ff3fbefe
[    2.254904] [<c04447b8>] (omap_wdt_disable.isra.5+0xc/0x60) from [<c0444b00>] (omap_wdt_probe+0x170/0x200)
[    2.265118] [<c0444b00>] (omap_wdt_probe+0x170/0x200) from [<c0364284>] (platform_drv_probe+0x18/0x1c)
[    2.274955] [<c0364284>] (platform_drv_probe+0x18/0x1c) from [<c0362ef4>] (driver_probe_device+0x108/0x21c)
[    2.285248] [<c0362ef4>] (driver_probe_device+0x108/0x21c) from [<c036309c>] (__driver_attach+0x94/0x98)
[    2.295263] [<c036309c>] (__driver_attach+0x94/0x98) from [<c03615e4>] (bus_for_each_dev+0x54/0x88)
[    2.304822] [<c03615e4>] (bus_for_each_dev+0x54/0x88) from [<c036256c>] (bus_add_driver+0xdc/0x29c)
[    2.314381] [<c036256c>] (bus_add_driver+0xdc/0x29c) from [<c0363568>] (driver_register+0x78/0x190)
[    2.323941] [<c0363568>] (driver_register+0x78/0x190) from [<c00086a4>] (do_one_initcall+0x34/0x178)
[    2.333605] [<c00086a4>] (do_one_initcall+0x34/0x178) from [<c075f8f8>] (kernel_init_freeable+0xfc/0x1c4)
[    2.343728] [<c075f8f8>] (kernel_init_freeable+0xfc/0x1c4) from [<c0547df4>] (kernel_init+0x8/0xe4)
[    2.353300] [<c0547df4>] (kernel_init+0x8/0xe4) from [<c0013e50>] (ret_from_fork+0x14/0x24)
[    2.362124] Code: e8bd80f8 e59f3050 e5803048 e2803034 (e5902034) 
[    2.368631] ---[ end trace 63f90a88f45b89ae ]---
[    2.373734] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
 

[PATCH v2 11/11] ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hunter, Jon
> Sent: Thursday, April 11, 2013 7:17 AM
> To: Shilimkar, Santosh
> Cc: Cousson, Benoit; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; tony at atomide.com; Hiremath, Vaibhav
> Subject: Re: [PATCH v2 11/11] ARM: OMAP2+: omap_hwmod: Don't call
> _init_mpu_rt_base if no sysc
> 
> 
> On 03/19/2013 08:30 AM, Santosh Shilimkar wrote:
> > OMAP hwmod layer does the reset of the IPs in early code so that
> > we have SOC in sane state. To do the soft-reset, it needs to
> ioremap()
> > the ip address space to be able to write to sysconfig registers.
> >
> > But there are few hwmod which doesn't have sysconfig registers and
> hence
> > no need to ioremap() them in early init code.
> >
> > So this patch makes prevet calling the _init_mpu_rt_base()
> conditional
> > based on sysc availability.
> >
> > Cc: Benoit Cousson <b-cousson@ti.com>
> >
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > ---
> >  arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-
> omap2/omap_hwmod.c
> > index 4501038..1a1f0a4 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod.c
> > @@ -2449,7 +2449,8 @@ static int __init _init(struct omap_hwmod *oh,
> void *data)
> >  	if (oh->_state != _HWMOD_STATE_REGISTERED)
> >  		return 0;
> >
> > -	_init_mpu_rt_base(oh, NULL);
> > +	if (oh->class->sysc)
> > +		_init_mpu_rt_base(oh, NULL);
> >
> >  	r = _init_clocks(oh, NULL);
> >  	if (IS_ERR_VALUE(r)) {
> 
> I have not looked into why, but this commit is triggering the following
> panic on am335x-evm. I don't see this on the omap platforms only
> am335x.
> 
> Adding Vaibhav ...
> 
I think I have already fixed this, can you try applying below patches

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg87524.html


Thanks,
Vaibhav



Thanks,
Vaibhav

[PATCH v2 00/11] ARM: dts: OMAP5: ocp address space and few updates for 3.10

[Benoit Cousson]

Hi Santosh,

The series looks good to me. I've just applied it and update my branch.

I just slightly modified some changelog to fix typos.

Thanks,
Benoit


On 03/19/2013 02:30 PM, Santosh Shilimkar wrote:
> Benoit,
> 
> Here is the branch rebased and updated against your 'for_3.10/dt' branch.
> Few minor updates about ocp/l3 node after our discussion at connect from
> last version. The series also contains couple of hwmod patches to deal
> with ocp address space from dt blob and avoiding iormap for some of
> the hwmods.
> 
> It has been tested on OMAP4 and OMAP5 devices. Though for OMAP5 testing, data
> files and other patches are needed which are also targeted for 3.10 merge
> window.
> 
> The following changes since commit 44fab7a60d4c3929a04b7dc882ac1143b3f21b0f:
> 
>   ARM: dts: omap3-devkit8000: Add NAND DT node (2013-03-18 15:01:23 +0100)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux.git for_3.10/omap_dt_update
> 
> for you to fetch changes up to c0c153b52b9ed4965b7496e462b2effa3e4fa9ce:
> 
>   ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc (2013-03-19 17:11:39 +0530)
> 
> ----------------------------------------------------------------
> 
> Lokesh Vutla (1):
>   ARM: dts: OMAP5: Add watchdog timer node
> 
> Rajendra Nayak (1):
>   ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
> 
> Santosh Shilimkar (9):
>   ARM: dts: omap5-evm: Update available memory to 2032 MB
>   ARM: dts: OMAP5: Align the local timer dt node as per the current
>     binding code
>   ARM: dts: OMAP5: Move the gic node out of ocp space
>   ARM: dts: OMAP5: Update the timer and gic nodes for HYP kernel
>     support
>   ARM: dts: OMAP5: Update keypad reg property
>   Documentation: dt: OMAP: l3-noc: Add *reg* in required properties
>   ARM: dts: OMAP4/5: Update l3-noc dt nodes
>   ARM: OMAP2+: hwmod: extract module address space from DT blob
>   ARM: OMAP2+: omap_hwmod: Don't call _init_mpu_rt_base if no sysc
> 
>  .../devicetree/bindings/arm/omap/l3-noc.txt        |    1 +
>  arch/arm/boot/dts/omap4.dtsi                       |    5 ++
>  arch/arm/boot/dts/omap5-evm.dts                    |    2 +-
>  arch/arm/boot/dts/omap5.dtsi                       |   56 +++++++++++++-------
>  arch/arm/mach-omap2/omap_hwmod.c                   |   48 +++++++++++++++--
>  5 files changed, 87 insertions(+), 25 deletions(-)
> 

[PATCH v2 00/11] ARM: dts: OMAP5: ocp address space and few updates for 3.10

[Santosh Shilimkar]

On Tuesday 26 March 2013 08:01 PM, Benoit Cousson wrote:
> Hi Santosh,
> 
> The series looks good to me. I've just applied it and update my branch.
> 
> I just slightly modified some changelog to fix typos.
> 
Thanks Benoit !!
Will pull your updated branch.

Regards,
Santosh