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From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU
Date: Fri, 20 Jun 2014 18:18:23 +0200	[thread overview]
Message-ID: <5173253.SQfLkZY3Wx@wuerfel> (raw)
In-Reply-To: <53A1571B.7080806@ti.com>

On Wednesday 18 June 2014 14:38:43 Kishon Vijay Abraham I wrote:
> On Thursday 29 May 2014 12:08 PM, Kishon Vijay Abraham I wrote:
> > 
> > Here the CPU address for configuration space is 0x20013000 and the controller
> > address for configuration space is 0x13000. The controller address should be
> > used while programming the ATU (in order for translation to happen properly in
> > DRA7xx).
> 
> I've fixed this up with what you suggested in the v1 of the series. Do you
> think this is fine?

Hi Kishon,

Yes, I think this will work and do the right thing in all cases. I'm not
completely sure if the change should be generalized into the range
parser or better kept in the pcie-designware driver as you do it here:

> > @@ -406,6 +413,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >               pp->config.cfg1_size = resource_size(cfg_res)/2;
> >               pp->cfg0_base = cfg_res->start;
> >               pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
> > +
> > +             /* Find the untranslated configuration space address */
> > +             index = of_property_match_string(np, "reg-names", "config");
> > +             addrp = of_get_address(np, index, false, false);
> > +             pp->cfg0_mod_addr = of_read_number(addrp, ns);
> > +             pp->cfg1_mod_addr = pp->cfg0_mod_addr + pp->config.cfg0_size;

I think I've recently seen some objections to hand-parsing standard
properties in driver code.

> >       } else {
> >               dev_err(pp->dev, "missing *config* reg space\n");
> >       }
> > @@ -431,12 +444,20 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >                       pp->config.io_size = resource_size(&pp->io);
> >                       pp->config.io_bus_addr = range.pci_addr;
> >                       pp->io_base = range.cpu_addr;
> > +
> > +                     /* Find the untranslated IO space address */
> > +                     pp->io_mod_addr = of_read_number(parser.range -
> > +                                                      parser.np + na, ns);
> >               }

So the of_read_number() call could be moved into of_pci_range_to_resource(),
with another field added to struct of_pci_range to carry the address on
the parent bus. Any other thoughts on this? Maybe Rob Herring or Andrew
Murray have a strong opinion on this.


	Arnd

  reply	other threads:[~2014-06-20 16:18 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-29  6:38 [PATCH v2 00/18] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 01/18] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 02/18] phy: pipe3: insert delay to enumerate in GEN2 mode Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg' Kishon Vijay Abraham I
2014-05-29  7:11   ` Mohit KUMAR DCG
2014-05-29 13:16     ` Kishon Vijay Abraham I
2014-05-29 15:03   ` Kumar Gala
2014-05-29 15:18     ` Liviu Dudau
2014-05-29 16:03       ` Kumar Gala
2014-05-29 16:30         ` Jason Gunthorpe
2014-05-29 16:51           ` Kumar Gala
2014-05-29 16:32   ` Murali Karicheri
2014-05-30  5:30     ` Kishon Vijay Abraham I
2014-05-30 14:15     ` Karicheri, Muralidharan
2014-06-18  9:14       ` Kishon Vijay Abraham I
2014-06-18  9:27         ` Jingoo Han
2014-05-29  6:38 ` [PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU Kishon Vijay Abraham I
2014-06-18  9:08   ` Kishon Vijay Abraham I
2014-06-20 16:18     ` Arnd Bergmann [this message]
2014-06-20 17:45   ` Rob Herring
2014-06-20 18:54     ` Arnd Bergmann
2014-05-29  6:38 ` [PATCH v2 05/18] PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-06-19 11:10   ` Tero Kristo
2014-06-19 12:45     ` Kishon Vijay Abraham I
2014-06-19 13:27       ` Tero Kristo
2014-05-29  6:38 ` [PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-06-19 11:12   ` Tero Kristo
2014-06-19 13:00     ` Kishon Vijay Abraham I
2014-06-19 13:24       ` Tero Kristo
2014-05-29  6:38 ` [PATCH v2 08/18] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 09/18] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-06-19 11:16   ` Tero Kristo
2014-06-19 13:23     ` Kishon Vijay Abraham I
2014-06-19 13:26       ` Tero Kristo
2014-05-29  6:38 ` [PATCH v2 11/18] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 12/18] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe " Kishon Vijay Abraham I
2014-06-19 11:20   ` Tero Kristo
2014-06-19 13:25     ` Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 14/18] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 15/18] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-29  6:38 ` [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-29  6:48   ` Jingoo Han
2014-05-29 13:17     ` Kishon Vijay Abraham I
2014-05-29 17:52   ` Rob Herring
2014-05-29 17:54     ` Will Deacon
2014-05-29  6:38 ` [TEMP PATCH v2 17/18] PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-29  6:38 ` [TEMP PATCH v2 18/18] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I

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