* [PATCH 0/2] ARM: sunxi: Clock fixes for the Allwinner A13
@ 2013-04-30 9:56 Maxime Ripard
2013-04-30 9:56 ` [PATCH 1/2] clk: sun5i: Add compatibles for " Maxime Ripard
2013-04-30 9:56 ` [PATCH 2/2] ARM: sun5i: Update the clock compatible strings Maxime Ripard
0 siblings, 2 replies; 7+ messages in thread
From: Maxime Ripard @ 2013-04-30 9:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This is a patchset making the current clock code fit for the A13.
The A13 has less clock gates available, while the logic remains, so
we need to make very few changes to handle the A13.
Thanks,
Maxime
Maxime Ripard (2):
clk: sun5i: Add compatibles for Allwinner A13
ARM: sun5i: Update the clock compatible strings
Documentation/devicetree/bindings/clock/sunxi.txt | 117 +++------------------
.../bindings/clock/sunxi/sun4i-a10-gates.txt | 93 ++++++++++++++++
.../bindings/clock/sunxi/sun5i-a13-gates.txt | 58 ++++++++++
arch/arm/boot/dts/sun5i-a13.dtsi | 35 +++---
drivers/clk/sunxi/clk-sunxi.c | 31 ++++--
5 files changed, 199 insertions(+), 135 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
--
1.8.1.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] clk: sun5i: Add compatibles for Allwinner A13
2013-04-30 9:56 [PATCH 0/2] ARM: sunxi: Clock fixes for the Allwinner A13 Maxime Ripard
@ 2013-04-30 9:56 ` Maxime Ripard
2013-04-30 11:20 ` Emilio López
2013-04-30 9:56 ` [PATCH 2/2] ARM: sun5i: Update the clock compatible strings Maxime Ripard
1 sibling, 1 reply; 7+ messages in thread
From: Maxime Ripard @ 2013-04-30 9:56 UTC (permalink / raw)
To: linux-arm-kernel
The A13 has a lot less clocks than the one found in the Allwinner A10.
Add these stripped down clocks to the clock driver and in the
documentation.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 117 +++------------------
.../bindings/clock/sunxi/sun4i-a10-gates.txt | 93 ++++++++++++++++
.../bindings/clock/sunxi/sun5i-a13-gates.txt | 58 ++++++++++
drivers/clk/sunxi/clk-sunxi.c | 31 ++++--
4 files changed, 187 insertions(+), 112 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 729f524..d495521 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -12,22 +12,30 @@ Required properties:
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
- "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
+ "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
+ "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
"allwinner,sun4i-apb0-clk" - for the APB0 clock
- "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
+ "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
+ "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
- "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
+ "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
+ "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
- "allwinner,sun4i-*-gates-clk" where it shall be set to 1
+ "allwinner,*-gates-clk" where it shall be set to 1
-Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
+Additionally, "allwinner,*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls
+Clock consumers should specify the desired clocks they use with a
+"clocks" phandle cell. Consumers that are using a gated clock should
+provide an additional ID in their clock property. The values of this
+ID are documented in sunxi/<soc>-gates.txt.
+
For example:
osc24M: osc24M at 01c20050 {
@@ -50,102 +58,3 @@ cpu: cpu at 01c20054 {
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};
-
-
-
-Gate clock outputs
-
-The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
-their corresponding offsets as present on sun4i are listed below. Note that
-some of these gates are not present on sun5i.
-
- * AXI gates ("allwinner,sun4i-axi-gates-clk")
-
- DRAM 0
-
- * AHB gates ("allwinner,sun4i-ahb-gates-clk")
-
- USB0 0
- EHCI0 1
- OHCI0 2*
- EHCI1 3
- OHCI1 4*
- SS 5
- DMA 6
- BIST 7
- MMC0 8
- MMC1 9
- MMC2 10
- MMC3 11
- MS 12**
- NAND 13
- SDRAM 14
-
- ACE 16
- EMAC 17
- TS 18
-
- SPI0 20
- SPI1 21
- SPI2 22
- SPI3 23
- PATA 24
- SATA 25**
- GPS 26*
-
- VE 32
- TVD 33
- TVE0 34
- TVE1 35
- LCD0 36
- LCD1 37
-
- CSI0 40
- CSI1 41
-
- HDMI 43
- DE_BE0 44
- DE_BE1 45
- DE_FE0 46
- DE_FE1 47
-
- MP 50
-
- MALI400 52
-
- * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
-
- CODEC 0
- SPDIF 1*
- AC97 2
- IIS 3
-
- PIO 5
- IR0 6
- IR1 7
-
- KEYPAD 10
-
- * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
-
- I2C0 0
- I2C1 1
- I2C2 2
-
- CAN 4
- SCR 5
- PS20 6
- PS21 7
-
- UART0 16
- UART1 17
- UART2 18
- UART3 19
- UART4 20
- UART5 21
- UART6 22
- UART7 23
-
-Notation:
- [*]: The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
new file mode 100644
index 0000000..6a03475
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
@@ -0,0 +1,93 @@
+Gate clock outputs
+------------------
+
+ * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+ DRAM 0
+
+ * AHB gates ("allwinner,sun4i-ahb-gates-clk")
+
+ USB0 0
+ EHCI0 1
+ OHCI0 2*
+ EHCI1 3
+ OHCI1 4*
+ SS 5
+ DMA 6
+ BIST 7
+ MMC0 8
+ MMC1 9
+ MMC2 10
+ MMC3 11
+ MS 12**
+ NAND 13
+ SDRAM 14
+
+ ACE 16
+ EMAC 17
+ TS 18
+
+ SPI0 20
+ SPI1 21
+ SPI2 22
+ SPI3 23
+ PATA 24
+ SATA 25**
+ GPS 26*
+
+ VE 32
+ TVD 33
+ TVE0 34
+ TVE1 35
+ LCD0 36
+ LCD1 37
+
+ CSI0 40
+ CSI1 41
+
+ HDMI 43
+ DE_BE0 44
+ DE_BE1 45
+ DE_FE1 46
+ DE_FE1 47
+
+ MP 50
+
+ MALI400 52
+
+ * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
+
+ CODEC 0
+ SPDIF 1*
+ AC97 2
+ IIS 3
+
+ PIO 5
+ IR0 6
+ IR1 7
+
+ KEYPAD 10
+
+ * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
+
+ I2C0 0
+ I2C1 1
+ I2C2 2
+
+ CAN 4
+ SCR 5
+ PS20 6
+ PS21 7
+
+ UART0 16
+ UART1 17
+ UART2 18
+ UART3 19
+ UART4 20
+ UART5 21
+ UART6 22
+ UART7 23
+
+Notation:
+ [*]: The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
new file mode 100644
index 0000000..006b6df
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
@@ -0,0 +1,58 @@
+Gate clock outputs
+------------------
+
+ * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+ DRAM 0
+
+ * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
+
+ USBOTG 0
+ EHCI 1
+ OHCI 2
+
+ SS 5
+ DMA 6
+ BIST 7
+ MMC0 8
+ MMC1 9
+ MMC2 10
+
+ NAND 13
+ SDRAM 14
+
+ SPI0 20
+ SPI1 21
+ SPI2 22
+
+ STIMER 28
+
+ VE 32
+
+ LCD 36
+
+ CSI 40
+
+ DE_BE 44
+
+ DE_FE 46
+
+ IEP 51
+ MALI400 52
+
+ * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
+
+ CODEC 0
+
+ PIO 5
+ IR 6
+
+ * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
+
+ I2C0 0
+ I2C1 1
+ I2C2 2
+
+ UART1 17
+
+ UART3 19
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 8492ad1..930d36f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -333,22 +333,34 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
-static const __initconst struct gates_data axi_gates_data = {
+static const __initconst struct gates_data sun4i_axi_gates_data = {
.mask = {1},
};
-static const __initconst struct gates_data ahb_gates_data = {
+static const __initconst struct gates_data sun4i_ahb_gates_data = {
.mask = {0x7F77FFF, 0x14FB3F},
};
-static const __initconst struct gates_data apb0_gates_data = {
+static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
+ .mask = {0x107067e7, 0x185111},
+};
+
+static const __initconst struct gates_data sun4i_apb0_gates_data = {
.mask = {0x4EF},
};
-static const __initconst struct gates_data apb1_gates_data = {
+static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
+ .mask = {0x61},
+};
+
+static const __initconst struct gates_data sun4i_apb1_gates_data = {
.mask = {0xFF00F7},
};
+static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
+ .mask = {0xa0007},
+};
+
static void __init sunxi_gates_clk_setup(struct device_node *node,
struct gates_data *data)
{
@@ -428,10 +440,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
/* Matches for gate clocks */
static const __initconst struct of_device_id clk_gates_match[] = {
- {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
- {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
- {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
- {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
+ {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
+ {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
+ {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
+ {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
+ {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
+ {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
+ {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
{}
};
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] ARM: sun5i: Update the clock compatible strings
2013-04-30 9:56 [PATCH 0/2] ARM: sunxi: Clock fixes for the Allwinner A13 Maxime Ripard
2013-04-30 9:56 ` [PATCH 1/2] clk: sun5i: Add compatibles for " Maxime Ripard
@ 2013-04-30 9:56 ` Maxime Ripard
2013-04-30 11:32 ` Emilio López
1 sibling, 1 reply; 7+ messages in thread
From: Maxime Ripard @ 2013-04-30 9:56 UTC (permalink / raw)
To: linux-arm-kernel
The Allwinner A13 has a smaller clock set than the one found in the A10.
Fix the A13 device tree and documentation to reflect this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a13.dtsi | 35 ++++++++++++-----------------------
1 file changed, 12 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..8ba65c1 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -95,20 +95,15 @@
ahb_gates: ahb_gates at 01c20060 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
+ compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
+ "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
+ "ahb_de_fe", "ahb_iep", "ahb_mali400";
};
apb0: apb0 at 01c20054 {
@@ -120,15 +115,13 @@
apb0_gates: apb0_gates at 01c20068 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
+ compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
};
- /* dummy is pll62 */
+ /* dummy is pll6 */
apb1_mux: apb1_mux at 01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
@@ -145,15 +138,11 @@
apb1_gates: apb1_gates at 01c2006c {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
+ compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_uart1", "apb1_uart3";
};
};
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/2] clk: sun5i: Add compatibles for Allwinner A13
2013-04-30 9:56 ` [PATCH 1/2] clk: sun5i: Add compatibles for " Maxime Ripard
@ 2013-04-30 11:20 ` Emilio López
2013-05-14 19:26 ` Mike Turquette
0 siblings, 1 reply; 7+ messages in thread
From: Emilio López @ 2013-04-30 11:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
El 30/04/13 06:56, Maxime Ripard escribi?:
> The A13 has a lot less clocks than the one found in the Allwinner A10.
> Add these stripped down clocks to the clock driver and in the
> documentation.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch looks good to me.
Acked-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 117 +++------------------
> .../bindings/clock/sunxi/sun4i-a10-gates.txt | 93 ++++++++++++++++
> .../bindings/clock/sunxi/sun5i-a13-gates.txt | 58 ++++++++++
> drivers/clk/sunxi/clk-sunxi.c | 31 ++++--
> 4 files changed, 187 insertions(+), 112 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 729f524..d495521 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -12,22 +12,30 @@ Required properties:
> "allwinner,sun4i-axi-clk" - for the AXI clock
> "allwinner,sun4i-axi-gates-clk" - for the AXI gates
> "allwinner,sun4i-ahb-clk" - for the AHB clock
> - "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
> + "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
> + "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
> "allwinner,sun4i-apb0-clk" - for the APB0 clock
> - "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
> + "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
> + "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
> "allwinner,sun4i-apb1-clk" - for the APB1 clock
> "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
> - "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
> + "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
> + "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> - clocks : shall be the input parent clock(s) phandle for the clock
> - #clock-cells : from common clock binding; shall be set to 0 except for
> - "allwinner,sun4i-*-gates-clk" where it shall be set to 1
> + "allwinner,*-gates-clk" where it shall be set to 1
>
> -Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
> +Additionally, "allwinner,*-gates-clk" clocks require:
> - clock-output-names : the corresponding gate names that the clock controls
>
> +Clock consumers should specify the desired clocks they use with a
> +"clocks" phandle cell. Consumers that are using a gated clock should
> +provide an additional ID in their clock property. The values of this
> +ID are documented in sunxi/<soc>-gates.txt.
> +
> For example:
>
> osc24M: osc24M at 01c20050 {
> @@ -50,102 +58,3 @@ cpu: cpu at 01c20054 {
> reg = <0x01c20054 0x4>;
> clocks = <&osc32k>, <&osc24M>, <&pll1>;
> };
> -
> -
> -
> -Gate clock outputs
> -
> -The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
> -their corresponding offsets as present on sun4i are listed below. Note that
> -some of these gates are not present on sun5i.
> -
> - * AXI gates ("allwinner,sun4i-axi-gates-clk")
> -
> - DRAM 0
> -
> - * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> -
> - USB0 0
> - EHCI0 1
> - OHCI0 2*
> - EHCI1 3
> - OHCI1 4*
> - SS 5
> - DMA 6
> - BIST 7
> - MMC0 8
> - MMC1 9
> - MMC2 10
> - MMC3 11
> - MS 12**
> - NAND 13
> - SDRAM 14
> -
> - ACE 16
> - EMAC 17
> - TS 18
> -
> - SPI0 20
> - SPI1 21
> - SPI2 22
> - SPI3 23
> - PATA 24
> - SATA 25**
> - GPS 26*
> -
> - VE 32
> - TVD 33
> - TVE0 34
> - TVE1 35
> - LCD0 36
> - LCD1 37
> -
> - CSI0 40
> - CSI1 41
> -
> - HDMI 43
> - DE_BE0 44
> - DE_BE1 45
> - DE_FE0 46
> - DE_FE1 47
> -
> - MP 50
> -
> - MALI400 52
> -
> - * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> -
> - CODEC 0
> - SPDIF 1*
> - AC97 2
> - IIS 3
> -
> - PIO 5
> - IR0 6
> - IR1 7
> -
> - KEYPAD 10
> -
> - * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> -
> - I2C0 0
> - I2C1 1
> - I2C2 2
> -
> - CAN 4
> - SCR 5
> - PS20 6
> - PS21 7
> -
> - UART0 16
> - UART1 17
> - UART2 18
> - UART3 19
> - UART4 20
> - UART5 21
> - UART6 22
> - UART7 23
> -
> -Notation:
> - [*]: The datasheet didn't mention these, but they are present on AW code
> - [**]: The datasheet had this marked as "NC" but they are used on AW code
> diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> new file mode 100644
> index 0000000..6a03475
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> @@ -0,0 +1,93 @@
> +Gate clock outputs
> +------------------
> +
> + * AXI gates ("allwinner,sun4i-axi-gates-clk")
> +
> + DRAM 0
> +
> + * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> +
> + USB0 0
> + EHCI0 1
> + OHCI0 2*
> + EHCI1 3
> + OHCI1 4*
> + SS 5
> + DMA 6
> + BIST 7
> + MMC0 8
> + MMC1 9
> + MMC2 10
> + MMC3 11
> + MS 12**
> + NAND 13
> + SDRAM 14
> +
> + ACE 16
> + EMAC 17
> + TS 18
> +
> + SPI0 20
> + SPI1 21
> + SPI2 22
> + SPI3 23
> + PATA 24
> + SATA 25**
> + GPS 26*
> +
> + VE 32
> + TVD 33
> + TVE0 34
> + TVE1 35
> + LCD0 36
> + LCD1 37
> +
> + CSI0 40
> + CSI1 41
> +
> + HDMI 43
> + DE_BE0 44
> + DE_BE1 45
> + DE_FE1 46
> + DE_FE1 47
> +
> + MP 50
> +
> + MALI400 52
> +
> + * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> +
> + CODEC 0
> + SPDIF 1*
> + AC97 2
> + IIS 3
> +
> + PIO 5
> + IR0 6
> + IR1 7
> +
> + KEYPAD 10
> +
> + * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> +
> + I2C0 0
> + I2C1 1
> + I2C2 2
> +
> + CAN 4
> + SCR 5
> + PS20 6
> + PS21 7
> +
> + UART0 16
> + UART1 17
> + UART2 18
> + UART3 19
> + UART4 20
> + UART5 21
> + UART6 22
> + UART7 23
> +
> +Notation:
> + [*]: The datasheet didn't mention these, but they are present on AW code
> + [**]: The datasheet had this marked as "NC" but they are used on AW code
> diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> new file mode 100644
> index 0000000..006b6df
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> @@ -0,0 +1,58 @@
> +Gate clock outputs
> +------------------
> +
> + * AXI gates ("allwinner,sun4i-axi-gates-clk")
> +
> + DRAM 0
> +
> + * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
> +
> + USBOTG 0
> + EHCI 1
> + OHCI 2
> +
> + SS 5
> + DMA 6
> + BIST 7
> + MMC0 8
> + MMC1 9
> + MMC2 10
> +
> + NAND 13
> + SDRAM 14
> +
> + SPI0 20
> + SPI1 21
> + SPI2 22
> +
> + STIMER 28
> +
> + VE 32
> +
> + LCD 36
> +
> + CSI 40
> +
> + DE_BE 44
> +
> + DE_FE 46
> +
> + IEP 51
> + MALI400 52
> +
> + * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
> +
> + CODEC 0
> +
> + PIO 5
> + IR 6
> +
> + * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
> +
> + I2C0 0
> + I2C1 1
> + I2C2 2
> +
> + UART1 17
> +
> + UART3 19
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 8492ad1..930d36f 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -333,22 +333,34 @@ struct gates_data {
> DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> };
>
> -static const __initconst struct gates_data axi_gates_data = {
> +static const __initconst struct gates_data sun4i_axi_gates_data = {
> .mask = {1},
> };
>
> -static const __initconst struct gates_data ahb_gates_data = {
> +static const __initconst struct gates_data sun4i_ahb_gates_data = {
> .mask = {0x7F77FFF, 0x14FB3F},
> };
>
> -static const __initconst struct gates_data apb0_gates_data = {
> +static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
> + .mask = {0x107067e7, 0x185111},
If you send a v2 please use uppercase e and a below for consistency.
> +};
> +
> +static const __initconst struct gates_data sun4i_apb0_gates_data = {
> .mask = {0x4EF},
> };
>
> -static const __initconst struct gates_data apb1_gates_data = {
> +static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
> + .mask = {0x61},
> +};
> +
> +static const __initconst struct gates_data sun4i_apb1_gates_data = {
> .mask = {0xFF00F7},
> };
>
> +static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
> + .mask = {0xa0007},
> +};
> +
> static void __init sunxi_gates_clk_setup(struct device_node *node,
> struct gates_data *data)
> {
> @@ -428,10 +440,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
>
> /* Matches for gate clocks */
> static const __initconst struct of_device_id clk_gates_match[] = {
> - {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> - {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> - {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> - {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
> + {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
> + {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
> + {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
> {}
> };
>
>
Thanks!
Emilio
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] ARM: sun5i: Update the clock compatible strings
2013-04-30 9:56 ` [PATCH 2/2] ARM: sun5i: Update the clock compatible strings Maxime Ripard
@ 2013-04-30 11:32 ` Emilio López
2013-05-15 8:53 ` Maxime Ripard
0 siblings, 1 reply; 7+ messages in thread
From: Emilio López @ 2013-04-30 11:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
El 30/04/13 06:56, Maxime Ripard escribi?:
> The Allwinner A13 has a smaller clock set than the one found in the A10.
> Fix the A13 device tree and documentation to reflect this.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The patch looks fine to me.
Acked-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> arch/arm/boot/dts/sun5i-a13.dtsi | 35 ++++++++++++-----------------------
> 1 file changed, 12 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
> index 31fa38f..8ba65c1 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -95,20 +95,15 @@
>
> ahb_gates: ahb_gates at 01c20060 {
> #clock-cells = <1>;
> - compatible = "allwinner,sun4i-ahb-gates-clk";
> + compatible = "allwinner,sun5i-a13-ahb-gates-clk";
> reg = <0x01c20060 0x8>;
> clocks = <&ahb>;
> - clock-output-names = "ahb_usb0", "ahb_ehci0",
> - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
> - "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
> - "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
> - "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
> - "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
> - "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
> - "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
> - "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
> - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
> - "ahb_de_fe1", "ahb_mp", "ahb_mali400";
> + clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
Should we keep the USB and DE names consistent between sun4i and sun5i?
Nobody should be referencing them by name, however, so it wouldn't cause
any issues on the long run.
> + "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
> + "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
> + "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
> + "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
> + "ahb_de_fe", "ahb_iep", "ahb_mali400";
> };
>
> apb0: apb0 at 01c20054 {
> @@ -120,15 +115,13 @@
>
> apb0_gates: apb0_gates at 01c20068 {
> #clock-cells = <1>;
> - compatible = "allwinner,sun4i-apb0-gates-clk";
> + compatible = "allwinner,sun5i-a13-apb0-gates-clk";
> reg = <0x01c20068 0x4>;
> clocks = <&apb0>;
> - clock-output-names = "apb0_codec", "apb0_spdif",
> - "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
> - "apb0_ir1", "apb0_keypad";
> + clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
> };
>
> - /* dummy is pll62 */
> + /* dummy is pll6 */
> apb1_mux: apb1_mux at 01c20058 {
> #clock-cells = <0>;
> compatible = "allwinner,sun4i-apb1-mux-clk";
> @@ -145,15 +138,11 @@
>
> apb1_gates: apb1_gates at 01c2006c {
> #clock-cells = <1>;
> - compatible = "allwinner,sun4i-apb1-gates-clk";
> + compatible = "allwinner,sun5i-a13-apb1-gates-clk";
> reg = <0x01c2006c 0x4>;
> clocks = <&apb1>;
> clock-output-names = "apb1_i2c0", "apb1_i2c1",
> - "apb1_i2c2", "apb1_can", "apb1_scr",
> - "apb1_ps20", "apb1_ps21", "apb1_uart0",
> - "apb1_uart1", "apb1_uart2", "apb1_uart3",
> - "apb1_uart4", "apb1_uart5", "apb1_uart6",
> - "apb1_uart7";
> + "apb1_i2c2", "apb1_uart1", "apb1_uart3";
> };
> };
>
>
Thanks,
Emilio
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] clk: sun5i: Add compatibles for Allwinner A13
2013-04-30 11:20 ` Emilio López
@ 2013-05-14 19:26 ` Mike Turquette
0 siblings, 0 replies; 7+ messages in thread
From: Mike Turquette @ 2013-05-14 19:26 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-04-30 04:20:23)
> Hi Maxime,
>
> El 30/04/13 06:56, Maxime Ripard escribi?:
> > The A13 has a lot less clocks than the one found in the Allwinner A10.
> > Add these stripped down clocks to the clock driver and in the
> > documentation.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> This patch looks good to me.
>
> Acked-by: Emilio L?pez <emilio@elopez.com.ar>
>
I've taken patch #1 into clk-next.
Thanks!
Mike
> > ---
> > Documentation/devicetree/bindings/clock/sunxi.txt | 117 +++------------------
> > .../bindings/clock/sunxi/sun4i-a10-gates.txt | 93 ++++++++++++++++
> > .../bindings/clock/sunxi/sun5i-a13-gates.txt | 58 ++++++++++
> > drivers/clk/sunxi/clk-sunxi.c | 31 ++++--
> > 4 files changed, 187 insertions(+), 112 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> > create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> >
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> > index 729f524..d495521 100644
> > --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> > @@ -12,22 +12,30 @@ Required properties:
> > "allwinner,sun4i-axi-clk" - for the AXI clock
> > "allwinner,sun4i-axi-gates-clk" - for the AXI gates
> > "allwinner,sun4i-ahb-clk" - for the AHB clock
> > - "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
> > + "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
> > + "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
> > "allwinner,sun4i-apb0-clk" - for the APB0 clock
> > - "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
> > + "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
> > + "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
> > "allwinner,sun4i-apb1-clk" - for the APB1 clock
> > "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
> > - "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
> > + "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
> > + "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
> >
> > Required properties for all clocks:
> > - reg : shall be the control register address for the clock.
> > - clocks : shall be the input parent clock(s) phandle for the clock
> > - #clock-cells : from common clock binding; shall be set to 0 except for
> > - "allwinner,sun4i-*-gates-clk" where it shall be set to 1
> > + "allwinner,*-gates-clk" where it shall be set to 1
> >
> > -Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
> > +Additionally, "allwinner,*-gates-clk" clocks require:
> > - clock-output-names : the corresponding gate names that the clock controls
> >
> > +Clock consumers should specify the desired clocks they use with a
> > +"clocks" phandle cell. Consumers that are using a gated clock should
> > +provide an additional ID in their clock property. The values of this
> > +ID are documented in sunxi/<soc>-gates.txt.
> > +
> > For example:
> >
> > osc24M: osc24M at 01c20050 {
> > @@ -50,102 +58,3 @@ cpu: cpu at 01c20054 {
> > reg = <0x01c20054 0x4>;
> > clocks = <&osc32k>, <&osc24M>, <&pll1>;
> > };
> > -
> > -
> > -
> > -Gate clock outputs
> > -
> > -The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
> > -their corresponding offsets as present on sun4i are listed below. Note that
> > -some of these gates are not present on sun5i.
> > -
> > - * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > -
> > - DRAM 0
> > -
> > - * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> > -
> > - USB0 0
> > - EHCI0 1
> > - OHCI0 2*
> > - EHCI1 3
> > - OHCI1 4*
> > - SS 5
> > - DMA 6
> > - BIST 7
> > - MMC0 8
> > - MMC1 9
> > - MMC2 10
> > - MMC3 11
> > - MS 12**
> > - NAND 13
> > - SDRAM 14
> > -
> > - ACE 16
> > - EMAC 17
> > - TS 18
> > -
> > - SPI0 20
> > - SPI1 21
> > - SPI2 22
> > - SPI3 23
> > - PATA 24
> > - SATA 25**
> > - GPS 26*
> > -
> > - VE 32
> > - TVD 33
> > - TVE0 34
> > - TVE1 35
> > - LCD0 36
> > - LCD1 37
> > -
> > - CSI0 40
> > - CSI1 41
> > -
> > - HDMI 43
> > - DE_BE0 44
> > - DE_BE1 45
> > - DE_FE0 46
> > - DE_FE1 47
> > -
> > - MP 50
> > -
> > - MALI400 52
> > -
> > - * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> > -
> > - CODEC 0
> > - SPDIF 1*
> > - AC97 2
> > - IIS 3
> > -
> > - PIO 5
> > - IR0 6
> > - IR1 7
> > -
> > - KEYPAD 10
> > -
> > - * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> > -
> > - I2C0 0
> > - I2C1 1
> > - I2C2 2
> > -
> > - CAN 4
> > - SCR 5
> > - PS20 6
> > - PS21 7
> > -
> > - UART0 16
> > - UART1 17
> > - UART2 18
> > - UART3 19
> > - UART4 20
> > - UART5 21
> > - UART6 22
> > - UART7 23
> > -
> > -Notation:
> > - [*]: The datasheet didn't mention these, but they are present on AW code
> > - [**]: The datasheet had this marked as "NC" but they are used on AW code
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> > new file mode 100644
> > index 0000000..6a03475
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
> > @@ -0,0 +1,93 @@
> > +Gate clock outputs
> > +------------------
> > +
> > + * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > +
> > + DRAM 0
> > +
> > + * AHB gates ("allwinner,sun4i-ahb-gates-clk")
> > +
> > + USB0 0
> > + EHCI0 1
> > + OHCI0 2*
> > + EHCI1 3
> > + OHCI1 4*
> > + SS 5
> > + DMA 6
> > + BIST 7
> > + MMC0 8
> > + MMC1 9
> > + MMC2 10
> > + MMC3 11
> > + MS 12**
> > + NAND 13
> > + SDRAM 14
> > +
> > + ACE 16
> > + EMAC 17
> > + TS 18
> > +
> > + SPI0 20
> > + SPI1 21
> > + SPI2 22
> > + SPI3 23
> > + PATA 24
> > + SATA 25**
> > + GPS 26*
> > +
> > + VE 32
> > + TVD 33
> > + TVE0 34
> > + TVE1 35
> > + LCD0 36
> > + LCD1 37
> > +
> > + CSI0 40
> > + CSI1 41
> > +
> > + HDMI 43
> > + DE_BE0 44
> > + DE_BE1 45
> > + DE_FE1 46
> > + DE_FE1 47
> > +
> > + MP 50
> > +
> > + MALI400 52
> > +
> > + * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
> > +
> > + CODEC 0
> > + SPDIF 1*
> > + AC97 2
> > + IIS 3
> > +
> > + PIO 5
> > + IR0 6
> > + IR1 7
> > +
> > + KEYPAD 10
> > +
> > + * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
> > +
> > + I2C0 0
> > + I2C1 1
> > + I2C2 2
> > +
> > + CAN 4
> > + SCR 5
> > + PS20 6
> > + PS21 7
> > +
> > + UART0 16
> > + UART1 17
> > + UART2 18
> > + UART3 19
> > + UART4 20
> > + UART5 21
> > + UART6 22
> > + UART7 23
> > +
> > +Notation:
> > + [*]: The datasheet didn't mention these, but they are present on AW code
> > + [**]: The datasheet had this marked as "NC" but they are used on AW code
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> > new file mode 100644
> > index 0000000..006b6df
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
> > @@ -0,0 +1,58 @@
> > +Gate clock outputs
> > +------------------
> > +
> > + * AXI gates ("allwinner,sun4i-axi-gates-clk")
> > +
> > + DRAM 0
> > +
> > + * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
> > +
> > + USBOTG 0
> > + EHCI 1
> > + OHCI 2
> > +
> > + SS 5
> > + DMA 6
> > + BIST 7
> > + MMC0 8
> > + MMC1 9
> > + MMC2 10
> > +
> > + NAND 13
> > + SDRAM 14
> > +
> > + SPI0 20
> > + SPI1 21
> > + SPI2 22
> > +
> > + STIMER 28
> > +
> > + VE 32
> > +
> > + LCD 36
> > +
> > + CSI 40
> > +
> > + DE_BE 44
> > +
> > + DE_FE 46
> > +
> > + IEP 51
> > + MALI400 52
> > +
> > + * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
> > +
> > + CODEC 0
> > +
> > + PIO 5
> > + IR 6
> > +
> > + * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
> > +
> > + I2C0 0
> > + I2C1 1
> > + I2C2 2
> > +
> > + UART1 17
> > +
> > + UART3 19
> > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> > index 8492ad1..930d36f 100644
> > --- a/drivers/clk/sunxi/clk-sunxi.c
> > +++ b/drivers/clk/sunxi/clk-sunxi.c
> > @@ -333,22 +333,34 @@ struct gates_data {
> > DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> > };
> >
> > -static const __initconst struct gates_data axi_gates_data = {
> > +static const __initconst struct gates_data sun4i_axi_gates_data = {
> > .mask = {1},
> > };
> >
> > -static const __initconst struct gates_data ahb_gates_data = {
> > +static const __initconst struct gates_data sun4i_ahb_gates_data = {
> > .mask = {0x7F77FFF, 0x14FB3F},
> > };
> >
> > -static const __initconst struct gates_data apb0_gates_data = {
> > +static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
> > + .mask = {0x107067e7, 0x185111},
>
> If you send a v2 please use uppercase e and a below for consistency.
>
> > +};
> > +
> > +static const __initconst struct gates_data sun4i_apb0_gates_data = {
> > .mask = {0x4EF},
> > };
> >
> > -static const __initconst struct gates_data apb1_gates_data = {
> > +static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
> > + .mask = {0x61},
> > +};
> > +
> > +static const __initconst struct gates_data sun4i_apb1_gates_data = {
> > .mask = {0xFF00F7},
> > };
> >
> > +static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
> > + .mask = {0xa0007},
>
> > +};
> > +
> > static void __init sunxi_gates_clk_setup(struct device_node *node,
> > struct gates_data *data)
> > {
> > @@ -428,10 +440,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
> >
> > /* Matches for gate clocks */
> > static const __initconst struct of_device_id clk_gates_match[] = {
> > - {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> > - {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> > - {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> > - {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> > + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
> > + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
> > + {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
> > + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
> > + {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> > + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
> > + {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
> > {}
> > };
> >
> >
>
> Thanks!
>
> Emilio
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] ARM: sun5i: Update the clock compatible strings
2013-04-30 11:32 ` Emilio López
@ 2013-05-15 8:53 ` Maxime Ripard
0 siblings, 0 replies; 7+ messages in thread
From: Maxime Ripard @ 2013-05-15 8:53 UTC (permalink / raw)
To: linux-arm-kernel
Le 30/04/2013 13:32, Emilio L?pez a ?crit :
> Hi Maxime,
>
> El 30/04/13 06:56, Maxime Ripard escribi?:
>> The Allwinner A13 has a smaller clock set than the one found in the A10.
>> Fix the A13 device tree and documentation to reflect this.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> The patch looks fine to me.
>
> Acked-by: Emilio L?pez <emilio@elopez.com.ar>
Ok, I just applied it to sunxi/dt-for-3.11
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-05-15 8:53 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-04-30 9:56 [PATCH 0/2] ARM: sunxi: Clock fixes for the Allwinner A13 Maxime Ripard
2013-04-30 9:56 ` [PATCH 1/2] clk: sun5i: Add compatibles for " Maxime Ripard
2013-04-30 11:20 ` Emilio López
2013-05-14 19:26 ` Mike Turquette
2013-04-30 9:56 ` [PATCH 2/2] ARM: sun5i: Update the clock compatible strings Maxime Ripard
2013-04-30 11:32 ` Emilio López
2013-05-15 8:53 ` Maxime Ripard
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