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From: "Heiko Stübner" <heiko@sntech.de>
To: cristian.ciocaltea@collabora.com,
	Jianfeng Liu <liujianfeng1994@gmail.com>
Cc: airlied@gmail.com, andy.yan@rock-chips.com, conor+dt@kernel.org,
	devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
	hjc@rock-chips.com, kernel@collabora.com, krzk+dt@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
	maarten.lankhorst@linux.intel.com, mripard@kernel.org,
	robh@kernel.org, simona@ffwll.ch, tzimmermann@suse.de
Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588
Date: Mon, 17 Feb 2025 15:33:41 +0100	[thread overview]
Message-ID: <5190979.MSiuQNM8U4@diego> (raw)
In-Reply-To: <20250217024437.35155-1-liujianfeng1994@gmail.com>

Am Montag, 17. Februar 2025, 03:44:37 MEZ schrieb Jianfeng Liu:
> Hi Cristian,
> 
> On Sat, 15 Feb 2025 02:55:39 +0200, Cristian Ciocaltea wrote:
> >The HDMI1 PHY PLL clock source cannot be added directly to vop node in
> >rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
> >optional feature and its PHY node belongs to a separate (extra) DT file.
> >
> >Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
> >clocks & clock-names properties in the extra DT file.
> 
> There are boards that only use hdmi1 such as ROCK 5 ITX. So there are two
> choices for this board:
> 
> 1, Enable hdptxphy0 as dependency of vop although it is not really used.
> 
> 2, Overwrite vop node at board dts to make it only use hdptxphy1 like:
> 
> &vop {
> 	clocks = <&cru ACLK_VOP>,
> 		 <&cru HCLK_VOP>,
> 		 <&cru DCLK_VOP0>,
> 		 <&cru DCLK_VOP1>,
> 		 <&cru DCLK_VOP2>,
> 		 <&cru DCLK_VOP3>,
> 		 <&cru PCLK_VOP_ROOT>,
> 		 <&hdptxphy1>;
> 	clock-names = "aclk",
> 		      "hclk",
> 		      "dclk_vp0",
> 		      "dclk_vp1",
> 		      "dclk_vp2",
> 		      "dclk_vp3",
> 		      "pclk_vop",
> 		      "pll_hdmiphy1";
> };
> 
> What do you think of these two method?

Going by the code in patch1 (+drm-misc) we have:
  vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0");
+
  vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1");

So the clock-reference to hdptxphy0 should just result in vop2->pll_hdmiphy0
being NULL and thus ignored further on?




  reply	other threads:[~2025-02-17 14:49 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-15  0:55 [PATCH 0/4] Improve Rockchip VOP2 display modes handling on RK3588 HDMI1 Cristian Ciocaltea
2025-02-15  0:55 ` [PATCH 1/4] drm/rockchip: vop2: Improve " Cristian Ciocaltea
2025-02-15  0:55 ` [PATCH 2/4] arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 Cristian Ciocaltea
2025-02-15  0:55 ` [PATCH 3/4] arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 " Cristian Ciocaltea
2025-02-17  2:44   ` Jianfeng Liu
2025-02-17 14:33     ` Heiko Stübner [this message]
2025-02-17 23:33       ` [PATCH " Cristian Ciocaltea
2025-02-18  3:38         ` Jianfeng Liu
2025-02-18  9:52         ` Jianfeng Liu
2025-02-18 10:00           ` Heiko Stübner
2025-02-18 12:17             ` Jianfeng Liu
2025-02-18 14:13               ` Sebastian Reichel
2025-02-18 14:53                 ` Heiko Stübner
2025-02-18 16:05                   ` Sebastian Reichel
2025-02-18 23:40                     ` Cristian Ciocaltea
2025-02-22  6:10                   ` Johannes Erdfelt
2025-02-15  0:55 ` [PATCH 4/4] arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1 Cristian Ciocaltea

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