* [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
2013-05-13 16:46 ` Stephen Warren
2013-05-13 16:47 ` Stephen Warren
2013-05-13 11:07 ` [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines Hiroshi Doyu
` (4 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
To replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
.../bindings/clock/nvidia,tegra20-car.txt | 152 +-------------------
include/dt-bindings/clk/tegra20-car.h | 158 +++++++++++++++++++++
2 files changed, 161 insertions(+), 149 deletions(-)
create mode 100644 include/dt-bindings/clk/tegra20-car.h
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680..edc30f6 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra20 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
+You can find the actual assignment in "dt-bindings/clk/tegra20-car.h"
+
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
@@ -14,154 +16,6 @@ Required properties :
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
- The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 95 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 96 and
- above.
-
- 0 cpu
- 1 unassigned
- 2 unassigned
- 3 ac97
- 4 rtc
- 5 tmr
- 6 uart1
- 7 unassigned (register bit affects uart2 and vfir)
- 8 gpio
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 twc
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 ide
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 unassigned
- 31 cache2
-
- 32 mem
- 33 ahbdma
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 stat_mon
- 38 pmc
- 39 fuse
- 40 kfuse
- 41 sbc1
- 42 snor
- 43 spi1
- 44 sbc2
- 45 xio
- 46 sbc3
- 47 dvc
- 48 dsi
- 49 unassigned (register bit affects tvo and cve)
- 50 mipi
- 51 hdmi
- 52 csi
- 53 tvdac
- 54 i2c2
- 55 uart3
- 56 unassigned
- 57 emc
- 58 usb2
- 59 usb3
- 60 mpe
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 speedo
- 65 uart4
- 66 uart5
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 pcie
- 71 owr
- 72 afi
- 73 csite
- 74 unassigned
- 75 avpucq
- 76 la
- 77 unassigned
- 78 unassigned
- 79 unassigned
- 80 unassigned
- 81 unassigned
- 82 unassigned
- 83 unassigned
- 84 irama
- 85 iramb
- 86 iramc
- 87 iramd
- 88 cram2
- 89 audio_2x a/k/a audio_2x_sync_clk
- 90 clk_d
- 91 unassigned
- 92 sus
- 93 cdev2
- 94 cdev1
- 95 unassigned
-
- 96 uart2
- 97 vfir
- 98 spdif_in
- 99 spdif_out
- 100 vi
- 101 vi_sensor
- 102 tvo
- 103 cve
- 104 osc
- 105 clk_32k a/k/a clk_s
- 106 clk_m
- 107 sclk
- 108 cclk
- 109 hclk
- 110 pclk
- 111 blink
- 112 pll_a
- 113 pll_a_out0
- 114 pll_c
- 115 pll_c_out1
- 116 pll_d
- 117 pll_d_out0
- 118 pll_e
- 119 pll_m
- 120 pll_m_out1
- 121 pll_p
- 122 pll_p_out1
- 123 pll_p_out2
- 124 pll_p_out3
- 125 pll_p_out4
- 126 pll_s
- 127 pll_u
- 128 pll_x
- 129 cop a/k/a avp
- 130 audio a/k/a audio_sync_clk
- 131 pll_ref
- 132 twd
-
Example SoC include file:
/ {
@@ -172,7 +26,7 @@ Example SoC include file:
};
usb at c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA20_CLK_USB2>; /* usb2 */
};
};
diff --git a/include/dt-bindings/clk/tegra20-car.h b/include/dt-bindings/clk/tegra20-car.h
new file mode 100644
index 0000000..e30b4bd
--- /dev/null
+++ b/include/dt-bindings/clk/tegra20-car.h
@@ -0,0 +1,158 @@
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA20_CAR_H
+
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+
+#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+#define TEGRA20_CLK_PCIE_XCLK 74
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+
+#endif /* _DT_BINDINGS_CLK_TEGRA20_CAR_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
2013-05-13 11:07 ` [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs Hiroshi Doyu
@ 2013-05-13 16:46 ` Stephen Warren
2013-05-14 5:59 ` Hiroshi Doyu
2013-05-13 16:47 ` Stephen Warren
1 sibling, 1 reply; 11+ messages in thread
From: Stephen Warren @ 2013-05-13 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
>
> - clocks = <&tegra_car 28>;
> + clocks = <&tegra_car CLK_HOST1X>;
I'd like slightly more description of the change here. What about:
=====
Create a header file to define the clock IDs used by the Tegra20 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.
This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
=====
I'm not sure exactly how these patches will get merged. For you
reference, I anticipate one of two things happening:
1)
* Patches 1, 3, 5 get put into a topic branch, and merged into both the
clk tree and the Tegra tree.
* Patches 2, 4, 6 get merged into the Tegra tree.
* The patches you're going to create for the drivers/clk code get merged
into Mike's clk tree
2)
* Mike ack's the patches you're going to create for the drivers/clk code.
* Everything gets merged through the Tegra tree.
This shouldn't impact you much, but just be aware that the drivers/clk
changes you create shouldn't depend on anything beyond patches 1, 3, 5
here and 3.10-rc1, then I can work out the merging with Mike without any
constraints.
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
> This binding uses the common clock binding:
> Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> +You can find the actual assignment in "dt-bindings/clk/tegra20-car.h"
Can you move this text down into the description of clock-cells, i.e.
where you removed the original list of IDs? That'll keep the text in the
place it's most useful. I would also like to explicitly mention "include
file" and use <> rather than "", since that matches the syntax that
should be used in .dts files, i.e.:
=====
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clk/tegra20-car.h>.
=====
Similar comments for patches 3 and 5.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
2013-05-13 16:46 ` Stephen Warren
@ 2013-05-14 5:59 ` Hiroshi Doyu
0 siblings, 0 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Stephen Warren <swarren@wwwdotorg.org> wrote @ Mon, 13 May 2013 18:46:27 +0200:
> I'm not sure exactly how these patches will get merged. For you
> reference, I anticipate one of two things happening:
>
> 1)
>
> * Patches 1, 3, 5 get put into a topic branch, and merged into both the
> clk tree and the Tegra tree.
>
> * Patches 2, 4, 6 get merged into the Tegra tree.
>
> * The patches you're going to create for the drivers/clk code get merged
> into Mike's clk tree
>
> 2)
>
> * Mike ack's the patches you're going to create for the drivers/clk code.
>
> * Everything gets merged through the Tegra tree.
>
> This shouldn't impact you much, but just be aware that the drivers/clk
> changes you create shouldn't depend on anything beyond patches 1, 3, 5
> here and 3.10-rc1, then I can work out the merging with Mike without any
> constraints.
Either way would work. Once Venu's USB patches are merged, mentioned
in [2/6], I'll resend the update version of this series.
drivers/clk/tegra replacement will follow, then.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs
2013-05-13 11:07 ` [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs Hiroshi Doyu
2013-05-13 16:46 ` Stephen Warren
@ 2013-05-13 16:47 ` Stephen Warren
1 sibling, 0 replies; 11+ messages in thread
From: Stephen Warren @ 2013-05-13 16:47 UTC (permalink / raw)
To: linux-arm-kernel
On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> To replace magic number in tegra_car:
>
> - clocks = <&tegra_car 28>;
> + clocks = <&tegra_car CLK_HOST1X>;
> @@ -172,7 +26,7 @@ Example SoC include file:
> };
>
> usb at c5004000 {
> - clocks = <&tegra_car 58>; /* usb2 */
> + clocks = <&tegra_car TEGRA20_CLK_USB2>; /* usb2 */
I forgot to mention: That comment isn't useful any more, since it's
obvious this represents the USB2 clock now that the actual cell data
uses a define.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
2013-05-13 16:54 ` Stephen Warren
2013-05-13 11:07 ` [PATCH 3/6] ARM: tegra30: create a DT header defining CLK IDs Hiroshi Doyu
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 4 +-
arch/arm/boot/dts/tegra20-harmony.dts | 4 +-
arch/arm/boot/dts/tegra20-medcom-wide.dts | 4 +-
arch/arm/boot/dts/tegra20-paz00.dts | 7 +-
arch/arm/boot/dts/tegra20-plutux.dts | 4 +-
arch/arm/boot/dts/tegra20-seaboard.dts | 4 +-
arch/arm/boot/dts/tegra20-tec.dts | 4 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 4 +-
arch/arm/boot/dts/tegra20-ventana.dts | 4 +-
arch/arm/boot/dts/tegra20-whistler.dts | 4 +-
arch/arm/boot/dts/tegra20.dtsi | 103 ++++++++++++++++-------------
11 files changed, 89 insertions(+), 57 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index be008f7..7e1b120 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -487,7 +487,9 @@
nvidia,ac97-controller = <&ac97>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index acbba40..ba2a269 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -693,7 +693,9 @@
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 85d5792..7599993 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -59,7 +59,9 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 66f245a..02a5ace 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -277,7 +277,8 @@
clock-frequency = <80000>;
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
- clocks = <&tegra_car 67>, <&tegra_car 124>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
};
@@ -526,7 +527,9 @@
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 3374e16..4277552 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -53,7 +53,9 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4d52f64e..6f0d982 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -833,7 +833,9 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9eaa962..b90a70e 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -54,7 +54,9 @@
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index e6200cf..2a0ac6f 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -408,7 +408,9 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 33ec764..5e5a690 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -645,7 +645,9 @@
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d6cb373..3dfec0b 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -584,7 +584,9 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0500179..f302ef8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra20-car.h>
#include "skeleton.dtsi"
@@ -20,7 +21,7 @@
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
#address-cells = <1>;
#size-cells = <1>;
@@ -31,48 +32,49 @@
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 60>;
+ clocks = <&tegra_car TEGRA20_CLK_MPE>;
};
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 100>;
+ clocks = <&tegra_car TEGRA20_CLK_VI>;
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 19>;
+ clocks = <&tegra_car TEGRA20_CLK_EPP>;
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 23>;
+ clocks = <&tegra_car TEGRA20_CLK_ISP>;
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 21>;
+ clocks = <&tegra_car TEGRA20_CLK_GR2D>;
};
gr3d {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car 24>;
+ clocks = <&tegra_car TEGRA20_CLK_GR3D>;
};
dc at 54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 27>, <&tegra_car 121>;
+ clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+ <&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp1", "parent";
rgb {
@@ -84,7 +86,8 @@
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 26>, <&tegra_car 121>;
+ clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+ <&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp2", "parent";
rgb {
@@ -96,7 +99,8 @@
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 51>, <&tegra_car 117>;
+ clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+ <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
status = "disabled";
};
@@ -105,14 +109,14 @@
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 102>;
+ clocks = <&tegra_car TEGRA20_CLK_TVO>;
status = "disabled";
};
dsi {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car 48>;
+ clocks = <&tegra_car TEGRA20_CLK_DSI>;
status = "disabled";
};
};
@@ -122,7 +126,7 @@
reg = <0x50040600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&tegra_car 132>;
+ clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
intc: interrupt-controller {
@@ -149,7 +153,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 5>;
+ clocks = <&tegra_car TEGRA20_CLK_TIMER>;
};
tegra_car: clock {
@@ -177,7 +181,7 @@
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 34>;
+ clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
};
ahb {
@@ -219,7 +223,7 @@
reg = <0x70002000 0x200>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>;
- clocks = <&tegra_car 3>;
+ clocks = <&tegra_car TEGRA20_CLK_AC97>;
status = "disabled";
};
@@ -228,7 +232,7 @@
reg = <0x70002800 0x200>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>;
- clocks = <&tegra_car 11>;
+ clocks = <&tegra_car TEGRA20_CLK_I2S1>;
status = "disabled";
};
@@ -237,7 +241,7 @@
reg = <0x70002a00 0x200>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 18>;
+ clocks = <&tegra_car TEGRA20_CLK_I2S2>;
status = "disabled";
};
@@ -254,7 +258,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
- clocks = <&tegra_car 6>;
+ clocks = <&tegra_car TEGRA20_CLK_UARTA>;
status = "disabled";
};
@@ -264,7 +268,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
- clocks = <&tegra_car 96>;
+ clocks = <&tegra_car TEGRA20_CLK_UARTB>;
status = "disabled";
};
@@ -274,7 +278,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
- clocks = <&tegra_car 55>;
+ clocks = <&tegra_car TEGRA20_CLK_UARTC>;
status = "disabled";
};
@@ -284,7 +288,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
- clocks = <&tegra_car 65>;
+ clocks = <&tegra_car TEGRA20_CLK_UARTD>;
status = "disabled";
};
@@ -294,7 +298,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
- clocks = <&tegra_car 66>;
+ clocks = <&tegra_car TEGRA20_CLK_UARTE>;
status = "disabled";
};
@@ -302,7 +306,7 @@
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
- clocks = <&tegra_car 17>;
+ clocks = <&tegra_car TEGRA20_CLK_PWM>;
status = "disabled";
};
@@ -310,7 +314,7 @@
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 4>;
+ clocks = <&tegra_car TEGRA20_CLK_RTC>;
};
i2c at 7000c000 {
@@ -319,7 +323,8 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 12>, <&tegra_car 124>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -331,7 +336,7 @@
nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 43>;
+ clocks = <&tegra_car TEGRA20_CLK_SPI>;
status = "disabled";
};
@@ -341,7 +346,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 54>, <&tegra_car 124>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -352,7 +358,8 @@
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 67>, <&tegra_car 124>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -363,7 +370,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 47>, <&tegra_car 124>;
+ clocks = <&tegra_car TEGRA20_CLK_DVC>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -375,7 +383,7 @@
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 41>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC1>;
status = "disabled";
};
@@ -386,7 +394,7 @@
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 44>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC2>;
status = "disabled";
};
@@ -397,7 +405,7 @@
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 46>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC3>;
status = "disabled";
};
@@ -408,7 +416,7 @@
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 68>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC4>;
status = "disabled";
};
@@ -416,14 +424,14 @@
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 36>;
+ clocks = <&tegra_car TEGRA20_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
- clocks = <&tegra_car 110>, <&clk32k_in>;
+ clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@@ -453,7 +461,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>;
+ clocks = <&tegra_car TEGRA20_CLK_USBD>;
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
status = "disabled";
@@ -464,7 +472,8 @@
reg = <0xc5000400 0x3c00>;
phy_type = "utmi";
nvidia,has-legacy-mode;
- clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clocks = <&tegra_car TEGRA20_CLK_USBD>,
+ <&tegra_car TEGRA20_CLK_PLL_U>;
clock-names = "phy", "pll_u";
};
@@ -473,7 +482,7 @@
reg = <0xc5004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
- clocks = <&tegra_car 58>;
+ clocks = <&tegra_car TEGRA20_CLK_USB2>;
nvidia,phy = <&phy2>;
status = "disabled";
};
@@ -482,7 +491,8 @@
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004400 0x3c00>;
phy_type = "ulpi";
- clocks = <&tegra_car 93>, <&tegra_car 127>;
+ clocks = <&tegra_car TEGRA20_CLK_CDEV2>,
+ <&tegra_car TEGRA20_CLK_PLL_U>;
clock-names = "phy", "pll_u";
};
@@ -491,7 +501,7 @@
reg = <0xc5008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
- clocks = <&tegra_car 59>;
+ clocks = <&tegra_car TEGRA20_CLK_USB3>;
nvidia,phy = <&phy3>;
status = "disabled";
};
@@ -500,7 +510,8 @@
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008400 0x3c00>;
phy_type = "utmi";
- clocks = <&tegra_car 22>, <&tegra_car 127>;
+ clocks = <&tegra_car TEGRA20_CLK_USBD>,
+ <&tegra_car TEGRA20_CLK_PLL_U>;
clock-names = "phy", "pll_u";
};
@@ -508,7 +519,7 @@
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 14>;
+ clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
status = "disabled";
};
@@ -516,7 +527,7 @@
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 9>;
+ clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
status = "disabled";
};
@@ -524,7 +535,7 @@
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 69>;
+ clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
status = "disabled";
};
@@ -532,7 +543,7 @@
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 15>;
+ clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
status = "disabled";
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines
2013-05-13 11:07 ` [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines Hiroshi Doyu
@ 2013-05-13 16:54 ` Stephen Warren
0 siblings, 0 replies; 11+ messages in thread
From: Stephen Warren @ 2013-05-13 16:54 UTC (permalink / raw)
To: linux-arm-kernel
On 05/13/2013 05:07 AM, Hiroshi Doyu wrote:
> Replace magic number in tegra_car:
>
> - clocks = <&tegra_car 28>;
> + clocks = <&tegra_car CLK_HOST1X>;
Patches 2, 4, 6 look basically fine. I'd also like slightly more
explanation in the commit description here. How about:
=====
Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic
numbers in the device tree. For example,
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
=====
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> #include <dt-bindings/gpio/tegra-gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clk/tegra20-car.h>
Can we keep the include files sorted?
One dependency issue with patches 2: There is a series of USB patches
(which Venu posted in the last couple of days) that fix the USB binding
to be complete. These will change the set of clocks referenced by the
EHCI and USB PHY nodes. I would like Venu's patches to be applied first,
since those DT changes will need to be merged into the USB tree so that
the USB tree can apply the subsequent driver changes. Can you hold off
on reposting your series until after I've applied Venu's changes, and
rebase this series on top of them? Hopefully it shouldn't take too long
to get Venu's series applied. Thanks.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/6] ARM: tegra30: create a DT header defining CLK IDs
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 1/6] ARM: tegra20: create a DT header defining CLK IDs Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 2/6] ARM: tegra20: convert device tree files to use CLK defines Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 4/6] ARM: tegra30: convert device tree files to use CLK defines Hiroshi Doyu
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
To replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
.../bindings/clock/nvidia,tegra30-car.txt | 209 +---------------
include/dt-bindings/clk/tegra30-car.h | 265 +++++++++++++++++++++
2 files changed, 268 insertions(+), 206 deletions(-)
create mode 100644 include/dt-bindings/clk/tegra30-car.h
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be..10e1700 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra30 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
+You can find the actual assignment in "dt-bindings/clk/tegra30-car.h"
+
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
@@ -14,211 +16,6 @@ Required properties :
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
- The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 160 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- above.
-
- 0 cpu
- 1 unassigned
- 2 unassigned
- 3 unassigned
- 4 rtc
- 5 timer
- 6 uarta
- 7 unassigned (register bit affects uartb and vfir)
- 8 gpio
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 unassigned
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 unassigned
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 i2s0
- 31 cop_cache
-
- 32 mc
- 33 ahbdma
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 statmon
- 38 pmc
- 39 unassigned (register bit affects fuse and fuse_burn)
- 40 kfuse
- 41 sbc1
- 42 nor
- 43 unassigned
- 44 sbc2
- 45 unassigned
- 46 sbc3
- 47 i2c5
- 48 dsia
- 49 unassigned (register bit affects cve and tvo)
- 50 mipi
- 51 hdmi
- 52 csi
- 53 tvdac
- 54 i2c2
- 55 uartc
- 56 unassigned
- 57 emc
- 58 usb2
- 59 usb3
- 60 mpe
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 speedo
- 65 uartd
- 66 uarte
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 pcie
- 71 owr
- 72 afi
- 73 csite
- 74 pciex
- 75 avpucq
- 76 la
- 77 unassigned
- 78 unassigned
- 79 dtv
- 80 ndspeed
- 81 i2cslow
- 82 dsib
- 83 unassigned
- 84 irama
- 85 iramb
- 86 iramc
- 87 iramd
- 88 cram2
- 89 unassigned
- 90 audio_2x a/k/a audio_2x_sync_clk
- 91 unassigned
- 92 csus
- 93 cdev2
- 94 cdev1
- 95 unassigned
-
- 96 cpu_g
- 97 cpu_lp
- 98 3d2
- 99 mselect
- 100 tsensor
- 101 i2s3
- 102 i2s4
- 103 i2c4
- 104 sbc5
- 105 sbc6
- 106 d_audio
- 107 apbif
- 108 dam0
- 109 dam1
- 110 dam2
- 111 hda2codec_2x
- 112 atomics
- 113 audio0_2x
- 114 audio1_2x
- 115 audio2_2x
- 116 audio3_2x
- 117 audio4_2x
- 118 audio5_2x
- 119 actmon
- 120 extern1
- 121 extern2
- 122 extern3
- 123 sata_oob
- 124 sata
- 125 hda
- 127 se
- 128 hda2hdmi
- 129 sata_cold
-
- 160 uartb
- 161 vfir
- 162 spdif_in
- 163 spdif_out
- 164 vi
- 165 vi_sensor
- 166 fuse
- 167 fuse_burn
- 168 cve
- 169 tvo
-
- 170 clk_32k
- 171 clk_m
- 172 clk_m_div2
- 173 clk_m_div4
- 174 pll_ref
- 175 pll_c
- 176 pll_c_out1
- 177 pll_m
- 178 pll_m_out1
- 179 pll_p
- 180 pll_p_out1
- 181 pll_p_out2
- 182 pll_p_out3
- 183 pll_p_out4
- 184 pll_a
- 185 pll_a_out0
- 186 pll_d
- 187 pll_d_out0
- 188 pll_d2
- 189 pll_d2_out0
- 190 pll_u
- 191 pll_x
- 192 pll_x_out0
- 193 pll_e
- 194 spdif_in_sync
- 195 i2s0_sync
- 196 i2s1_sync
- 197 i2s2_sync
- 198 i2s3_sync
- 199 i2s4_sync
- 200 vimclk
- 201 audio0
- 202 audio1
- 203 audio2
- 204 audio3
- 205 audio4
- 206 audio5
- 207 clk_out_1 (extern1)
- 208 clk_out_2 (extern2)
- 209 clk_out_3 (extern3)
- 210 sclk
- 211 blink
- 212 cclk_g
- 213 cclk_lp
- 214 twd
- 215 cml0
- 216 cml1
- 217 hclk
- 218 pclk
-
Example SoC include file:
/ {
@@ -229,7 +26,7 @@ Example SoC include file:
};
usb at c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA30_CLK_USB2>; /* usb2 */
};
};
diff --git a/include/dt-bindings/clk/tegra30-car.h b/include/dt-bindings/clk/tegra30-car.h
new file mode 100644
index 0000000..594f61e
--- /dev/null
+++ b/include/dt-bindings/clk/tegra30-car.h
@@ -0,0 +1,265 @@
+/*
+ * This header provides constants for binding nvidia,tegra30-car.
+ *
+ * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA30_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA30_CAR_H
+
+#define TEGRA30_CLK_CPU 0
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA30_CLK_RTC 4
+#define TEGRA30_CLK_TIMER 5
+#define TEGRA30_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA30_CLK_GPIO 8
+#define TEGRA30_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA30_CLK_I2S1 11
+#define TEGRA30_CLK_I2C1 12
+#define TEGRA30_CLK_NDFLASH 13
+#define TEGRA30_CLK_SDMMC1 14
+#define TEGRA30_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA30_CLK_PWM 17
+#define TEGRA30_CLK_I2S2 18
+#define TEGRA30_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA30_CLK_GR2D 21
+#define TEGRA30_CLK_USBD 22
+#define TEGRA30_CLK_ISP 23
+#define TEGRA30_CLK_GR3D 24
+/* 25 */
+#define TEGRA30_CLK_DISP2 26
+#define TEGRA30_CLK_DISP1 27
+#define TEGRA30_CLK_HOST1X 28
+#define TEGRA30_CLK_VCP 29
+#define TEGRA30_CLK_I2S0 30
+#define TEGRA30_CLK_COP_CACHE 31
+
+#define TEGRA30_CLK_MC 32
+#define TEGRA30_CLK_AHBDMA 33
+#define TEGRA30_CLK_APBDMA 34
+/* 35 */
+#define TEGRA30_CLK_KBC 36
+#define TEGRA30_CLK_STATMON 37
+#define TEGRA30_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA30_CLK_KFUSE 40
+#define TEGRA30_CLK_SBC1 41
+#define TEGRA30_CLK_NOR 42
+/* 43 */
+#define TEGRA30_CLK_SBC2 44
+/* 45 */
+#define TEGRA30_CLK_SBC3 46
+#define TEGRA30_CLK_I2C5 47
+#define TEGRA30_CLK_DSIA 48
+/* 49 (register bit affects cve and tvo) */
+#define TEGRA30_CLK_MIPI 50
+#define TEGRA30_CLK_HDMI 51
+#define TEGRA30_CLK_CSI 52
+#define TEGRA30_CLK_TVDAC 53
+#define TEGRA30_CLK_I2C2 54
+#define TEGRA30_CLK_UARTC 55
+/* 56 */
+#define TEGRA30_CLK_EMC 57
+#define TEGRA30_CLK_USB2 58
+#define TEGRA30_CLK_USB3 59
+#define TEGRA30_CLK_MPE 60
+#define TEGRA30_CLK_VDE 61
+#define TEGRA30_CLK_BSEA 62
+#define TEGRA30_CLK_BSEV 63
+
+#define TEGRA30_CLK_SPEEDO 64
+#define TEGRA30_CLK_UARTD 65
+#define TEGRA30_CLK_UARTE 66
+#define TEGRA30_CLK_I2C3 67
+#define TEGRA30_CLK_SBC4 68
+#define TEGRA30_CLK_SDMMC3 69
+#define TEGRA30_CLK_PCIE 70
+#define TEGRA30_CLK_OWR 71
+#define TEGRA30_CLK_AFI 72
+#define TEGRA30_CLK_CSITE 73
+#define TEGRA30_CLK_PCIEX 74
+#define TEGRA30_CLK_AVPUCQ 75
+#define TEGRA30_CLK_LA 76
+/* 77 */
+/* 78 */
+#define TEGRA30_CLK_DTV 79
+#define TEGRA30_CLK_NDSPEED 80
+#define TEGRA30_CLK_I2CSLOW 81
+#define TEGRA30_CLK_DSIB 82
+/* 83 */
+#define TEGRA30_CLK_IRAMA 84
+#define TEGRA30_CLK_IRAMB 85
+#define TEGRA30_CLK_IRAMC 86
+#define TEGRA30_CLK_IRAMD 87
+#define TEGRA30_CLK_CRAM2 88
+/* 89 */
+#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
+/* 91 */
+#define TEGRA30_CLK_CSUS 92
+#define TEGRA30_CLK_CDEV2 93
+#define TEGRA30_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA30_CLK_CPU_G 96
+#define TEGRA30_CLK_CPU_LP 97
+#define TEGRA30_CLK_GR3D2 98
+#define TEGRA30_CLK_MSELECT 99
+#define TEGRA30_CLK_TSENSOR 100
+#define TEGRA30_CLK_I2S3 101
+#define TEGRA30_CLK_I2S4 102
+#define TEGRA30_CLK_I2C4 103
+#define TEGRA30_CLK_SBC5 104
+#define TEGRA30_CLK_SBC6 105
+#define TEGRA30_CLK_D_AUDIO 106
+#define TEGRA30_CLK_APBIF 107
+#define TEGRA30_CLK_DAM0 108
+#define TEGRA30_CLK_DAM1 109
+#define TEGRA30_CLK_DAM2 110
+#define TEGRA30_CLK_HDA2CODEC_2X 111
+#define TEGRA30_CLK_ATOMICS 112
+#define TEGRA30_CLK_AUDIO0_2X 113
+#define TEGRA30_CLK_AUDIO1_2X 114
+#define TEGRA30_CLK_AUDIO2_2X 115
+#define TEGRA30_CLK_AUDIO3_2X 116
+#define TEGRA30_CLK_AUDIO4_2X 117
+#define TEGRA30_CLK_SPDIF_2X 118
+#define TEGRA30_CLK_ACTMON 119
+#define TEGRA30_CLK_EXTERN1 120
+#define TEGRA30_CLK_EXTERN2 121
+#define TEGRA30_CLK_EXTERN3 122
+#define TEGRA30_CLK_SATA_OOB 123
+#define TEGRA30_CLK_SATA 124
+#define TEGRA30_CLK_HDA 125
+/* 126 */
+#define TEGRA30_CLK_SE 127
+
+#define TEGRA30_CLK_HDA2HDMI 128
+#define TEGRA30_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 */
+/* 144 */
+/* 145 */
+/* 146 */
+/* 147 */
+/* 148 */
+/* 149 */
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 */
+/* 156 */
+/* 157 */
+/* 158 */
+/* 159 */
+
+#define TEGRA30_CLK_UARTB 160
+#define TEGRA30_CLK_VFIR 161
+#define TEGRA30_CLK_SPDIF_IN 162
+#define TEGRA30_CLK_SPDIF_OUT 163
+#define TEGRA30_CLK_VI 164
+#define TEGRA30_CLK_VI_SENSOR 165
+#define TEGRA30_CLK_FUSE 166
+#define TEGRA30_CLK_FUSE_BURN 167
+#define TEGRA30_CLK_CVE 168
+#define TEGRA30_CLK_TVO 169
+#define TEGRA30_CLK_CLK_32K 170
+#define TEGRA30_CLK_CLK_M 171
+#define TEGRA30_CLK_CLK_M_DIV2 172
+#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_PLL_REF 174
+#define TEGRA30_CLK_PLL_C 175
+#define TEGRA30_CLK_PLL_C_OUT1 176
+#define TEGRA30_CLK_PLL_M 177
+#define TEGRA30_CLK_PLL_M_OUT1 178
+#define TEGRA30_CLK_PLL_P 179
+#define TEGRA30_CLK_PLL_P_OUT1 180
+#define TEGRA30_CLK_PLL_P_OUT2 181
+#define TEGRA30_CLK_PLL_P_OUT3 182
+#define TEGRA30_CLK_PLL_P_OUT4 183
+#define TEGRA30_CLK_PLL_A 184
+#define TEGRA30_CLK_PLL_A_OUT0 185
+#define TEGRA30_CLK_PLL_D 186
+#define TEGRA30_CLK_PLL_D_OUT0 187
+#define TEGRA30_CLK_PLL_D2 188
+#define TEGRA30_CLK_PLL_D2_OUT0 189
+#define TEGRA30_CLK_PLL_U 190
+#define TEGRA30_CLK_PLL_X 191
+
+#define TEGRA30_CLK_PLL_X_OUT0 192
+#define TEGRA30_CLK_PLL_E 193
+#define TEGRA30_CLK_SPDIF_IN_SYNC 194
+#define TEGRA30_CLK_I2S0_SYNC 195
+#define TEGRA30_CLK_I2S1_SYNC 196
+#define TEGRA30_CLK_I2S2_SYNC 197
+#define TEGRA30_CLK_I2S3_SYNC 198
+#define TEGRA30_CLK_I2S4_SYNC 199
+#define TEGRA30_CLK_VIMCLK_SYNC 200
+#define TEGRA30_CLK_AUDIO0 201
+#define TEGRA30_CLK_AUDIO1 202
+#define TEGRA30_CLK_AUDIO2 203
+#define TEGRA30_CLK_AUDIO3 204
+#define TEGRA30_CLK_AUDIO4 205
+#define TEGRA30_CLK_SPDIF 206
+#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
+#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
+#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+#define TEGRA30_CLK_SCLK 210
+#define TEGRA30_CLK_BLINK 211
+#define TEGRA30_CLK_CCLK_G 212
+#define TEGRA30_CLK_CCLK_LP 213
+#define TEGRA30_CLK_TWD 214
+#define TEGRA30_CLK_CML0 215
+#define TEGRA30_CLK_CML1 216
+#define TEGRA30_CLK_HCLK 217
+#define TEGRA30_CLK_PCLK 218
+/* 219 */
+/* 220 */
+/* 221 */
+/* 222 */
+/* 223 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA30_CLK_CLK_OUT_1_MUX 300
+#define TEGRA30_CLK_CLK_MAX 301
+
+#endif /* _DT_BINDINGS_CLK_TEGRA30_CAR_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/6] ARM: tegra30: convert device tree files to use CLK defines
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
` (2 preceding siblings ...)
2013-05-13 11:07 ` [PATCH 3/6] ARM: tegra30: create a DT header defining CLK IDs Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 5/6] ARM: tegra114: create a DT header defining CLK IDs Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 6/6] ARM: tegra114: convert device tree files to use CLK defines Hiroshi Doyu
5 siblings, 0 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/boot/dts/tegra30-beaver.dts | 4 +-
arch/arm/boot/dts/tegra30-cardhu.dtsi | 4 +-
arch/arm/boot/dts/tegra30.dtsi | 110 +++++++++++++++++++---------------
3 files changed, 69 insertions(+), 49 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 9f4b684..5f6dcff 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -413,7 +413,9 @@
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 85f26ba..fc3ffd8 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -534,7 +534,9 @@
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 329465a..fe1904e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra30-car.h>
#include "skeleton.dtsi"
@@ -20,7 +21,7 @@
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
#address-cells = <1>;
#size-cells = <1>;
@@ -31,35 +32,35 @@
compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 60>;
+ clocks = <&tegra_car TEGRA30_CLK_MPE>;
};
vi {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 164>;
+ clocks = <&tegra_car TEGRA30_CLK_VI>;
};
epp {
compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 19>;
+ clocks = <&tegra_car TEGRA30_CLK_EPP>;
};
isp {
compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 23>;
+ clocks = <&tegra_car TEGRA30_CLK_ISP>;
};
gr2d {
compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 21>;
+ clocks = <&tegra_car TEGRA30_CLK_GR2D>;
};
gr3d {
@@ -73,7 +74,8 @@
compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 27>, <&tegra_car 179>;
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_P>;
clock-names = "disp1", "parent";
rgb {
@@ -85,7 +87,8 @@
compatible = "nvidia,tegra30-dc";
reg = <0x54240000 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 26>, <&tegra_car 179>;
+ clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+ <&tegra_car TEGRA30_CLK_PLL_P>;
clock-names = "disp2", "parent";
rgb {
@@ -97,7 +100,8 @@
compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 51>, <&tegra_car 189>;
+ clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+ <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
clock-names = "hdmi", "parent";
status = "disabled";
};
@@ -106,14 +110,14 @@
compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 169>;
+ clocks = <&tegra_car TEGRA30_CLK_TVO>;
status = "disabled";
};
dsi {
compatible = "nvidia,tegra30-dsi";
reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car 48>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIA>;
status = "disabled";
};
};
@@ -123,7 +127,7 @@
reg = <0x50040600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&tegra_car 214>;
+ clocks = <&tegra_car TEGRA30_CLK_TWD>;
};
intc: interrupt-controller {
@@ -152,7 +156,7 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 5>;
+ clocks = <&tegra_car TEGRA30_CLK_TIMER>;
};
tegra_car: clock {
@@ -196,7 +200,7 @@
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 34>;
+ clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
};
ahb: ahb {
@@ -241,7 +245,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
- clocks = <&tegra_car 6>;
+ clocks = <&tegra_car TEGRA30_CLK_UARTA>;
status = "disabled";
};
@@ -251,7 +255,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
- clocks = <&tegra_car 160>;
+ clocks = <&tegra_car TEGRA30_CLK_UARTB>;
status = "disabled";
};
@@ -261,7 +265,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
- clocks = <&tegra_car 55>;
+ clocks = <&tegra_car TEGRA30_CLK_UARTC>;
status = "disabled";
};
@@ -271,7 +275,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
- clocks = <&tegra_car 65>;
+ clocks = <&tegra_car TEGRA30_CLK_UARTD>;
status = "disabled";
};
@@ -281,7 +285,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
- clocks = <&tegra_car 66>;
+ clocks = <&tegra_car TEGRA30_CLK_UARTE>;
status = "disabled";
};
@@ -289,7 +293,7 @@
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
- clocks = <&tegra_car 17>;
+ clocks = <&tegra_car TEGRA30_CLK_PWM>;
status = "disabled";
};
@@ -297,7 +301,7 @@
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 4>;
+ clocks = <&tegra_car TEGRA30_CLK_RTC>;
};
i2c at 7000c000 {
@@ -306,7 +310,8 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 12>, <&tegra_car 182>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -317,7 +322,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 54>, <&tegra_car 182>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -328,7 +334,8 @@
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 67>, <&tegra_car 182>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -339,7 +346,8 @@
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 103>, <&tegra_car 182>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -350,7 +358,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 47>, <&tegra_car 182>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@@ -362,7 +371,7 @@
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 41>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC1>;
status = "disabled";
};
@@ -373,7 +382,7 @@
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 44>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC2>;
status = "disabled";
};
@@ -384,7 +393,7 @@
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 46>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC3>;
status = "disabled";
};
@@ -395,7 +404,7 @@
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 68>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC4>;
status = "disabled";
};
@@ -406,7 +415,7 @@
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 104>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC5>;
status = "disabled";
};
@@ -417,7 +426,7 @@
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 105>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC6>;
status = "disabled";
};
@@ -425,14 +434,14 @@
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 36>;
+ clocks = <&tegra_car TEGRA30_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
- clocks = <&tegra_car 218>, <&clk32k_in>;
+ clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@@ -461,10 +470,17 @@
0x70080200 0x100>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
- <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
- <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
- <&tegra_car 110>, <&tegra_car 162>;
+ clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+ <&tegra_car TEGRA30_CLK_APBIF>,
+ <&tegra_car TEGRA30_CLK_I2S0>,
+ <&tegra_car TEGRA30_CLK_I2S1>,
+ <&tegra_car TEGRA30_CLK_I2S2>,
+ <&tegra_car TEGRA30_CLK_I2S3>,
+ <&tegra_car TEGRA30_CLK_I2S4>,
+ <&tegra_car TEGRA30_CLK_DAM0>,
+ <&tegra_car TEGRA30_CLK_DAM1>,
+ <&tegra_car TEGRA30_CLK_DAM2>,
+ <&tegra_car TEGRA30_CLK_SPDIF_IN>;
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif_in";
@@ -476,7 +492,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080300 0x100>;
nvidia,ahub-cif-ids = <4 4>;
- clocks = <&tegra_car 30>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S0>;
status = "disabled";
};
@@ -484,7 +500,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080400 0x100>;
nvidia,ahub-cif-ids = <5 5>;
- clocks = <&tegra_car 11>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S1>;
status = "disabled";
};
@@ -492,7 +508,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080500 0x100>;
nvidia,ahub-cif-ids = <6 6>;
- clocks = <&tegra_car 18>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S2>;
status = "disabled";
};
@@ -500,7 +516,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080600 0x100>;
nvidia,ahub-cif-ids = <7 7>;
- clocks = <&tegra_car 101>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S3>;
status = "disabled";
};
@@ -508,7 +524,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080700 0x100>;
nvidia,ahub-cif-ids = <8 8>;
- clocks = <&tegra_car 102>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S4>;
status = "disabled";
};
};
@@ -517,7 +533,7 @@
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 14>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
status = "disabled";
};
@@ -525,7 +541,7 @@
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 9>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
status = "disabled";
};
@@ -533,7 +549,7 @@
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 69>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
status = "disabled";
};
@@ -541,7 +557,7 @@
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 15>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
status = "disabled";
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/6] ARM: tegra114: create a DT header defining CLK IDs
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
` (3 preceding siblings ...)
2013-05-13 11:07 ` [PATCH 4/6] ARM: tegra30: convert device tree files to use CLK defines Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
2013-05-13 11:07 ` [PATCH 6/6] ARM: tegra114: convert device tree files to use CLK defines Hiroshi Doyu
5 siblings, 0 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
.../bindings/clock/nvidia,tegra114-car.txt | 250 +--------------
include/dt-bindings/clk/tegra114-car.h | 342 +++++++++++++++++++++
2 files changed, 345 insertions(+), 247 deletions(-)
create mode 100644 include/dt-bindings/clk/tegra114-car.h
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index d6cb083..5177196 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -3,6 +3,8 @@ NVIDIA Tegra114 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
+You can find the actual assignment in "dt-bindings/clk/tegra114-car.h"
+
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
@@ -14,252 +16,6 @@ Required properties :
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
- The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 160 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- above.
-
- 0 unassigned
- 1 unassigned
- 2 unassigned
- 3 unassigned
- 4 rtc
- 5 timer
- 6 uarta
- 7 unassigned (register bit affects uartb and vfir)
- 8 unassigned
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 unassigned
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 unassigned
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 i2s0
- 31 unassigned
-
- 32 unassigned
- 33 unassigned
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 unassigned
- 38 unassigned
- 39 unassigned (register bit affects fuse and fuse_burn)
- 40 kfuse
- 41 sbc1
- 42 nor
- 43 unassigned
- 44 sbc2
- 45 unassigned
- 46 sbc3
- 47 i2c5
- 48 dsia
- 49 unassigned
- 50 mipi
- 51 hdmi
- 52 csi
- 53 unassigned
- 54 i2c2
- 55 uartc
- 56 mipi-cal
- 57 emc
- 58 usb2
- 59 usb3
- 60 msenc
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 unassigned
- 65 uartd
- 66 unassigned
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 unassigned
- 71 owr
- 72 afi
- 73 csite
- 74 unassigned
- 75 unassigned
- 76 la
- 77 trace
- 78 soc_therm
- 79 dtv
- 80 ndspeed
- 81 i2cslow
- 82 dsib
- 83 tsec
- 84 unassigned
- 85 unassigned
- 86 unassigned
- 87 unassigned
- 88 unassigned
- 89 xusb_host
- 90 unassigned
- 91 msenc
- 92 csus
- 93 unassigned
- 94 unassigned
- 95 unassigned (bit affects xusb_dev and xusb_dev_src)
-
- 96 unassigned
- 97 unassigned
- 98 unassigned
- 99 mselect
- 100 tsensor
- 101 i2s3
- 102 i2s4
- 103 i2c4
- 104 sbc5
- 105 sbc6
- 106 d_audio
- 107 apbif
- 108 dam0
- 109 dam1
- 110 dam2
- 111 hda2codec_2x
- 112 unassigned
- 113 audio0_2x
- 114 audio1_2x
- 115 audio2_2x
- 116 audio3_2x
- 117 audio4_2x
- 118 spdif_2x
- 119 actmon
- 120 extern1
- 121 extern2
- 122 extern3
- 123 unassigned
- 124 unassigned
- 125 hda
- 126 unassigned
- 127 se
-
- 128 hda2hdmi
- 129 unassigned
- 130 unassigned
- 131 unassigned
- 132 unassigned
- 133 unassigned
- 134 unassigned
- 135 unassigned
- 136 unassigned
- 137 unassigned
- 138 unassigned
- 139 unassigned
- 140 unassigned
- 141 unassigned
- 142 unassigned
- 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
- xusb_host_src and xusb_ss_src)
- 144 cilab
- 145 cilcd
- 146 cile
- 147 dsialp
- 148 dsiblp
- 149 unassigned
- 150 dds
- 151 unassigned
- 152 dp2
- 153 amx
- 154 adx
- 155 unassigned (bit affects dfll_ref and dfll_soc)
- 156 xusb_ss
-
- 192 uartb
- 193 vfir
- 194 spdif_in
- 195 spdif_out
- 196 vi
- 197 vi_sensor
- 198 fuse
- 199 fuse_burn
- 200 clk_32k
- 201 clk_m
- 202 clk_m_div2
- 203 clk_m_div4
- 204 pll_ref
- 205 pll_c
- 206 pll_c_out1
- 207 pll_c2
- 208 pll_c3
- 209 pll_m
- 210 pll_m_out1
- 211 pll_p
- 212 pll_p_out1
- 213 pll_p_out2
- 214 pll_p_out3
- 215 pll_p_out4
- 216 pll_a
- 217 pll_a_out0
- 218 pll_d
- 219 pll_d_out0
- 220 pll_d2
- 221 pll_d2_out0
- 222 pll_u
- 223 pll_u_480M
- 224 pll_u_60M
- 225 pll_u_48M
- 226 pll_u_12M
- 227 pll_x
- 228 pll_x_out0
- 229 pll_re_vco
- 230 pll_re_out
- 231 pll_e_out0
- 232 spdif_in_sync
- 233 i2s0_sync
- 234 i2s1_sync
- 235 i2s2_sync
- 236 i2s3_sync
- 237 i2s4_sync
- 238 vimclk_sync
- 239 audio0
- 240 audio1
- 241 audio2
- 242 audio3
- 243 audio4
- 244 spdif
- 245 clk_out_1
- 246 clk_out_2
- 247 clk_out_3
- 248 blink
- 252 xusb_host_src
- 253 xusb_falcon_src
- 254 xusb_fs_src
- 255 xusb_ss_src
- 256 xusb_dev_src
- 257 xusb_dev
- 258 xusb_hs_src
- 259 sclk
- 260 hclk
- 261 pclk
- 262 cclk_g
- 263 cclk_lp
- 264 dfll_ref
- 265 dfll_soc
-
Example SoC include file:
/ {
@@ -270,7 +26,7 @@ Example SoC include file:
};
usb at c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA114_CLK_USB2>; /* usb2 */
};
};
diff --git a/include/dt-bindings/clk/tegra114-car.h b/include/dt-bindings/clk/tegra114-car.h
new file mode 100644
index 0000000..83ea208
--- /dev/null
+++ b/include/dt-bindings/clk/tegra114-car.h
@@ -0,0 +1,342 @@
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLK_TEGRA114_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR_2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR_3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+
+/* 32 */
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/* xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+/* 264 */
+/* 265 */
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_CLK_MAX 311
+
+#endif /* _DT_BINDINGS_CLK_TEGRA114_CAR_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6/6] ARM: tegra114: convert device tree files to use CLK defines
2013-05-13 11:06 [PATCH 0/6] CLK: tegra: convert device tree files to use CLK defines Hiroshi Doyu
` (4 preceding siblings ...)
2013-05-13 11:07 ` [PATCH 5/6] ARM: tegra114: create a DT header defining CLK IDs Hiroshi Doyu
@ 2013-05-13 11:07 ` Hiroshi Doyu
5 siblings, 0 replies; 11+ messages in thread
From: Hiroshi Doyu @ 2013-05-13 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Replace magic number in tegra_car:
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 4 +-
arch/arm/boot/dts/tegra114.dtsi | 79 +++++++++++++++++++---------------
2 files changed, 47 insertions(+), 36 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 59695f01..cfcb3e2 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -957,7 +957,9 @@
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
- clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>;
+ clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+ <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA114_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 15d1b58..1d3127e 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clk/tegra114-car.h>
#include "skeleton.dtsi"
@@ -35,7 +36,7 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 5>;
+ clocks = <&tegra_car TEGRA114_CLK_TIMER>;
};
tegra_car: clock {
@@ -79,7 +80,7 @@
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 34>;
+ clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
};
ahb: ahb {
@@ -125,7 +126,7 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled";
- clocks = <&tegra_car 6>;
+ clocks = <&tegra_car TEGRA114_CLK_UARTA>;
};
uartb: serial at 70006040 {
@@ -135,7 +136,7 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled";
- clocks = <&tegra_car 192>;
+ clocks = <&tegra_car TEGRA114_CLK_UARTB>;
};
uartc: serial at 70006200 {
@@ -145,7 +146,7 @@
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled";
- clocks = <&tegra_car 55>;
+ clocks = <&tegra_car TEGRA114_CLK_UARTC>;
};
uartd: serial at 70006300 {
@@ -155,14 +156,14 @@
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled";
- clocks = <&tegra_car 65>;
+ clocks = <&tegra_car TEGRA114_CLK_UARTD>;
};
pwm: pwm {
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
- clocks = <&tegra_car 17>;
+ clocks = <&tegra_car TEGRA114_CLK_PWM>;
status = "disabled";
};
@@ -172,7 +173,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 12>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C1>;
clock-names = "div-clk";
status = "disabled";
};
@@ -183,7 +184,7 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 54>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C2>;
clock-names = "div-clk";
status = "disabled";
};
@@ -194,7 +195,7 @@
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 67>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C3>;
clock-names = "div-clk";
status = "disabled";
};
@@ -205,7 +206,7 @@
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 103>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C4>;
clock-names = "div-clk";
status = "disabled";
};
@@ -216,7 +217,7 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 47>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C5>;
clock-names = "div-clk";
status = "disabled";
};
@@ -228,7 +229,7 @@
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 41>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC1>;
clock-names = "spi";
status = "disabled";
};
@@ -240,7 +241,7 @@
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 44>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC2>;
clock-names = "spi";
status = "disabled";
};
@@ -252,7 +253,7 @@
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 46>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC3>;
clock-names = "spi";
status = "disabled";
};
@@ -264,7 +265,7 @@
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 68>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC4>;
clock-names = "spi";
status = "disabled";
};
@@ -276,7 +277,7 @@
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 104>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC5>;
clock-names = "spi";
status = "disabled";
};
@@ -288,7 +289,7 @@
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 105>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC6>;
clock-names = "spi";
status = "disabled";
};
@@ -297,21 +298,21 @@
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 4>;
+ clocks = <&tegra_car TEGRA114_CLK_RTC>;
};
kbc {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 36>;
+ clocks = <&tegra_car TEGRA114_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
- clocks = <&tegra_car 261>, <&clk32k_in>;
+ clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@@ -336,11 +337,19 @@
<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
<&apbdma 29>;
- clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
- <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
- <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
- <&tegra_car 110>, <&tegra_car 194>, <&tegra_car 153>,
- <&tegra_car 154>;
+ clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+ <&tegra_car TEGRA114_CLK_APBIF>,
+ <&tegra_car TEGRA114_CLK_I2S0>,
+ <&tegra_car TEGRA114_CLK_I2S1>,
+ <&tegra_car TEGRA114_CLK_I2S2>,
+ <&tegra_car TEGRA114_CLK_I2S3>,
+ <&tegra_car TEGRA114_CLK_I2S4>,
+ <&tegra_car TEGRA114_CLK_DAM0>,
+ <&tegra_car TEGRA114_CLK_DAM1>,
+ <&tegra_car TEGRA114_CLK_DAM2>,
+ <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+ <&tegra_car TEGRA114_CLK_AMX>,
+ <&tegra_car TEGRA114_CLK_ADX>;
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif_in", "amx", "adx";
@@ -352,7 +361,7 @@
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080300 0x100>;
nvidia,ahub-cif-ids = <4 4>;
- clocks = <&tegra_car 30>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S0>;
status = "disabled";
};
@@ -360,7 +369,7 @@
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080400 0x100>;
nvidia,ahub-cif-ids = <5 5>;
- clocks = <&tegra_car 11>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S1>;
status = "disabled";
};
@@ -368,7 +377,7 @@
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080500 0x100>;
nvidia,ahub-cif-ids = <6 6>;
- clocks = <&tegra_car 18>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S2>;
status = "disabled";
};
@@ -376,7 +385,7 @@
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080600 0x100>;
nvidia,ahub-cif-ids = <7 7>;
- clocks = <&tegra_car 101>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S3>;
status = "disabled";
};
@@ -384,7 +393,7 @@
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080700 0x100>;
nvidia,ahub-cif-ids = <8 8>;
- clocks = <&tegra_car 102>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S4>;
status = "disabled";
};
};
@@ -393,7 +402,7 @@
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 14>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
status = "disable";
};
@@ -401,7 +410,7 @@
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 9>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
status = "disable";
};
@@ -409,7 +418,7 @@
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 69>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
status = "disable";
};
@@ -417,7 +426,7 @@
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car 15>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
status = "disable";
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 11+ messages in thread