ARM Cortex-A7 support in Linux

ARM Cortex-A7 support in Linux

[Sharma Bhupesh-B45370]

Hi Catalin, list

I am trying to locate support for Cortex-A7 soc (in Linux) and it's primary features like:
- SMMU 400 (Virtualization)
- CCI 400 
- LPAE
- GIC 400

We wish to use this core in one of our SoCs and will like to reuse most of the code.
I can see some support added for:
- Cortex-A7 dts by Pawel for Versatile board
	http://linux-arm.org/git?p=arm-dts.git;a=commitdiff;h=81195261a984e8c734f319eda80f86ba82b37d27

- LPAE support by Catalin
	http://lxr.linux.no/linux+v3.9.2/arch/arm/mm/Kconfig#L589

- CCI 400 RFC patches from Lorenzo
	https://patchwork.kernel.org/patch/2508121/

- Basic dts support for GIC virtualization support is already present here:
	http://lxr.linux.no/linux+v3.9.2/Documentation/devicetree/bindings/arm/gic.txt#L64

But I am not sure about the following:
- Does the current GIC driver support GIC-400 features as well?

- I don't see many of these features supported in u-boot. Any idea if any work is going on for the same? 

Thanks for your help.
Regards,
Bhupesh

ARM Cortex-A7 support in Linux

[Marc Zyngier]

On Fri, 17 May 2013 09:56:22 +0000, Sharma Bhupesh-B45370
<B45370@freescale.com> wrote:

> But I am not sure about the following:
> - Does the current GIC driver support GIC-400 features as well?

It depends which feature you're after. Linux supports the GIC
virtualization extensions with KVM, for example. But we don't make any use
of other things like priorities, split deactivation/priority drop...

         M.
-- 
Fast, cheap, reliable. Pick two.

ARM Cortex-A7 support in Linux

[Russell King - ARM Linux]

On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> It depends which feature you're after. Linux supports the GIC
> virtualization extensions with KVM, for example. But we don't make any use
> of other things like priorities, split deactivation/priority drop...

Not that we could make use of priorities anymore as all interrupt handlers
are now run with IRQs disabled; an IRQ handler can't be interrupted by a
higher priority IRQ coming in.

Part of the solution to that is to go back to the original philosophy of
IRQ handling in Linux - do the least possible amount of work in the IRQ
and move the heavier stuff off into soft-IRQ context.  Unfortunately,
many drivers are no longer written like that, and just do a great amount
of time consuming work in their IRQ handler.

ARM Cortex-A7 support in Linux

[Will Deacon]

On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> > It depends which feature you're after. Linux supports the GIC
> > virtualization extensions with KVM, for example. But we don't make any use
> > of other things like priorities, split deactivation/priority drop...
> 
> Not that we could make use of priorities anymore as all interrupt handlers
> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
> higher priority IRQ coming in.
> 
> Part of the solution to that is to go back to the original philosophy of
> IRQ handling in Linux - do the least possible amount of work in the IRQ
> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
> many drivers are no longer written like that, and just do a great amount
> of time consuming work in their IRQ handler.

We could also consider using interrupt priorities to have a fake NMI (I
think PPC does this for some cores), which is useful for profiling and
watchdogs, especially now that FIQ is often stolen by the secure world.

I remember dismissing this in the past because I thought it would increase
our GIC distributor accesses, but I don't remember why.

Will

ARM Cortex-A7 support in Linux

[Marc Zyngier]

On 17/05/13 12:36, Will Deacon wrote:
> On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
>> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
>>> It depends which feature you're after. Linux supports the GIC
>>> virtualization extensions with KVM, for example. But we don't make any use
>>> of other things like priorities, split deactivation/priority drop...
>>
>> Not that we could make use of priorities anymore as all interrupt handlers
>> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
>> higher priority IRQ coming in.
>>
>> Part of the solution to that is to go back to the original philosophy of
>> IRQ handling in Linux - do the least possible amount of work in the IRQ
>> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
>> many drivers are no longer written like that, and just do a great amount
>> of time consuming work in their IRQ handler.
> 
> We could also consider using interrupt priorities to have a fake NMI (I
> think PPC does this for some cores), which is useful for profiling and
> watchdogs, especially now that FIQ is often stolen by the secure world.
> 
> I remember dismissing this in the past because I thought it would increase
> our GIC distributor accesses, but I don't remember why.

I think it would rather require to write to the interrupt priority mask
register (GIC_PMR) in the CPU interface. The cost is probably the same,
actually (probably quite high, given how often we enable/disable
interrupts).

	M.
-- 
Jazz is not dead. It just smells funny...

ARM Cortex-A7 support in Linux

[Will Deacon]

On Fri, May 17, 2013 at 12:42:11PM +0100, Marc Zyngier wrote:
> On 17/05/13 12:36, Will Deacon wrote:
> > On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
> >> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
> >>> It depends which feature you're after. Linux supports the GIC
> >>> virtualization extensions with KVM, for example. But we don't make any use
> >>> of other things like priorities, split deactivation/priority drop...
> >>
> >> Not that we could make use of priorities anymore as all interrupt handlers
> >> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
> >> higher priority IRQ coming in.
> >>
> >> Part of the solution to that is to go back to the original philosophy of
> >> IRQ handling in Linux - do the least possible amount of work in the IRQ
> >> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
> >> many drivers are no longer written like that, and just do a great amount
> >> of time consuming work in their IRQ handler.
> > 
> > We could also consider using interrupt priorities to have a fake NMI (I
> > think PPC does this for some cores), which is useful for profiling and
> > watchdogs, especially now that FIQ is often stolen by the secure world.
> > 
> > I remember dismissing this in the past because I thought it would increase
> > our GIC distributor accesses, but I don't remember why.
> 
> I think it would rather require to write to the interrupt priority mask
> register (GIC_PMR) in the CPU interface. The cost is probably the same,
> actually (probably quite high, given how often we enable/disable
> interrupts).

In terms of the hardware, maybe, but the distributor requires a lock and
will also trap to the hypervisor if accessed from a guest.

However, since the GIC_PMR is in the CPU interface then that should be fine.

Will

ARM Cortex-A7 support in Linux

[Marc Zyngier]

On 17/05/13 12:48, Will Deacon wrote:
> On Fri, May 17, 2013 at 12:42:11PM +0100, Marc Zyngier wrote:
>> On 17/05/13 12:36, Will Deacon wrote:
>>> On Fri, May 17, 2013 at 11:55:00AM +0100, Russell King - ARM Linux wrote:
>>>> On Fri, May 17, 2013 at 12:47:45PM +0200, Marc Zyngier wrote:
>>>>> It depends which feature you're after. Linux supports the GIC
>>>>> virtualization extensions with KVM, for example. But we don't make any use
>>>>> of other things like priorities, split deactivation/priority drop...
>>>>
>>>> Not that we could make use of priorities anymore as all interrupt handlers
>>>> are now run with IRQs disabled; an IRQ handler can't be interrupted by a
>>>> higher priority IRQ coming in.
>>>>
>>>> Part of the solution to that is to go back to the original philosophy of
>>>> IRQ handling in Linux - do the least possible amount of work in the IRQ
>>>> and move the heavier stuff off into soft-IRQ context.  Unfortunately,
>>>> many drivers are no longer written like that, and just do a great amount
>>>> of time consuming work in their IRQ handler.
>>>
>>> We could also consider using interrupt priorities to have a fake NMI (I
>>> think PPC does this for some cores), which is useful for profiling and
>>> watchdogs, especially now that FIQ is often stolen by the secure world.
>>>
>>> I remember dismissing this in the past because I thought it would increase
>>> our GIC distributor accesses, but I don't remember why.
>>
>> I think it would rather require to write to the interrupt priority mask
>> register (GIC_PMR) in the CPU interface. The cost is probably the same,
>> actually (probably quite high, given how often we enable/disable
>> interrupts).
> 
> In terms of the hardware, maybe, but the distributor requires a lock and
> will also trap to the hypervisor if accessed from a guest.
> 
> However, since the GIC_PMR is in the CPU interface then that should be fine.

Absolutely. I was just thinking of the respective costs of a device
write vs setting the I bit in CPSR.

	M.
-- 
Jazz is not dead. It just smells funny...