[PATCH 0/4] ARM: rockchip: add smp functionality

[PATCH 0/4] ARM: rockchip: add smp functionality

[Heiko Stübner]

This series enables the use of the additional cores on Rockchip
Cortex-A9 SoCs.

To achieve this, add the scu, the needed sram and power-management-unit.

This is again new teritory for me, so I might've messed up something,
but overall I'm happy to have gained a bit of smp understanding :-)

This of course goes on top of the basic support series.

Heiko Stuebner (4):
  arm: rockchip: add snoop-control-unit
  arm: rockchip: add sram dt nodes and documentation
  arm: rockchip: add power-management-unit dt node
  arm: rockchip: add smp bringup code

 .../devicetree/bindings/arm/rockchip/pmu.txt       |   16 +++
 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29 ++++
 arch/arm/boot/dts/rk3066a.dtsi                     |   24 ++++
 arch/arm/mach-rockchip/Kconfig                     |    1 +
 arch/arm/mach-rockchip/Makefile                    |    1 +
 arch/arm/mach-rockchip/core.h                      |   22 +++
 arch/arm/mach-rockchip/headsmp.S                   |   32 +++++
 arch/arm/mach-rockchip/platsmp.c                   |  145 ++++++++++++++++++++
 arch/arm/mach-rockchip/rockchip.c                  |    2 +
 9 files changed, 272 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
 create mode 100644 arch/arm/mach-rockchip/core.h
 create mode 100644 arch/arm/mach-rockchip/headsmp.S
 create mode 100644 arch/arm/mach-rockchip/platsmp.c

-- 
1.7.10.4

[PATCH 1/4] ARM: rockchip: add snoop-control-unit

[Heiko Stübner]

This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a.dtsi |    5 +++++
 arch/arm/mach-rockchip/Kconfig |    1 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 56bfac9..26c4311 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -48,6 +48,11 @@
 		compatible = "simple-bus";
 		ranges;
 
+		scu at 1013c000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0x1013c000 0x100>;
+		};
+
 		gic: interrupt-controller at 1013d000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 25ee12b..0f5484c 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -5,6 +5,7 @@ config ARCH_ROCKCHIP
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_GIC
 	select CACHE_L2X0
+	select HAVE_ARM_SCU
 	select HAVE_ARM_TWD if LOCAL_TIMERS
 	select HAVE_SMP
 	select LOCAL_TIMERS if SMP
-- 
1.7.10.4

[PATCH 2/4] ARM: rockchip: add sram dt nodes and documentation

[Heiko Stübner]

The Rockchip SoCs need a special part of their sram for bringup
of additional cores. Therefore the mapped area should be split
into a special area for the smp code and a generic area that gets
handled by mmio-sram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29 ++++++++++++++++++++
 arch/arm/boot/dts/rk3066a.dtsi                     |   14 ++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt

diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
new file mode 100644
index 0000000..9c81fac
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
@@ -0,0 +1,29 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+While the suspend also needs to have code in the sram that can be realized
+with the generic mmio-sram driver and only the smp specific part needs to
+be mapped specially in the smp code.
+
+Therefore split the sram mapping in a smp-specific part that gets used
+by the smp code exclusively and a bigger generic part for mmio-sram
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-smp-sram";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	sram at 10080000 {
+		compatible = "rockchip,rk3066-smp-sram";
+		reg = <0x10080000 0x100>;
+	};
+
+	sram: sram at 10080100 {
+		compatible = "mmio-sram";
+		reg = <0x10080100 0x9900>;
+	};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 26c4311..44eabd2 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -53,6 +53,20 @@
 			reg = <0x1013c000 0x100>;
 		};
 
+		/*
+		 * the first part of the sram is needed for the smp
+		 * trampoline code during cpu bringup
+		 */
+		sram at 10080000 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x10080000 0x100>;
+		};
+
+		sram: sram at 10080100 {
+			compatible = "mmio-sram";
+			reg = <0x10080100 0x9900>;
+		};
+
 		gic: interrupt-controller at 1013d000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-- 
1.7.10.4

[PATCH 3/4] ARM: rockchip: add power-management-unit dt node

[Heiko Stübner]

The pmu is needed to bring up the cores during smp operations.
Therefore add a node and documentation for it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 Documentation/devicetree/bindings/arm/rockchip/pmu.txt |   16 ++++++++++++++++
 arch/arm/boot/dts/rk3066a.dtsi                         |    5 +++++
 2 files changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
new file mode 100644
index 0000000..3ee9b42
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
@@ -0,0 +1,16 @@
+Rockchip power-management-unit:
+-------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-pmu";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	pmu at 20004000 {
+		compatible = "rockchip,rk3066-pmu";
+		reg = <0x20004000 0x100>;
+	};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 44eabd2..7b690ab 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -67,6 +67,11 @@
 			reg = <0x10080100 0x9900>;
 		};
 
+		pmu at 20004000 {
+			compatible = "rockchip,rk3066-pmu";
+			reg = <0x20004000 0x100>;
+		};
+
 		gic: interrupt-controller at 1013d000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-- 
1.7.10.4

[PATCH 4/4] ARM: rockchip: add smp bringup code

[Heiko Stübner]

This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.

We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else it is
currently using it, so a generic implementation can be done later.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/mach-rockchip/Makefile   |    1 +
 arch/arm/mach-rockchip/core.h     |   22 ++++++
 arch/arm/mach-rockchip/headsmp.S  |   32 ++++++++
 arch/arm/mach-rockchip/platsmp.c  |  145 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/rockchip.c |    2 +
 5 files changed, 202 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/core.h
 create mode 100644 arch/arm/mach-rockchip/headsmp.S
 create mode 100644 arch/arm/mach-rockchip/platsmp.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1547d4f..4377a14 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
new file mode 100644
index 0000000..e2e7c9d
--- /dev/null
+++ b/arch/arm/mach-rockchip/core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+extern char rockchip_secondary_trampoline;
+extern char rockchip_secondary_trampoline_end;
+
+extern unsigned long rockchip_boot_fn;
+extern void rockchip_secondary_startup(void);
+
+extern struct smp_operations rockchip_smp_ops;
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
new file mode 100644
index 0000000..3dd72f7
--- /dev/null
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__CPUINIT
+
+ENTRY(rockchip_secondary_startup)
+	bl	v7_invalidate_l1
+	b	secondary_startup
+ENDPROC(rockchip_secondary_startup)
+
+ENTRY(rockchip_secondary_trampoline)
+	ldr	pc, 1f
+ENDPROC(rockchip_secondary_trampoline)
+	.globl	rockchip_boot_fn
+rockchip_boot_fn:
+1:	.space	4
+
+ENTRY(rockchip_secondary_trampoline_end)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
new file mode 100644
index 0000000..9568b3c
--- /dev/null
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include <asm/mach/map.h>
+
+#include "core.h"
+
+static void __iomem *scu_base_addr;
+static void __iomem *imem_base_addr;
+static int ncores;
+
+/*
+ * temporary PMU handling
+ */
+
+#define PMU_PWRDN_CON		0x08
+#define PMU_PWRDN_ST		0x0c
+
+static void __iomem *pmu_base_addr;
+
+static inline bool pmu_power_domain_is_on(int pd)
+{
+	return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
+}
+
+static void pmu_set_power_domain(int pd, bool on)
+{
+	u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
+	if (on)
+		val &= ~BIT(pd);
+	else
+		val |=  BIT(pd);
+	writel(val, pmu_base_addr + PMU_PWRDN_CON);
+
+	while (pmu_power_domain_is_on(pd) != on) { }
+}
+
+/*
+ * Handling of CPU cores
+ */
+
+static int __cpuinit rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long sz = &rockchip_secondary_trampoline_end -
+					    &rockchip_secondary_trampoline;
+
+	if (!imem_base_addr || !pmu_base_addr) {
+		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
+		return -ENXIO;
+	}
+
+	if (cpu >= ncores) {
+		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
+							__func__, cpu, ncores);
+		return -ENXIO;
+	}
+
+	/* copy the trampoline to sram, that gets run during startup of the core */
+	memcpy(imem_base_addr, &rockchip_secondary_trampoline, sz);
+	flush_cache_all();
+	outer_clean_range(0, sz);
+
+	dsb_sev();
+
+	/* start the core */
+	pmu_set_power_domain(0 + cpu, true);
+
+	return 0;
+}
+
+static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *node;
+	unsigned int i;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+	if (!node) {
+		pr_err("%s: missing scu\n", __func__);
+		return;
+	}
+
+	scu_base_addr = of_iomap(node, 0);
+	if (!scu_base_addr) {
+		pr_err("%s: could not map scu registers\n", __func__);
+		return;
+	}
+
+	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+	if (!node) {
+		pr_err("%s: could not find sram dt node\n", __func__);
+		return;
+	}
+
+	imem_base_addr = of_iomap(node, 0);
+
+	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
+	if (!node) {
+		pr_err("%s: could not find sram dt node\n", __func__);
+		return;
+	}
+
+	pmu_base_addr = of_iomap(node, 0);
+
+	/*
+	 * While the number of cpus is gathered from dt, also get the number
+	 * of cores from the scu to verify this value when booting the cores.
+	 */
+	ncores = scu_get_core_count(scu_base_addr);
+
+	scu_enable(scu_base_addr);
+
+	/* Make sure that all cores except the first are really off */
+	for (i = 1; i < ncores; i++)
+		pmu_set_power_domain(0 + i, false);
+
+	/* set the boot function for the sram code */
+	rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+}
+
+struct smp_operations rockchip_smp_ops __initdata = {
+	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
+	.smp_boot_secondary	= rockchip_boot_secondary,
+};
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 0933e17..fd569a1 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -24,6 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "core.h"
 
 static void __init rockchip_timer_init(void)
 {
@@ -48,6 +49,7 @@ static const char * const rockchip_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+	.smp		= smp_ops(rockchip_smp_ops),
 	.init_machine	= rockchip_dt_init,
 	.init_time	= rockchip_timer_init,
 	.dt_compat	= rockchip_board_dt_compat,
-- 
1.7.10.4

[PATCH 2/4] ARM: rockchip: add sram dt nodes and documentation

[Rob Herring]

On 06/17/2013 05:44 PM, Heiko St?bner wrote:
> The Rockchip SoCs need a special part of their sram for bringup
> of additional cores. Therefore the mapped area should be split
> into a special area for the smp code and a generic area that gets
> handled by mmio-sram.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29 ++++++++++++++++++++
>  arch/arm/boot/dts/rk3066a.dtsi                     |   14 ++++++++++
>  2 files changed, 43 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> new file mode 100644
> index 0000000..9c81fac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> @@ -0,0 +1,29 @@
> +Rockchip SRAM for smp bringup:
> +------------------------------
> +
> +Rockchip smp-capable SoCs use the first part of the sram for the bringup
> +of the cores. Once the core gets powered up it executes the code that is
> +residing at the very beginning of the sram.
> +
> +While the suspend also needs to have code in the sram that can be realized
> +with the generic mmio-sram driver and only the smp specific part needs to
> +be mapped specially in the smp code.
> +
> +Therefore split the sram mapping in a smp-specific part that gets used
> +by the smp code exclusively and a bigger generic part for mmio-sram
> +
> +Required node properties:
> +- compatible value : = "rockchip,rk3066-smp-sram";
> +- reg : physical base address and the size of the registers window
> +
> +Example:
> +
> +	sram at 10080000 {
> +		compatible = "rockchip,rk3066-smp-sram";
> +		reg = <0x10080000 0x100>;
> +	};
> +
> +	sram: sram at 10080100 {
> +		compatible = "mmio-sram";
> +		reg = <0x10080100 0x9900>;

I think a better way would be to specify some portion of the sram as
reserved rather than defining the s/w use of the sram in DT. Something
like this:

mmio-sram-reserved = <base size base size>;

where base values are relative to reg property base.

Rob

> +	};
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index 26c4311..44eabd2 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -53,6 +53,20 @@
>  			reg = <0x1013c000 0x100>;
>  		};
>  
> +		/*
> +		 * the first part of the sram is needed for the smp
> +		 * trampoline code during cpu bringup
> +		 */
> +		sram at 10080000 {
> +			compatible = "rockchip,rk3066-smp-sram";
> +			reg = <0x10080000 0x100>;
> +		};
> +
> +		sram: sram at 10080100 {
> +			compatible = "mmio-sram";
> +			reg = <0x10080100 0x9900>;
> +		};
> +
>  		gic: interrupt-controller at 1013d000 {
>  			compatible = "arm,cortex-a9-gic";
>  			interrupt-controller;
> 

[PATCH 2/4] ARM: rockchip: add sram dt nodes and documentation

[Heiko Stübner]

Am Dienstag, 18. Juni 2013, 01:41:27 schrieb Rob Herring:
> On 06/17/2013 05:44 PM, Heiko St?bner wrote:
> > The Rockchip SoCs need a special part of their sram for bringup
> > of additional cores. Therefore the mapped area should be split
> > into a special area for the smp code and a generic area that gets
> > handled by mmio-sram.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > 
> >  .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29
> >  ++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi                    
> >  |   14 ++++++++++ 2 files changed, 43 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> > b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file
> > mode 100644
> > index 0000000..9c81fac
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> > @@ -0,0 +1,29 @@
> > +Rockchip SRAM for smp bringup:
> > +------------------------------
> > +
> > +Rockchip smp-capable SoCs use the first part of the sram for the bringup
> > +of the cores. Once the core gets powered up it executes the code that is
> > +residing at the very beginning of the sram.
> > +
> > +While the suspend also needs to have code in the sram that can be
> > realized +with the generic mmio-sram driver and only the smp specific
> > part needs to +be mapped specially in the smp code.
> > +
> > +Therefore split the sram mapping in a smp-specific part that gets used
> > +by the smp code exclusively and a bigger generic part for mmio-sram
> > +
> > +Required node properties:
> > +- compatible value : = "rockchip,rk3066-smp-sram";
> > +- reg : physical base address and the size of the registers window
> > +
> > +Example:
> > +
> > +	sram at 10080000 {
> > +		compatible = "rockchip,rk3066-smp-sram";
> > +		reg = <0x10080000 0x100>;
> > +	};
> > +
> > +	sram: sram at 10080100 {
> > +		compatible = "mmio-sram";
> > +		reg = <0x10080100 0x9900>;
> 
> I think a better way would be to specify some portion of the sram as
> reserved rather than defining the s/w use of the sram in DT.
> Something like this:
> 
> mmio-sram-reserved = <base size base size>;
> 
> where base values are relative to reg property base.

hmm, but I don't see how to get then access to the reserved part. As can be 
seen in patch 4 [which I've forgotton to cc you in, sorry] the smp-trampoline 
gets copied into this area for the core to execute after poweron, so I need to 
get the mapped representation of the reserved area.

Or do you mean

- let mmio-sram only allocate the non-reserved spaces for itself
- grab mmio-sram node in the smp code and map the necessary reserved space

This might actually work.


Thanks
Heiko


> > +	};
> > diff --git a/arch/arm/boot/dts/rk3066a.dtsi
> > b/arch/arm/boot/dts/rk3066a.dtsi index 26c4311..44eabd2 100644
> > --- a/arch/arm/boot/dts/rk3066a.dtsi
> > +++ b/arch/arm/boot/dts/rk3066a.dtsi
> > @@ -53,6 +53,20 @@
> > 
> >  			reg = <0x1013c000 0x100>;
> >  		
> >  		};
> > 
> > +		/*
> > +		 * the first part of the sram is needed for the smp
> > +		 * trampoline code during cpu bringup
> > +		 */
> > +		sram at 10080000 {
> > +			compatible = "rockchip,rk3066-smp-sram";
> > +			reg = <0x10080000 0x100>;
> > +		};
> > +
> > +		sram: sram at 10080100 {
> > +			compatible = "mmio-sram";
> > +			reg = <0x10080100 0x9900>;
> > +		};
> > +
> > 
> >  		gic: interrupt-controller at 1013d000 {
> >  		
> >  			compatible = "arm,cortex-a9-gic";
> >  			interrupt-controller;

[PATCH 2/4] ARM: rockchip: add sram dt nodes and documentation

[Rob Herring]

On 06/17/2013 08:17 PM, Heiko St?bner wrote:
> Am Dienstag, 18. Juni 2013, 01:41:27 schrieb Rob Herring:
>> On 06/17/2013 05:44 PM, Heiko St?bner wrote:
>>> The Rockchip SoCs need a special part of their sram for bringup
>>> of additional cores. Therefore the mapped area should be split
>>> into a special area for the smp code and a generic area that gets
>>> handled by mmio-sram.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> ---
>>>
>>>  .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29
>>>  ++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi                    
>>>  |   14 ++++++++++ 2 files changed, 43 insertions(+)
>>>  create mode 100644
>>>  Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
>>> b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file
>>> mode 100644
>>> index 0000000..9c81fac
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
>>> @@ -0,0 +1,29 @@
>>> +Rockchip SRAM for smp bringup:
>>> +------------------------------
>>> +
>>> +Rockchip smp-capable SoCs use the first part of the sram for the bringup
>>> +of the cores. Once the core gets powered up it executes the code that is
>>> +residing at the very beginning of the sram.
>>> +
>>> +While the suspend also needs to have code in the sram that can be
>>> realized +with the generic mmio-sram driver and only the smp specific
>>> part needs to +be mapped specially in the smp code.
>>> +
>>> +Therefore split the sram mapping in a smp-specific part that gets used
>>> +by the smp code exclusively and a bigger generic part for mmio-sram
>>> +
>>> +Required node properties:
>>> +- compatible value : = "rockchip,rk3066-smp-sram";
>>> +- reg : physical base address and the size of the registers window
>>> +
>>> +Example:
>>> +
>>> +	sram at 10080000 {
>>> +		compatible = "rockchip,rk3066-smp-sram";
>>> +		reg = <0x10080000 0x100>;
>>> +	};
>>> +
>>> +	sram: sram at 10080100 {
>>> +		compatible = "mmio-sram";
>>> +		reg = <0x10080100 0x9900>;
>>
>> I think a better way would be to specify some portion of the sram as
>> reserved rather than defining the s/w use of the sram in DT.
>> Something like this:
>>
>> mmio-sram-reserved = <base size base size>;
>>
>> where base values are relative to reg property base.
> 
> hmm, but I don't see how to get then access to the reserved part. As can be 
> seen in patch 4 [which I've forgotton to cc you in, sorry] the smp-trampoline 
> gets copied into this area for the core to execute after poweron, so I need to 
> get the mapped representation of the reserved area.

That's helpful to know.

> Or do you mean
> 
> - let mmio-sram only allocate the non-reserved spaces for itself
> - grab mmio-sram node in the smp code and map the necessary reserved space

That would work. Another alternative would be having a way in the kernel
to reserve a specific region of sram.

If you have to know what to put in the sram and are putting that into
the kernel, then having to know where to put it is not really much more
kernel data. So I don't really see the point to put a "smp boot" area
into device tree.

Seems like we're getting several platforms that are putting all their
secondary core boot code into the kernel. I'm not sure this is something
we want in the kernel. We may need to define the boot protocol for
secondary cores just like the boot core and start pushing this into
bootloaders.

Rob

> 
> This might actually work.
> 
> 
> Thanks
> Heiko
> 
> 
>>> +	};
>>> diff --git a/arch/arm/boot/dts/rk3066a.dtsi
>>> b/arch/arm/boot/dts/rk3066a.dtsi index 26c4311..44eabd2 100644
>>> --- a/arch/arm/boot/dts/rk3066a.dtsi
>>> +++ b/arch/arm/boot/dts/rk3066a.dtsi
>>> @@ -53,6 +53,20 @@
>>>
>>>  			reg = <0x1013c000 0x100>;
>>>  		
>>>  		};
>>>
>>> +		/*
>>> +		 * the first part of the sram is needed for the smp
>>> +		 * trampoline code during cpu bringup
>>> +		 */
>>> +		sram at 10080000 {
>>> +			compatible = "rockchip,rk3066-smp-sram";
>>> +			reg = <0x10080000 0x100>;
>>> +		};
>>> +
>>> +		sram: sram at 10080100 {
>>> +			compatible = "mmio-sram";
>>> +			reg = <0x10080100 0x9900>;
>>> +		};
>>> +
>>>
>>>  		gic: interrupt-controller at 1013d000 {
>>>  		
>>>  			compatible = "arm,cortex-a9-gic";
>>>  			interrupt-controller;
> 

[PATCH 2/4] ARM: rockchip: add sram dt nodes and documentation

[Heiko Stübner]

Am Dienstag, 18. Juni 2013, 04:30:46 schrieb Rob Herring:
> On 06/17/2013 08:17 PM, Heiko St?bner wrote:
> > Am Dienstag, 18. Juni 2013, 01:41:27 schrieb Rob Herring:
> >> On 06/17/2013 05:44 PM, Heiko St?bner wrote:
> >>> The Rockchip SoCs need a special part of their sram for bringup
> >>> of additional cores. Therefore the mapped area should be split
> >>> into a special area for the smp code and a generic area that gets
> >>> handled by mmio-sram.
> >>> 
> >>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >>> ---
> >>> 
> >>>  .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   29
> >>>  ++++++++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi
> >>>  
> >>>  |   14 ++++++++++ 2 files changed, 43 insertions(+)
> >>>  
> >>>  create mode 100644
> >>>  Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> >>> 
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> >>> b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file
> >>> mode 100644
> >>> index 0000000..9c81fac
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
> >>> @@ -0,0 +1,29 @@
> >>> +Rockchip SRAM for smp bringup:
> >>> +------------------------------
> >>> +
> >>> +Rockchip smp-capable SoCs use the first part of the sram for the
> >>> bringup +of the cores. Once the core gets powered up it executes the
> >>> code that is +residing at the very beginning of the sram.
> >>> +
> >>> +While the suspend also needs to have code in the sram that can be
> >>> realized +with the generic mmio-sram driver and only the smp specific
> >>> part needs to +be mapped specially in the smp code.
> >>> +
> >>> +Therefore split the sram mapping in a smp-specific part that gets used
> >>> +by the smp code exclusively and a bigger generic part for mmio-sram
> >>> +
> >>> +Required node properties:
> >>> +- compatible value : = "rockchip,rk3066-smp-sram";
> >>> +- reg : physical base address and the size of the registers window
> >>> +
> >>> +Example:
> >>> +
> >>> +	sram at 10080000 {
> >>> +		compatible = "rockchip,rk3066-smp-sram";
> >>> +		reg = <0x10080000 0x100>;
> >>> +	};
> >>> +
> >>> +	sram: sram at 10080100 {
> >>> +		compatible = "mmio-sram";
> >>> +		reg = <0x10080100 0x9900>;
> >> 
> >> I think a better way would be to specify some portion of the sram as
> >> reserved rather than defining the s/w use of the sram in DT.
> >> Something like this:
> >> 
> >> mmio-sram-reserved = <base size base size>;
> >> 
> >> where base values are relative to reg property base.
> > 
> > hmm, but I don't see how to get then access to the reserved part. As can
> > be seen in patch 4 [which I've forgotton to cc you in, sorry] the
> > smp-trampoline gets copied into this area for the core to execute after
> > poweron, so I need to get the mapped representation of the reserved
> > area.
> 
> That's helpful to know.
> 
> > Or do you mean
> > 
> > - let mmio-sram only allocate the non-reserved spaces for itself
> > - grab mmio-sram node in the smp code and map the necessary reserved
> > space
> 
> That would work. Another alternative would be having a way in the kernel
> to reserve a specific region of sram.

Problem is, that the mmio-sram driver that gets to control the sram via 
genalloc only runs later in the boot process, so when bringing up smp cores 
it's not present yet.

So I'll try it with the reserve-variant above.


> If you have to know what to put in the sram and are putting that into
> the kernel, then having to know where to put it is not really much more
> kernel data. So I don't really see the point to put a "smp boot" area
> into device tree.
> 
> Seems like we're getting several platforms that are putting all their
> secondary core boot code into the kernel. I'm not sure this is something
> we want in the kernel. We may need to define the boot protocol for
> secondary cores just like the boot core and start pushing this into
> bootloaders.

sorry, but you've lost me here somewhere - but smp is also very new to me :-)

What gets put into sram for the Rockchip SoCs is

	ENTRY(rockchip_secondary_trampoline)
		ldr	pc, 1f
	ENDPROC(rockchip_secondary_trampoline)
		.globl	rockchip_boot_fn
	rockchip_boot_fn:
	1:	.space	4
	ENTRY(rockchip_secondary_trampoline_end)

that then simply points the core back to the regular kernel code, that does 
the real bringup:

	ENTRY(rockchip_secondary_startup)
		bl	v7_invalidate_l1
		b	secondary_startup
	ENDPROC(rockchip_secondary_startup)

and I currently fail to see how this would only be done in the bootloader, 
especially, as it probably needs to be rerun after turning the core off and on 
again via cpu hotplug, so the sram content there would also need to stay 
untouched.

And from what I've seen, how this is done in general in different SoCs varies 
a lot.


Heiko