* [PATCH 0/4] Enable ethernet support for SOCFPGA
@ 2013-07-17 23:10 dinguyen at altera.com
2013-07-17 23:10 ` [PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga dinguyen at altera.com
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: dinguyen at altera.com @ 2013-07-17 23:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
Hello,
These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA
platform.
patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller.
patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.
Thanks,
Dinh Nguyen (4):
arm: socfpga: Enable ARM_TWD for socfpga
arm: socfpga: Add platform initialization for ethernet
ARM: socfpga: dts: Fix entries for the ethernet entries.
arm: socfpga: Add support for SD/MMC and ethernet to defconfig
arch/arm/boot/dts/socfpga.dtsi | 4 +-
arch/arm/boot/dts/socfpga_cyclone5.dts | 2 +-
arch/arm/configs/socfpga_defconfig | 8 +++
arch/arm/mach-socfpga/Kconfig | 1 +
arch/arm/mach-socfpga/core.h | 8 +++
arch/arm/mach-socfpga/socfpga.c | 85 +++++++++++++++++++++++++++++++-
6 files changed, 104 insertions(+), 4 deletions(-)
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
--
1.7.9.5
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com @ 2013-07-17 23:10 ` dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 2/4] arm: socfpga: Add platform initialization for ethernet dinguyen at altera.com ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: dinguyen at altera.com @ 2013-07-17 23:10 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Update Kconfig to enable TWD. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Pavel Machek <pavel@denx.de> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index dd86db4..efad818 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,7 @@ config ARCH_SOCFPGA select GENERIC_CLOCKEVENTS select GPIO_PL061 if GPIOLIB select HAVE_ARM_SCU + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select MFD_SYSCON select SPARSE_IRQ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] arm: socfpga: Add platform initialization for ethernet 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga dinguyen at altera.com @ 2013-07-17 23:10 ` dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries dinguyen at altera.com ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: dinguyen at altera.com @ 2013-07-17 23:10 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add platform specific intilization to put the STMMAC ethernet controller into the correct PHY mode. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Pavel Machek <pavel@denx.de> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> --- arch/arm/mach-socfpga/core.h | 8 ++++ arch/arm/mach-socfpga/socfpga.c | 85 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 572b8f7..505b8fe5 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -28,6 +28,14 @@ #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ +#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 + extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index bfce964..abbde76 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -16,10 +16,14 @@ */ #include <linux/clk-provider.h> #include <linux/irqchip.h> +#include <linux/micrel_phy.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/of_net.h> #include <linux/of_platform.h> #include <linux/reboot.h> +#include <linux/stmmac.h> +#include <linux/phy.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -33,6 +37,22 @@ void __iomem *rst_manager_base_addr; void __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; +static int stmmac_plat_init(struct platform_device *pdev); + +static struct plat_stmmacenet_data stmmacenet0_data = { + .init = &stmmac_plat_init, +}; + +static struct plat_stmmacenet_data stmmacenet1_data = { + .init = &stmmac_plat_init, +}; + +static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data), + OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data), + {/* sentinel */} +}; + static struct map_desc scu_io_desc __initdata = { .virtual = SOCFPGA_SCU_VIRT_BASE, .pfn = 0, /* run-time */ @@ -58,6 +78,65 @@ static void __init socfpga_scu_map_io(void) iotable_init(&scu_io_desc, 1); } +static int ksz9021rlrn_phy_fixup(struct phy_device *phydev) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) { + /* min rx data delay */ + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xa0d0); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 0x104); + } + + return 0; +} + +static int stmmac_plat_init(struct platform_device *pdev) +{ + u32 ctrl, val, shift; + int phymode; + + if (of_machine_is_compatible("altr,socfpga-vt")) + return 0; + + phymode = of_get_phy_mode(pdev->dev.of_node); + + switch (phymode) { + case PHY_INTERFACE_MODE_RGMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + default: + pr_err("%s bad phy mode %d", __func__, phymode); + return -EINVAL; + } + + if (&stmmacenet1_data == pdev->dev.platform_data) + shift = SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH; + else if (&stmmacenet0_data == pdev->dev.platform_data) + shift = 0; + else { + pr_err("%s unexpected platform data pointer\n", __func__); + return -EINVAL; + } + + ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET); + ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << shift); + ctrl |= (val << shift); + + writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET)); + + return 0; +} + static void __init socfpga_map_io(void) { socfpga_scu_map_io(); @@ -106,9 +185,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + socfpga_auxdata_lookup, NULL); of_clk_init(NULL); socfpga_init_clocks(); + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN, + MICREL_PHY_ID_MASK, ksz9021rlrn_phy_fixup); } static const char *altera_dt_match[] = { -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries. 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 2/4] arm: socfpga: Add platform initialization for ethernet dinguyen at altera.com @ 2013-07-17 23:10 ` dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig dinguyen at altera.com 2013-07-18 9:16 ` [PATCH 0/4] Enable ethernet support for SOCFPGA Jack Mitchell 4 siblings, 0 replies; 10+ messages in thread From: dinguyen at altera.com @ 2013-07-17 23:10 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Use the gate-clock emac_0_clk and emac_1_clk. Fix phy-addr binding to the correct snps,phy-addr binding. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Pavel Machek <pavel@denx.de> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> --- arch/arm/boot/dts/socfpga.dtsi | 4 ++-- arch/arm/boot/dts/socfpga_cyclone5.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index dbf7f22..93ee655 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -444,7 +444,7 @@ interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; + clocks = <&emac_0_clk>; clock-names = "stmmaceth"; status = "disabled"; }; @@ -455,7 +455,7 @@ interrupts = <0 120 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; + clocks = <&emac_1_clk>; clock-names = "stmmaceth"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 1853cb1..102c4d8 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -50,7 +50,7 @@ ethernet at ff702000 { phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ + snps,phy-addr = <0xffffffff>; /* probe for phy addr */ status = "okay"; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com ` (2 preceding siblings ...) 2013-07-17 23:10 ` [PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries dinguyen at altera.com @ 2013-07-17 23:10 ` dinguyen at altera.com 2013-07-18 9:16 ` [PATCH 0/4] Enable ethernet support for SOCFPGA Jack Mitchell 4 siblings, 0 replies; 10+ messages in thread From: dinguyen at altera.com @ 2013-07-17 23:10 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY. Also enable EXT3 and NFS FS support. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Pavel Machek <pavel@denx.de> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> --- arch/arm/configs/socfpga_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 4e1ce21..dcca3a1 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -52,6 +52,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_STMMAC_ETH=y +CONFIG_MICREL_PHY=y # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set CONFIG_INPUT_EVDEV=y # CONFIG_SERIO_SERPORT is not set @@ -66,6 +67,9 @@ CONFIG_SERIAL_8250_DW=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT3_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set CONFIG_VFAT_FS=y @@ -82,3 +86,7 @@ CONFIG_DEBUG_INFO=y CONFIG_ENABLE_DEFAULT_TRACERS=y CONFIG_DEBUG_USER=y CONFIG_XZ_DEC=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_SOCFPGA=y -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 0/4] Enable ethernet support for SOCFPGA 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com ` (3 preceding siblings ...) 2013-07-17 23:10 ` [PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig dinguyen at altera.com @ 2013-07-18 9:16 ` Jack Mitchell 2013-07-18 11:35 ` Jack Mitchell 2013-07-18 11:59 ` Pavel Machek 4 siblings, 2 replies; 10+ messages in thread From: Jack Mitchell @ 2013-07-18 9:16 UTC (permalink / raw) To: linux-arm-kernel On 18/07/13 00:10, dinguyen at altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > Hello, > > These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA > platform. > > patch (1/4): Adds select ARM_TWD for the platform > patch (2/4): Add platform specific initialization for the ethernet controller. > patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr. > Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated. > patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS. > > Thanks, > > Dinh Nguyen (4): > arm: socfpga: Enable ARM_TWD for socfpga > arm: socfpga: Add platform initialization for ethernet > ARM: socfpga: dts: Fix entries for the ethernet entries. > arm: socfpga: Add support for SD/MMC and ethernet to defconfig > > arch/arm/boot/dts/socfpga.dtsi | 4 +- > arch/arm/boot/dts/socfpga_cyclone5.dts | 2 +- > arch/arm/configs/socfpga_defconfig | 8 +++ > arch/arm/mach-socfpga/Kconfig | 1 + > arch/arm/mach-socfpga/core.h | 8 +++ > arch/arm/mach-socfpga/socfpga.c | 85 +++++++++++++++++++++++++++++++- > 6 files changed, 104 insertions(+), 4 deletions(-) > > CC: Arnd Bergmann <arnd@arndb.de> > CC: Olof Johansson <olof@lixom.net> > Cc: Rob Herring <rob.herring@calxeda.com> > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Cc: Pavel Machek <pavel@denx.de> > Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> > Hi Dinh, What tree is this based against, or what patches are a pre-requisite to this series? I applied the patches to linux-arm/master but the compile failed. arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup': arch/arm/mach-socfpga/socfpga.c:85:21: error: 'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function) phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, ^ arch/arm/mach-socfpga/socfpga.c:85:21: note: each undeclared identifier is reported only once for each function it appears in arch/arm/mach-socfpga/socfpga.c:86:4: error: 'MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW' undeclared (first use in this function) MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000); ^ arch/arm/mach-socfpga/socfpga.c:87:21: error: 'MICREL_KSZ9021_EXTREG_DATA_WRITE' undeclared (first use in this function) phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); ^ arch/arm/mach-socfpga/socfpga.c:91:4: error: 'MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW' undeclared (first use in this function) MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000); ^ arch/arm/mach-socfpga/socfpga.c: In function 'socfpga_cyclone5_init': arch/arm/mach-socfpga/socfpga.c:193:30: error: 'PHY_ID_KSZ9021RLRN' undeclared (first use in this function) phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN, ^ Cheers, Jack. -- Jack Mitchell (jack at embed.me.uk) Embedded Systems Engineer http://www.embed.me.uk -- ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/4] Enable ethernet support for SOCFPGA 2013-07-18 9:16 ` [PATCH 0/4] Enable ethernet support for SOCFPGA Jack Mitchell @ 2013-07-18 11:35 ` Jack Mitchell 2013-07-18 11:59 ` Pavel Machek 1 sibling, 0 replies; 10+ messages in thread From: Jack Mitchell @ 2013-07-18 11:35 UTC (permalink / raw) To: linux-arm-kernel On 18/07/13 10:16, Jack Mitchell wrote: > On 18/07/13 00:10, dinguyen at altera.com wrote: >> From: Dinh Nguyen <dinguyen@altera.com> >> >> Hello, >> >> These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA >> platform. >> >> patch (1/4): Adds select ARM_TWD for the platform >> patch (2/4): Add platform specific initialization for the ethernet >> controller. >> patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the >> PHY addr. >> Set the ethernet clocks to be emac_0_clk and emac_1_clk so it >> be gated. >> patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS. >> >> Thanks, >> >> Dinh Nguyen (4): >> arm: socfpga: Enable ARM_TWD for socfpga >> arm: socfpga: Add platform initialization for ethernet >> ARM: socfpga: dts: Fix entries for the ethernet entries. >> arm: socfpga: Add support for SD/MMC and ethernet to defconfig >> >> arch/arm/boot/dts/socfpga.dtsi | 4 +- >> arch/arm/boot/dts/socfpga_cyclone5.dts | 2 +- >> arch/arm/configs/socfpga_defconfig | 8 +++ >> arch/arm/mach-socfpga/Kconfig | 1 + >> arch/arm/mach-socfpga/core.h | 8 +++ >> arch/arm/mach-socfpga/socfpga.c | 85 >> +++++++++++++++++++++++++++++++- >> 6 files changed, 104 insertions(+), 4 deletions(-) >> >> CC: Arnd Bergmann <arnd@arndb.de> >> CC: Olof Johansson <olof@lixom.net> >> Cc: Rob Herring <rob.herring@calxeda.com> >> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> >> Cc: Pavel Machek <pavel@denx.de> >> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> >> > > Hi Dinh, > > What tree is this based against, or what patches are a pre-requisite to > this series? I applied the patches to linux-arm/master but the compile > failed. > > arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup': > arch/arm/mach-socfpga/socfpga.c:85:21: error: > 'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function) > phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, > ^ > arch/arm/mach-socfpga/socfpga.c:85:21: note: each undeclared identifier > is reported only once for each function it appears in > arch/arm/mach-socfpga/socfpga.c:86:4: error: > 'MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW' undeclared (first use in this > function) > MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000); > ^ > arch/arm/mach-socfpga/socfpga.c:87:21: error: > 'MICREL_KSZ9021_EXTREG_DATA_WRITE' undeclared (first use in this function) > phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); > ^ > arch/arm/mach-socfpga/socfpga.c:91:4: error: > 'MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW' undeclared (first use in this > function) > MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000); > ^ > arch/arm/mach-socfpga/socfpga.c: In function 'socfpga_cyclone5_init': > arch/arm/mach-socfpga/socfpga.c:193:30: error: 'PHY_ID_KSZ9021RLRN' > undeclared (first use in this function) > phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN, > ^ > Cheers, > Jack. > Dinh, So I found your patch "phy: micrel: Add definitions for common Micrel PHY registers" and applied it, now the kernel compiles. I do however still run into the "Waiting for root device" issue. This is still on my Arrow SoCkit board, which may be a bit different to the Altera devkit; so please don't let this be a blocker if it works find with your kit. It is strange though that both boards can share the same 3.9-vendor dts/kernel without any changes... Synopsys Designware Multimedia Card Interface Driver oprofile: no performance counters oprofile: using timer interrupt. TCP: cubic registered NET: Registered protocol family 17 NET: Registered protocol family 15 VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 ThumbEE CPU extension supported. Registering SWP/SWPB emulation handler Waiting for root device /dev/mmcblk0p2... Cheers, Jack. -- Jack Mitchell (jack at embed.me.uk) Embedded Systems Engineer http://www.embed.me.uk -- ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/4] Enable ethernet support for SOCFPGA 2013-07-18 9:16 ` [PATCH 0/4] Enable ethernet support for SOCFPGA Jack Mitchell 2013-07-18 11:35 ` Jack Mitchell @ 2013-07-18 11:59 ` Pavel Machek 2013-07-18 13:12 ` Dinh Nguyen 1 sibling, 1 reply; 10+ messages in thread From: Pavel Machek @ 2013-07-18 11:59 UTC (permalink / raw) To: linux-arm-kernel Hi! > >These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA > >platform. > > > >patch (1/4): Adds select ARM_TWD for the platform > >patch (2/4): Add platform specific initialization for the ethernet controller. > >patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr. > > Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated. > >patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS. > What tree is this based against, or what patches are a pre-requisite > to this series? I applied the patches to linux-arm/master but the > compile failed. > > arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup': > arch/arm/mach-socfpga/socfpga.c:85:21: error: > 'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function) > phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, > ^ It seems it depends on: Date: Mon, 15 Jul 2013 18:08:50 -0500 From: dinguyen@altera.com To: dinh.linux at gmail.com, netdev at vger.kernel.org Cc: Pavel Machek <pavel@denx.de>, Nicolas Ferre <nicolas.ferre@atmel.com>, "David S. Miller" <davem@davemloft.net>, linux-arm-kernel at lists.infradead.org, Shawn Guo <shawn.guo@linaro.org>, Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>, Andrew Victor <linux@maxim.org.za>, Dinh Nguyen <dinguyen@altera.com> Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY registers X-Mailer: git-send-email 1.7.9.5 From: Dinh Nguyen <dinguyen@altera.com> Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines. Also add support for the KSZ9021RLRN PHY. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/4] Enable ethernet support for SOCFPGA 2013-07-18 11:59 ` Pavel Machek @ 2013-07-18 13:12 ` Dinh Nguyen 2013-07-18 13:38 ` Jack Mitchell 0 siblings, 1 reply; 10+ messages in thread From: Dinh Nguyen @ 2013-07-18 13:12 UTC (permalink / raw) To: linux-arm-kernel Hi Jack, On Thu, 2013-07-18 at 13:59 +0200, ZY - pavel wrote: > Hi! > > > >These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA > > >platform. > > > > > >patch (1/4): Adds select ARM_TWD for the platform > > >patch (2/4): Add platform specific initialization for the ethernet controller. > > >patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr. > > > Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated. > > >patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS. > > > What tree is this based against, or what patches are a pre-requisite > > to this series? I applied the patches to linux-arm/master but the > > compile failed. > > > > arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup': > > arch/arm/mach-socfpga/socfpga.c:85:21: error: > > 'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function) > > phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, > > ^ > > It seems it depends on: > > Date: Mon, 15 Jul 2013 18:08:50 -0500 > From: dinguyen at altera.com > To: dinh.linux at gmail.com, netdev at vger.kernel.org > Cc: Pavel Machek <pavel@denx.de>, Nicolas Ferre > <nicolas.ferre@atmel.com>, > "David S. Miller" <davem@davemloft.net>, > linux-arm-kernel at lists.infradead.org, > Shawn Guo <shawn.guo@linaro.org>, > Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>, > Andrew Victor <linux@maxim.org.za>, > Dinh Nguyen <dinguyen@altera.com> > Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY > registers > X-Mailer: git-send-email 1.7.9.5 > > From: Dinh Nguyen <dinguyen@altera.com> > > Add defines for common Micrel PHY setups so that other platforms > can use them. Update imx61 and sama5 hardware to use the micrel_phy.h > PHY defines. > > Also add support for the KSZ9021RLRN PHY. > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Yes, the above patch is necessary. I was hoping that patch can go into either Shawn's or Nicolas' tree. I have received ACKs from both. There is also the SD/MMC bindings patch that has not been applied to the arm-soc tree yet. I have started collecting the patches at github in the meantime: git at github.com:dinh-linux/linux-socfpga.git for-next Dinh > > Pavel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/4] Enable ethernet support for SOCFPGA 2013-07-18 13:12 ` Dinh Nguyen @ 2013-07-18 13:38 ` Jack Mitchell 0 siblings, 0 replies; 10+ messages in thread From: Jack Mitchell @ 2013-07-18 13:38 UTC (permalink / raw) To: linux-arm-kernel On 18/07/13 14:12, Dinh Nguyen wrote: > Hi Jack, > > On Thu, 2013-07-18 at 13:59 +0200, ZY - pavel wrote: >> Hi! >> >>>> These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA >>>> platform. >>>> >>>> patch (1/4): Adds select ARM_TWD for the platform >>>> patch (2/4): Add platform specific initialization for the ethernet controller. >>>> patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr. >>>> Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated. >>>> patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS. >> >>> What tree is this based against, or what patches are a pre-requisite >>> to this series? I applied the patches to linux-arm/master but the >>> compile failed. >>> >>> arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup': >>> arch/arm/mach-socfpga/socfpga.c:85:21: error: >>> 'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function) >>> phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, >>> ^ >> >> It seems it depends on: >> >> Date: Mon, 15 Jul 2013 18:08:50 -0500 >> From: dinguyen at altera.com >> To: dinh.linux at gmail.com, netdev at vger.kernel.org >> Cc: Pavel Machek <pavel@denx.de>, Nicolas Ferre >> <nicolas.ferre@atmel.com>, >> "David S. Miller" <davem@davemloft.net>, >> linux-arm-kernel at lists.infradead.org, >> Shawn Guo <shawn.guo@linaro.org>, >> Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>, >> Andrew Victor <linux@maxim.org.za>, >> Dinh Nguyen <dinguyen@altera.com> >> Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY >> registers >> X-Mailer: git-send-email 1.7.9.5 >> >> From: Dinh Nguyen <dinguyen@altera.com> >> >> Add defines for common Micrel PHY setups so that other platforms >> can use them. Update imx61 and sama5 hardware to use the micrel_phy.h >> PHY defines. >> >> Also add support for the KSZ9021RLRN PHY. >> >> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > > Yes, the above patch is necessary. I was hoping that patch can go into > either Shawn's or Nicolas' tree. I have received ACKs from both. There > is also the SD/MMC bindings patch that has not been applied to the > arm-soc tree yet. I have started collecting the patches at github in the > meantime: > > git at github.com:dinh-linux/linux-socfpga.git for-next > > Dinh Dinh, Perfect, that boots from the mmc! For what it's worth, for the whole series + pre-requisite patches on an Arrow SoCkit devkit: Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk> -- Jack Mitchell (jack at embed.me.uk) Embedded Systems Engineer http://www.embed.me.uk -- ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-07-18 13:38 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-07-17 23:10 [PATCH 0/4] Enable ethernet support for SOCFPGA dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 2/4] arm: socfpga: Add platform initialization for ethernet dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries dinguyen at altera.com 2013-07-17 23:10 ` [PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig dinguyen at altera.com 2013-07-18 9:16 ` [PATCH 0/4] Enable ethernet support for SOCFPGA Jack Mitchell 2013-07-18 11:35 ` Jack Mitchell 2013-07-18 11:59 ` Pavel Machek 2013-07-18 13:12 ` Dinh Nguyen 2013-07-18 13:38 ` Jack Mitchell
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