From: Choong Yong Liang <yong.liang.choong@linux.intel.com>
To: Simon Horman <simon.horman@corigine.com>
Cc: "Rajneesh Bhardwaj" <irenic.rajneesh@gmail.com>,
"David E Box" <david.e.box@intel.com>,
"Hans de Goede" <hdegoede@redhat.com>,
"Mark Gross" <markgross@kernel.org>,
"Jose Abreu" <Jose.Abreu@synopsys.com>,
"Andrew Lunn" <andrew@lunn.ch>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"Russell King" <linux@armlinux.org.uk>,
"David S . Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Marek Behún" <kabel@kernel.org>,
"Jean Delvare" <jdelvare@suse.com>,
"Guenter Roeck" <linux@roeck-us.net>,
"Giuseppe Cavallaro" <peppe.cavallaro@st.com>,
"Alexandre Torgue" <alexandre.torgue@foss.st.com>,
"Jose Abreu" <joabreu@synopsys.com>,
"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
"Richard Cochran" <richardcochran@gmail.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Alexei Starovoitov" <ast@kernel.org>,
"Daniel Borkmann" <daniel@iogearbox.net>,
"Jesper Dangaard Brouer" <hawk@kernel.org>,
"John Fastabend" <john.fastabend@gmail.com>,
"Wong Vee Khee" <veekhee@apple.com>,
"Jon Hunter" <jonathanh@nvidia.com>,
"Jesse Brandeburg" <jesse.brandeburg@intel.com>,
"Revanth Kumar Uppala" <ruppala@nvidia.com>,
"Shenwei Wang" <shenwei.wang@nxp.com>,
"Andrey Konovalov" <andrey.konovalov@linaro.org>,
"Jochen Henneberg" <jh@henneberg-systemdesign.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org,
bpf@vger.kernel.org, "Voon Wei Feng" <weifeng.voon@intel.com>,
Tan@web.codeaurora.org, "Tee Min" <tee.min.tan@linux.intel.com>,
"Michael Sit Wei Hong" <michael.wei.hong.sit@intel.com>,
"Lai Peter Jun Ann" <jun.ann.lai@intel.com>
Subject: Re: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access
Date: Fri, 23 Jun 2023 13:54:21 +0800 [thread overview]
Message-ID: <52021da4-c2a5-5350-0a7c-273d76a221c6@linux.intel.com> (raw)
In-Reply-To: <ZJRdllrXB4bi7oOQ@corigine.com>
Hi Simon,
Yes, you are right. I will add static in v2. Thank you.
On 22/6/2023 10:41 pm, Simon Horman wrote:
> On Thu, Jun 22, 2023 at 12:19:00PM +0800, Choong Yong Liang wrote:
>> From: "David E. Box" <david.e.box@linux.intel.com>
>>
>> - Exports intel_pmc_core_ipc() for host access to the PMC IPC mailbox
>> - Add support to use IPC command allows host to access SoC registers
>> through PMC firmware that are otherwise inaccessible to the host due to
>> security policies.
>>
>> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
>> Signed-off-by: Chao Qin <chao.qin@intel.com>
>> Signed-off-by: Choong Yong Liang <yong.liang.choong@linux.intel.com>
>
> ...
>
>> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
>> index da6e7206d38b..0d60763c5144 100644
>> --- a/drivers/platform/x86/intel/pmc/core.c
>> +++ b/drivers/platform/x86/intel/pmc/core.c
>> @@ -16,6 +16,7 @@
>> #include <linux/delay.h>
>> #include <linux/dmi.h>
>> #include <linux/io.h>
>> +#include <linux/intel_pmc_core.h>
>> #include <linux/module.h>
>> #include <linux/pci.h>
>> #include <linux/slab.h>
>> @@ -26,7 +27,9 @@
>> #include <asm/msr.h>
>> #include <asm/tsc.h>
>>
>> -#include "core.h"
>> +#define PMC_IPCS_PARAM_COUNT 7
>> +
>> +static const struct x86_cpu_id *pmc_cpu_id;
>>
>> /* Maximum number of modes supported by platfoms that has low power mode capability */
>> const char *pmc_lpm_modes[] = {
>
> Hi Choong Yong Liang,
>
> It looks like pmc_lpm_mode is used in this file and, as of this patch,
> has no declaration. Should it be static?
>
> ...
>
>> diff --git a/drivers/platform/x86/intel/pmc/core.h b/include/linux/intel_pmc_core.h
>> similarity index 95%
>> rename from drivers/platform/x86/intel/pmc/core.h
>> rename to include/linux/intel_pmc_core.h
>> index 9ca9b9746719..82810e8b92a2 100644
>> --- a/drivers/platform/x86/intel/pmc/core.h
>> +++ b/include/linux/intel_pmc_core.h
>> @@ -250,7 +250,16 @@ enum ppfear_regs {
>> #define MTL_LPM_STATUS_OFFSET 0x1700
>> #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C
>>
>> -extern const char *pmc_lpm_modes[];
>> +#define IPC_SOC_REGISTER_ACCESS 0xAA
>> +#define IPC_SOC_SUB_CMD_READ 0x00
>> +#define IPC_SOC_SUB_CMD_WRITE 0x01
>> +
>> +struct pmc_ipc_cmd {
>> + u32 cmd;
>> + u32 sub_cmd;
>> + u32 size;
>> + u32 wbuf[4];
>> +};
>>
>> struct pmc_bit_map {
>> const char *name;
>
> ...
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next prev parent reply other threads:[~2023-06-23 5:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230622041905.629430-1-yong.liang.choong@linux.intel.com>
[not found] ` <20230622041905.629430-2-yong.liang.choong@linux.intel.com>
2023-06-22 8:18 ` [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access Hans de Goede
2023-06-23 5:52 ` Choong Yong Liang
2023-06-23 12:44 ` Wong Vee Khee
2023-06-22 14:41 ` Simon Horman
2023-06-23 5:54 ` Choong Yong Liang [this message]
[not found] ` <20230622041905.629430-4-yong.liang.choong@linux.intel.com>
2023-06-22 14:43 ` [PATCH net-next 3/6] net: phy: update in-band AN mode when changing interface by PHY driver Simon Horman
2023-06-22 15:06 ` Russell King (Oracle)
2023-06-23 5:35 ` Simon Horman
2023-06-23 6:02 ` Choong Yong Liang
2023-06-23 5:57 ` Choong Yong Liang
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