* [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM
@ 2013-08-26 5:39 alison_chaiken at mentor.com
2013-08-26 13:41 ` Matt Sealey
2013-08-27 6:02 ` Huang Shijie
0 siblings, 2 replies; 10+ messages in thread
From: alison_chaiken at mentor.com @ 2013-08-26 5:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Alison Chaiken <alison_chaiken@mentor.com>
Update imx6.dtsi iomuxc pinctrl config settings to reflect Table 4-1 of Rev. 0
(11/2012) of IMX6DQRM, i.MX6 technical reference manual.
Impact:
USDHC: increase drive speed and impedance.
I2C and EIM: change drive impedance and disable open-drain.
ECSPI: change drive impedance.
ESAI and ENET: probably pedantic changes.
Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
---
arch/arm/boot/dts/imx6dl.dtsi | 148 +++++++++++++--------------
arch/arm/boot/dts/imx6q.dtsi | 226 ++++++++++++++++++++---------------------
arch/arm/boot/dts/imx6sl.dtsi | 48 ++++-----
3 files changed, 211 insertions(+), 211 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 2b3ecd6..36075b0 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -51,9 +51,9 @@
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
- MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0
+ MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0
+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0
>;
};
};
@@ -63,19 +63,19 @@
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
@@ -84,19 +84,19 @@
fsl,pins = <
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
>;
};
};
@@ -104,23 +104,23 @@
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
- MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
+ MX6DL_PAD_SD4_DAT0__NAND_DQS 0x1b0b0
>;
};
};
@@ -128,8 +128,8 @@
i2c1 {
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
- MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0
+ MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0
>;
};
};
@@ -137,8 +137,8 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
- MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
+ MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
>;
};
};
@@ -146,8 +146,8 @@
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
- MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0
+ MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0
>;
};
};
@@ -155,7 +155,7 @@
usbotg {
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
- MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0
>;
};
};
@@ -163,16 +163,16 @@
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
- MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6DL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
+ MX6DL_PAD_NANDF_D4__SD2_DATA4 0x1b0b0
+ MX6DL_PAD_NANDF_D5__SD2_DATA5 0x1b0b0
+ MX6DL_PAD_NANDF_D6__SD2_DATA6 0x1b0b0
+ MX6DL_PAD_NANDF_D7__SD2_DATA7 0x1b0b0
>;
};
};
@@ -180,27 +180,27 @@
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
+ MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0
+ MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0
+ MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0
+ MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0
>;
};
pinctrl_usdhc3_2: usdhc3grp_2 {
fsl,pins = <
- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
>;
};
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ba09dc3..826bfe0 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -103,9 +103,9 @@
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
- MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0
+ MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0
+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0
>;
};
};
@@ -125,19 +125,19 @@
fsl,pins = <
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
@@ -146,19 +146,19 @@
fsl,pins = <
MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
>;
};
@@ -166,19 +166,19 @@
fsl,pins = <
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
@@ -187,22 +187,22 @@
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
- MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6Q_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
+ MX6Q_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
+ MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
+ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
+ MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
+ MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
+ MX6Q_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
+ MX6Q_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
+ MX6Q_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
+ MX6Q_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
+ MX6Q_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
+ MX6Q_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
+ MX6Q_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
+ MX6Q_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
+ MX6Q_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
+ MX6Q_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
@@ -211,15 +211,15 @@
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
- MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b0b0
+ MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b0b0
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
- MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0
+ MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0
>;
};
};
@@ -227,8 +227,8 @@
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
- MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b0b0
+ MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b0b0
>;
};
};
@@ -236,8 +236,8 @@
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
- MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b0b0
+ MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b0b0
>;
};
};
@@ -245,8 +245,8 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
- MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
+ MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
>;
};
};
@@ -254,8 +254,8 @@
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
- MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b0
+ MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b0
>;
};
};
@@ -263,8 +263,8 @@
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
- MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0
+ MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0
>;
};
};
@@ -272,13 +272,13 @@
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
- MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6Q_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
- MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0
>;
};
};
@@ -286,27 +286,27 @@
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
- MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
+ MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
+ MX6Q_PAD_NANDF_D4__SD2_DATA4 0x1b0b0
+ MX6Q_PAD_NANDF_D5__SD2_DATA5 0x1b0b0
+ MX6Q_PAD_NANDF_D6__SD2_DATA6 0x1b0b0
+ MX6Q_PAD_NANDF_D7__SD2_DATA7 0x1b0b0
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
- MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
>;
};
};
@@ -314,27 +314,27 @@
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
- MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
+ MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0
+ MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0
+ MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0
+ MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
- MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
>;
};
};
@@ -342,27 +342,27 @@
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
- MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
+ MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
+ MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
+ MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
+ MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x1b0b0
+ MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x1b0b0
+ MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x1b0b0
+ MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x1b0b0
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
- MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
+ MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
+ MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
+ MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
>;
};
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c5e5da0..81edb19 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -527,8 +527,8 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b0
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b0
>;
};
};
@@ -536,16 +536,16 @@
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x1b0b0
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x1b0b0
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x1b0b0
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x1b0b0
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x1b0b0
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x1b0b0
>;
};
};
@@ -553,12 +553,12 @@
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x1b0b0
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
>;
};
};
@@ -566,12 +566,12 @@
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x1b0b0
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
>;
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM
2013-08-26 5:39 [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM alison_chaiken at mentor.com
@ 2013-08-26 13:41 ` Matt Sealey
2013-08-26 19:34 ` Chaiken, Alison
2013-08-27 6:02 ` Huang Shijie
1 sibling, 1 reply; 10+ messages in thread
From: Matt Sealey @ 2013-08-26 13:41 UTC (permalink / raw)
To: linux-arm-kernel
Have these been cross-referenced against the same table in Rev 1 of
the manual (4/2013)?
On Mon, Aug 26, 2013 at 12:39 AM, <alison_chaiken@mentor.com> wrote:
> From: Alison Chaiken <alison_chaiken@mentor.com>
>
> Update imx6.dtsi iomuxc pinctrl config settings to reflect Table 4-1 of Rev. 0
> (11/2012) of IMX6DQRM, i.MX6 technical reference manual.
>
> Impact:
> USDHC: increase drive speed and impedance.
> I2C and EIM: change drive impedance and disable open-drain.
> ECSPI: change drive impedance.
> ESAI and ENET: probably pedantic changes.
>
> Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
> ---
> arch/arm/boot/dts/imx6dl.dtsi | 148 +++++++++++++--------------
> arch/arm/boot/dts/imx6q.dtsi | 226 ++++++++++++++++++++---------------------
> arch/arm/boot/dts/imx6sl.dtsi | 48 ++++-----
> 3 files changed, 211 insertions(+), 211 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 2b3ecd6..36075b0 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -51,9 +51,9 @@
> ecspi1 {
> pinctrl_ecspi1_1: ecspi1grp-1 {
> fsl,pins = <
> - MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> - MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> - MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0
> + MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0
> + MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0
> >;
> };
> };
> @@ -63,19 +63,19 @@
> fsl,pins = <
> MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030
> + MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
> MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030
> + MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
> MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> >;
> };
> @@ -84,19 +84,19 @@
> fsl,pins = <
> MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
> MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
> - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x13030
> + MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
> MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x13030
> + MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
> >;
> };
> };
> @@ -104,23 +104,23 @@
> gpmi-nand {
> pinctrl_gpmi_nand_1: gpmi-nand-1 {
> fsl,pins = <
> - MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> - MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> - MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> - MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
> - MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> - MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> - MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> - MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> - MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> - MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> - MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> - MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> - MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> - MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> - MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> - MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> - MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> + MX6DL_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
> + MX6DL_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
> + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
> + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
> + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
> + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
> + MX6DL_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
> + MX6DL_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
> + MX6DL_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
> + MX6DL_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
> + MX6DL_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
> + MX6DL_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
> + MX6DL_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
> + MX6DL_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
> + MX6DL_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
> + MX6DL_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
> + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x1b0b0
> >;
> };
> };
> @@ -128,8 +128,8 @@
> i2c1 {
> pinctrl_i2c1_2: i2c1grp-2 {
> fsl,pins = <
> - MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> - MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0
> + MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0
> >;
> };
> };
> @@ -137,8 +137,8 @@
> uart1 {
> pinctrl_uart1_1: uart1grp-1 {
> fsl,pins = <
> - MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> - MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
> + MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
> >;
> };
> };
> @@ -146,8 +146,8 @@
> uart4 {
> pinctrl_uart4_1: uart4grp-1 {
> fsl,pins = <
> - MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> - MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0
> + MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0
> >;
> };
> };
> @@ -155,7 +155,7 @@
> usbotg {
> pinctrl_usbotg_2: usbotggrp-2 {
> fsl,pins = <
> - MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0
> >;
> };
> };
> @@ -163,16 +163,16 @@
> usdhc2 {
> pinctrl_usdhc2_1: usdhc2grp-1 {
> fsl,pins = <
> - MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6DL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
> MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
> - MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> - MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> - MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> - MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> - MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
> - MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
> - MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
> - MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
> + MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
> + MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
> + MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
> + MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
> + MX6DL_PAD_NANDF_D4__SD2_DATA4 0x1b0b0
> + MX6DL_PAD_NANDF_D5__SD2_DATA5 0x1b0b0
> + MX6DL_PAD_NANDF_D6__SD2_DATA6 0x1b0b0
> + MX6DL_PAD_NANDF_D7__SD2_DATA7 0x1b0b0
> >;
> };
> };
> @@ -180,27 +180,27 @@
> usdhc3 {
> pinctrl_usdhc3_1: usdhc3grp-1 {
> fsl,pins = <
> - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
> MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
> - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> - MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> - MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> - MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> - MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
> + MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0
> + MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0
> + MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0
> + MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0
> >;
> };
>
> pinctrl_usdhc3_2: usdhc3grp_2 {
> fsl,pins = <
> - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6DL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
> MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
> - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
> + MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
> + MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
> + MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
> >;
> };
> };
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ba09dc3..826bfe0 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -103,9 +103,9 @@
> ecspi1 {
> pinctrl_ecspi1_1: ecspi1grp-1 {
> fsl,pins = <
> - MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> - MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> - MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0
> + MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0
> + MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0
> >;
> };
> };
> @@ -125,19 +125,19 @@
> fsl,pins = <
> MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
> + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
> MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
> + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
> MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> >;
> };
> @@ -146,19 +146,19 @@
> fsl,pins = <
> MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
> MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
> - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
> + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
> MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
> + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
> >;
> };
>
> @@ -166,19 +166,19 @@
> fsl,pins = <
> MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x13030
> + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b030
> + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b030
> + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b030
> + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b030
> + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
> MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x13030
> + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b030
> + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b030
> + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b030
> + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b030
> + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
> MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> >;
> };
> @@ -187,22 +187,22 @@
> gpmi-nand {
> pinctrl_gpmi_nand_1: gpmi-nand-1 {
> fsl,pins = <
> - MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> - MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> - MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> - MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
> - MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> - MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> - MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> - MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> - MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> - MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> - MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> - MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> - MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> - MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> - MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> - MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> + MX6Q_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
> + MX6Q_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
> + MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
> + MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
> + MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
> + MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
> + MX6Q_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
> + MX6Q_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
> + MX6Q_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
> + MX6Q_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
> + MX6Q_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
> + MX6Q_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
> + MX6Q_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
> + MX6Q_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
> + MX6Q_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
> + MX6Q_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
> MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
> >;
> };
> @@ -211,15 +211,15 @@
> i2c1 {
> pinctrl_i2c1_1: i2c1grp-1 {
> fsl,pins = <
> - MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
> - MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
> + MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b0b0
> + MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b0b0
> >;
> };
>
> pinctrl_i2c1_2: i2c1grp-2 {
> fsl,pins = <
> - MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> - MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0
> + MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0
> >;
> };
> };
> @@ -227,8 +227,8 @@
> i2c2 {
> pinctrl_i2c2_1: i2c2grp-1 {
> fsl,pins = <
> - MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
> - MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
> + MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b0b0
> + MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b0b0
> >;
> };
> };
> @@ -236,8 +236,8 @@
> i2c3 {
> pinctrl_i2c3_1: i2c3grp-1 {
> fsl,pins = <
> - MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
> - MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
> + MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b0b0
> + MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b0b0
> >;
> };
> };
> @@ -245,8 +245,8 @@
> uart1 {
> pinctrl_uart1_1: uart1grp-1 {
> fsl,pins = <
> - MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> - MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
> + MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
> >;
> };
> };
> @@ -254,8 +254,8 @@
> uart2 {
> pinctrl_uart2_1: uart2grp-1 {
> fsl,pins = <
> - MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> - MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b0
> + MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b0
> >;
> };
> };
> @@ -263,8 +263,8 @@
> uart4 {
> pinctrl_uart4_1: uart4grp-1 {
> fsl,pins = <
> - MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> - MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0
> + MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0
> >;
> };
> };
> @@ -272,13 +272,13 @@
> usbotg {
> pinctrl_usbotg_1: usbotggrp-1 {
> fsl,pins = <
> - MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
> + MX6Q_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
> >;
> };
>
> pinctrl_usbotg_2: usbotggrp-2 {
> fsl,pins = <
> - MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0
> >;
> };
> };
> @@ -286,27 +286,27 @@
> usdhc2 {
> pinctrl_usdhc2_1: usdhc2grp-1 {
> fsl,pins = <
> - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0
> MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
> - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
> - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
> - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
> - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
> - MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
> - MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
> - MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
> - MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
> + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
> + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
> + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
> + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
> + MX6Q_PAD_NANDF_D4__SD2_DATA4 0x1b0b0
> + MX6Q_PAD_NANDF_D5__SD2_DATA5 0x1b0b0
> + MX6Q_PAD_NANDF_D6__SD2_DATA6 0x1b0b0
> + MX6Q_PAD_NANDF_D7__SD2_DATA7 0x1b0b0
> >;
> };
>
> pinctrl_usdhc2_2: usdhc2grp-2 {
> fsl,pins = <
> - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6Q_PAD_SD2_CMD__SD2_CMD 0x1b0b0
> MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
> - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
> - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
> - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
> - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
> + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
> + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
> + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
> >;
> };
> };
> @@ -314,27 +314,27 @@
> usdhc3 {
> pinctrl_usdhc3_1: usdhc3grp-1 {
> fsl,pins = <
> - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0
> MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
> - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
> - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
> - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
> - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
> - MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
> - MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
> - MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
> - MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
> + MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0
> + MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0
> + MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0
> + MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0
> >;
> };
>
> pinctrl_usdhc3_2: usdhc3grp-2 {
> fsl,pins = <
> - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6Q_PAD_SD3_CMD__SD3_CMD 0x1b0b0
> MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
> - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
> - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
> - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
> - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
> + MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
> + MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
> + MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
> >;
> };
> };
> @@ -342,27 +342,27 @@
> usdhc4 {
> pinctrl_usdhc4_1: usdhc4grp-1 {
> fsl,pins = <
> - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0
> MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
> - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
> - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
> - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
> - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
> - MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
> - MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
> - MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
> - MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
> + MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
> + MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
> + MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
> + MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x1b0b0
> + MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x1b0b0
> + MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x1b0b0
> + MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x1b0b0
> >;
> };
>
> pinctrl_usdhc4_2: usdhc4grp-2 {
> fsl,pins = <
> - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6Q_PAD_SD4_CMD__SD4_CMD 0x1b0b0
> MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
> - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
> - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
> - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
> - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
> + MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
> + MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
> + MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
> >;
> };
> };
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index c5e5da0..81edb19 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -527,8 +527,8 @@
> uart1 {
> pinctrl_uart1_1: uart1grp-1 {
> fsl,pins = <
> - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
> - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
> + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b0
> + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b0
> >;
> };
> };
> @@ -536,16 +536,16 @@
> usdhc1 {
> pinctrl_usdhc1_1: usdhc1grp-1 {
> fsl,pins = <
> - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
> - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
> - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
> - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
> - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
> - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
> - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
> - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
> - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
> - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
> + MX6SL_PAD_SD1_CMD__SD1_CMD 0x1b0b0
> + MX6SL_PAD_SD1_CLK__SD1_CLK 0x1b0b0
> + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0
> + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0
> + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0
> + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0
> + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x1b0b0
> + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x1b0b0
> + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x1b0b0
> + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x1b0b0
> >;
> };
> };
> @@ -553,12 +553,12 @@
> usdhc2 {
> pinctrl_usdhc2_1: usdhc2grp-1 {
> fsl,pins = <
> - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
> - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
> - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6SL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
> + MX6SL_PAD_SD2_CLK__SD2_CLK 0x1b0b0
> + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
> + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
> + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
> + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
> >;
> };
> };
> @@ -566,12 +566,12 @@
> usdhc3 {
> pinctrl_usdhc3_1: usdhc3grp-1 {
> fsl,pins = <
> - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
> - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
> - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6SL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
> + MX6SL_PAD_SD3_CLK__SD3_CLK 0x1b0b0
> + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
> + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
> + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
> + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
> >;
> };
> };
> --
> 1.7.10.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM
2013-08-26 13:41 ` Matt Sealey
@ 2013-08-26 19:34 ` Chaiken, Alison
0 siblings, 0 replies; 10+ messages in thread
From: Chaiken, Alison @ 2013-08-26 19:34 UTC (permalink / raw)
To: linux-arm-kernel
Matt Sealey [neko at bakuhatsu.net] helpfully inquires:
Have these been cross-referenced against the same table in Rev 1 of the manual (4/2013)?
I respond: indeed they have been! The configs in the patch have been checked against the table in the Rev. 1 April manual, which has a different format but not new values. I absent-mindedly selected an old version of the commit message, sorry.
In addition, the configs have been tested with kernels older than the older release on multiple reference boards from Freescale and Boundary Devices. Furthermore, many of the changes were ack'ed by Huang Shijie of FSL in, for example,
http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg32771.html
In April I submitted a related documentation patch
http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg30583.html
that has fallen by the wayside. Sorry for failing to include this information in the original posting, but I could not get "git send-email --compose" to behave properly with emacsclient and employer's SMTP.
--
Alison Chaiken
Mentor Embedded Software Division
Fremont, CA USA
alison_chaiken at mentor.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM
2013-08-26 5:39 [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM alison_chaiken at mentor.com
2013-08-26 13:41 ` Matt Sealey
@ 2013-08-27 6:02 ` Huang Shijie
2013-08-28 3:17 ` [PATCH 0/2] alison_chaiken at mentor.com
1 sibling, 1 reply; 10+ messages in thread
From: Huang Shijie @ 2013-08-27 6:02 UTC (permalink / raw)
To: linux-arm-kernel
? 2013?08?26? 13:39, alison_chaiken at mentor.com ??:
> From: Alison Chaiken <alison_chaiken@mentor.com>
>
> Update imx6.dtsi iomuxc pinctrl config settings to reflect Table 4-1 of Rev. 0
> (11/2012) of IMX6DQRM, i.MX6 technical reference manual.
>
> Impact:
> USDHC: increase drive speed and impedance.
> I2C and EIM: change drive impedance and disable open-drain.
> ECSPI: change drive impedance.
> ESAI and ENET: probably pedantic changes.
Could you rebase this patch with the latest code? linux-next?
thanks
Huang Shijie
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2]
2013-08-27 6:02 ` Huang Shijie
@ 2013-08-28 3:17 ` alison_chaiken at mentor.com
2013-08-28 3:17 ` [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM alison_chaiken at mentor.com
2013-08-28 3:17 ` [PATCH 2/2] i.MX6: Documentation: Change fsl, imx-pinctrl.txt to match i.MX6 TRM alison_chaiken at mentor.com
0 siblings, 2 replies; 10+ messages in thread
From: alison_chaiken at mentor.com @ 2013-08-28 3:17 UTC (permalink / raw)
To: linux-arm-kernel
From: Alison Chaiken <alison_chaiken@mentor.com>
Tested on a variety of i.MX6 reference boards with older kernels. Newly added
pinctrl configuration settings that are not tested are not modified.
Changes since v1:
* Now rebased on linux-next.
Alison Chaiken (2):
ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM
i.MX6: Documentation: Change fsl,imx-pinctrl.txt to match i.MX6 TRM
.../bindings/pinctrl/fsl,imx-pinctrl.txt | 25 +-
arch/arm/boot/dts/imx6qdl.dtsi | 354 ++++++++++-----------
arch/arm/boot/dts/imx6sl.dtsi | 48 +--
3 files changed, 214 insertions(+), 213 deletions(-)
--
1.8.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM
2013-08-28 3:17 ` [PATCH 0/2] alison_chaiken at mentor.com
@ 2013-08-28 3:17 ` alison_chaiken at mentor.com
2013-09-02 5:01 ` Huang Shijie
2013-08-28 3:17 ` [PATCH 2/2] i.MX6: Documentation: Change fsl, imx-pinctrl.txt to match i.MX6 TRM alison_chaiken at mentor.com
1 sibling, 1 reply; 10+ messages in thread
From: alison_chaiken at mentor.com @ 2013-08-28 3:17 UTC (permalink / raw)
To: linux-arm-kernel
From: Alison Chaiken <alison_chaiken@mentor.com>
Update imx6.dtsi iomuxc pinctrl config settings to reflect Table 4-1 of Rev. 1
(4/2013) of IMX6DQRM, i.MX6 technical reference manual.
Impact:
USDHC: increase drive speed and impedance.
I2C and EIM: change drive impedance and disable open-drain.
ECSPI: change drive impedance.
ESAI and ENET: probably pedantic changes.
Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 354 ++++++++++++++++++++---------------------
arch/arm/boot/dts/imx6sl.dtsi | 48 +++---
2 files changed, 201 insertions(+), 201 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ccd55c2..b1285c3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -611,17 +611,17 @@
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b0b0
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x1b0b0
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x1b0b0
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1b0b0
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1b0b0
>;
};
};
@@ -629,9 +629,9 @@
ecspi3 {
pinctrl_ecspi3_1: ecspi3grp-1 {
fsl,pins = <
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x1b0b0
>;
};
};
@@ -641,19 +641,19 @@
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
@@ -662,19 +662,19 @@
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
>;
};
@@ -682,19 +682,19 @@
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
@@ -703,30 +703,30 @@
esai {
pinctrl_esai_1: esaigrp-1 {
fsl,pins = <
- MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
+ MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b0b0
+ MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b0b0
>;
};
pinctrl_esai_2: esaigrp-2 {
fsl,pins = <
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
+ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b0b0
+ MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b0b0
+ MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b0b0
+ MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b0b0
>;
};
};
@@ -759,23 +759,23 @@
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x1b0b0
>;
};
};
@@ -820,15 +820,15 @@
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b0b0
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b0b0
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b0b0
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b0b0
>;
};
};
@@ -836,22 +836,22 @@
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b0b0
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b0b0
>;
};
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b0b0
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b0b0
>;
};
pinctrl_i2c2_3: i2c2grp-3 {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b0b0
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b0b0
>;
};
};
@@ -859,29 +859,29 @@
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b0b0
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b0b0
>;
};
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b0b0
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b0b0
>;
};
pinctrl_i2c3_3: i2c3grp-3 {
fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b0b0
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b0b0
>;
};
pinctrl_i2c3_4: i2c3grp-4 {
fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b0b0
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b0b0
>;
};
};
@@ -1015,8 +1015,8 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
>;
};
};
@@ -1024,15 +1024,15 @@
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b0
>;
};
pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
>;
@@ -1042,8 +1042,8 @@
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b0
+ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
@@ -1051,8 +1051,8 @@
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
@@ -1062,8 +1062,8 @@
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b0
>;
};
};
@@ -1071,13 +1071,13 @@
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0
>;
};
};
@@ -1115,27 +1115,27 @@
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
- MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
- MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
- MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x1b0b0
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x1b0b0
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0
+ MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x1b0b0
>;
};
pinctrl_usdhc1_2: usdhc1grp-2 {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x1b0b0
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x1b0b0
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0
>;
};
};
@@ -1143,27 +1143,27 @@
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x1b0b0
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x1b0b0
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x1b0b0
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
>;
};
};
@@ -1171,27 +1171,27 @@
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1b0b0
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x1b0b0
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x1b0b0
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x1b0b0
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x1b0b0
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1b0b0
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
>;
};
};
@@ -1199,27 +1199,27 @@
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1b0b0
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x1b0b0
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x1b0b0
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x1b0b0
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x1b0b0
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1b0b0
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x1b0b0
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x1b0b0
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x1b0b0
>;
};
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c46651e..946402d 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -551,8 +551,8 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b0
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b0
>;
};
};
@@ -560,16 +560,16 @@
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x1b0b0
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x1b0b0
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x1b0b0
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x1b0b0
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x1b0b0
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x1b0b0
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x1b0b0
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x1b0b0
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x1b0b0
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x1b0b0
>;
};
};
@@ -577,12 +577,12 @@
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x1b0b0
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x1b0b0
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x1b0b0
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x1b0b0
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x1b0b0
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x1b0b0
>;
};
};
@@ -590,12 +590,12 @@
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x1b0b0
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x1b0b0
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x1b0b0
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x1b0b0
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x1b0b0
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x1b0b0
>;
};
};
--
1.8.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM
2013-08-28 3:17 ` [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM alison_chaiken at mentor.com
@ 2013-09-02 5:01 ` Huang Shijie
2013-09-03 16:01 ` Chaiken, Alison
2013-09-04 13:48 ` Shawn Guo
0 siblings, 2 replies; 10+ messages in thread
From: Huang Shijie @ 2013-09-02 5:01 UTC (permalink / raw)
To: linux-arm-kernel
? 2013?08?28? 11:17, alison_chaiken at mentor.com ??:
> @@ -759,23 +759,23 @@
> gpmi-nand {
> pinctrl_gpmi_nand_1: gpmi-nand-1 {
> fsl,pins = <
> - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
> - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x1b0b0
> + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x1b0b0
> + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x1b0b0
> + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x1b0b0
> + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x1b0b0
> + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x1b0b0
> + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x1b0b0
> + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x1b0b0
> + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x1b0b0
> + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x1b0b0
> + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x1b0b0
> + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x1b0b0
> + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x1b0b0
> + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x1b0b0
> + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x1b0b0
> + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x1b0b0
> >;
> };
> };
I tested this patch with the imx6q-ard board and imx6dl-ard board.
For the gpmi nand test result:
[1] imx6q-ard: We can pass the bonie++ stress test with the imx6q-ard board.
[2] imx6dl-ard: But we fails to read the nand ID with the imx6dl-ard board.
In other word, this gpmi can _not_ works with this patch.
But without this patch, the imx6dl-ard works fine.
In section 4.1, the spec tells us that the 0x1b0b0 is just the "default
settings for the each pad",
not the right settings for the each pad.
thanks
Huang Shijie
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM
2013-09-02 5:01 ` Huang Shijie
@ 2013-09-03 16:01 ` Chaiken, Alison
2013-09-04 13:48 ` Shawn Guo
1 sibling, 0 replies; 10+ messages in thread
From: Chaiken, Alison @ 2013-09-03 16:01 UTC (permalink / raw)
To: linux-arm-kernel
I wrote:
>> @@ -759,23 +759,23 @@
>> gpmi-nand {
>> pinctrl_gpmi_nand_1: gpmi-nand-1 {
>> fsl,pins = <
>> - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
>> - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
[ . . . ]
>> };
>> };
Huang Shijie [b32955 at freescale.com] responds:
>I tested this patch with the imx6q-ard board and imx6dl-ard board.
>For the gpmi nand test result:
>[1] imx6q-ard: We can pass the bonie++ stress test with the imx6q-ard board.
>[2] imx6dl-ard: But we fails to read the nand ID with the imx6dl-ard board.
>In other word, this gpmi can _not_ works with this patch.
Huang, I appreciate your speedy testing and sharing of results. While I carefully and lengthily RTFM to create this patch, we can agree that making the hardware work well is the final goal! We have tested the patch I sent on our hardware with our tests, but certainly any patch that renders some features of some boards inoperable is unacceptable.
The patch we are discussing is about 670 lines, and the NAND part is about 60. What is your advice regarding the remaining ~600 lines?
Best wishes,
Alison Chaiken
Mentor Embedded Software Division
Fremont, CA, USA
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM
2013-09-02 5:01 ` Huang Shijie
2013-09-03 16:01 ` Chaiken, Alison
@ 2013-09-04 13:48 ` Shawn Guo
1 sibling, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2013-09-04 13:48 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 02, 2013 at 01:01:39PM +0800, Huang Shijie wrote:
> I tested this patch with the imx6q-ard board and imx6dl-ard board.
>
> For the gpmi nand test result:
> [1] imx6q-ard: We can pass the bonie++ stress test with the imx6q-ard board.
>
> [2] imx6dl-ard: But we fails to read the nand ID with the imx6dl-ard board.
> In other word, this gpmi can _not_ works with this patch.
The reason I'm not keen on merging this patch is just because I'm
concerned by such breakages that it could possibly bring us.
Do you actually see any issue in real with using the existing pad
settings on your board?
> But without this patch, the imx6dl-ard works fine.
>
> In section 4.1, the spec tells us that the 0x1b0b0 is just the "default
> settings for the each pad",
> not the right settings for the each pad.
+1, the default setting != the best setting for boards, and that's why
the design leaves the pad settings configurable.
Shawn
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] i.MX6: Documentation: Change fsl, imx-pinctrl.txt to match i.MX6 TRM
2013-08-28 3:17 ` [PATCH 0/2] alison_chaiken at mentor.com
2013-08-28 3:17 ` [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM alison_chaiken at mentor.com
@ 2013-08-28 3:17 ` alison_chaiken at mentor.com
1 sibling, 0 replies; 10+ messages in thread
From: alison_chaiken at mentor.com @ 2013-08-28 3:17 UTC (permalink / raw)
To: linux-arm-kernel
From: Alison Chaiken <alison_chaiken@mentor.com>
Update documentation file fsl,imx-pinctrl.txt to match iomuxc pinctrl config
settings to reflect Rev. 1 (4/2013) of IMX6DQRM, i.MX6 technical reference
manual.
Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
---
.../bindings/pinctrl/fsl,imx-pinctrl.txt | 25 +++++++++++-----------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
index 3a7caf7..9b347f1 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -72,23 +72,24 @@ iomuxc at 020e0000 {
/* shared pinctrl settings */
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ fsl,pins = <1386 0x1b0b0 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
- 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
- 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
- 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
- 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
- 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
- 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
- 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
- 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+ 1462 0x1b0b0 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x1b0b0 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x1b0b0 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x1b0b0 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x1b0b0 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x1b0b0 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x1b0b0 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x1b0b0>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
};
};
....
};
-Refer to the IOMUXC controller chapter in imx6q datasheet,
-0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
-80Ohm driver strength and Fast Slew Rate.
+Referring to "Pin Assignments" Table of "i.MX 6Dual/6Quad Applications Processor
+Reference Manual, Rev. 1, 04/2013",
+0x1b0b0 means enable hysteresis, 100KOhm Pull Up, 100Mhz speed,
+40Ohm driver strength and Slow Slew Rate.
User should refer to each SoC spec to set the correct value.
TODO: when dtc macro support is available, we can change above raw data
--
1.8.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-09-04 13:48 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2013-08-26 5:39 [PATCH] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 0 IMX6DQRM alison_chaiken at mentor.com
2013-08-26 13:41 ` Matt Sealey
2013-08-26 19:34 ` Chaiken, Alison
2013-08-27 6:02 ` Huang Shijie
2013-08-28 3:17 ` [PATCH 0/2] alison_chaiken at mentor.com
2013-08-28 3:17 ` [PATCH 1/2] ARM: i.MX6: dts: change iomuxc pinctrl config to match Rev. 1 IMX6DQRM alison_chaiken at mentor.com
2013-09-02 5:01 ` Huang Shijie
2013-09-03 16:01 ` Chaiken, Alison
2013-09-04 13:48 ` Shawn Guo
2013-08-28 3:17 ` [PATCH 2/2] i.MX6: Documentation: Change fsl, imx-pinctrl.txt to match i.MX6 TRM alison_chaiken at mentor.com
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