[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

From: Vaibhav Bedia <vaibhav.bedia@ti.com>

The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.

The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>

Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/kernel/head.S |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..4924b11 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -486,7 +486,23 @@ __fixup_smp:
 	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
 	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
 	teq	r0, #0x80000000		@ not part of a uniprocessor system?
-	moveq	pc, lr			@ yes, assume SMP
+	bne    __fixup_smp_on_up	@ no, assume UP
+
+	@ Core indicates it is SMP.  Check for Aegis SOC where a single
+	@ Cortex-A9 CPU is present but SMP operations fault.
+	mov	r4, #0x41000000
+	orr	r4, r4, #0x0000c000
+	orr	r4, r4, #0x00000090
+	teq	r3, r4			@ Check for ARM Cortex-A9
+	movne	pc, lr			@ Not ARM Cortex-A9,
+
+	mrc	p15, 4, r0, c15, c0	@ get SCU base address
+	teq	r0, #0x0		@ '0' on actual UP A9 hardware
+	beq	__fixup_smp_on_up	@ So its an A9 UP
+	ldr	r0, [r0, #4]		@ read SCU Config
+	and	r0, r0, #0x3		@ number of CPUs
+	teq	r0, #0x0		@ is 1?
+	movne	pc, lr
 
 __fixup_smp_on_up:
 	adr	r0, 1f
-- 
1.7.9.5

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Will Deacon]

On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
> 
> The generic code is well equipped to differentiate between
> SMP and UP configurations.However, there are some devices which
> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
> the SMP_ON_UP support, we need to additionally check the
> number the cores in Cortex-A9 MPCore configuration. Without
> such a check in place, the startup code tries to execute
> ALT_SMP() set of instructions which lead to CPU faults.
> 
> The issue was spotted on TI's Aegis device and this patch
> makes now the device work with omap2plus_defconfig which
> enables SMP by default. The change is kept limited to only
> Cortex-A9 MPCore detection code.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> 
> Acked-by: Sricharan R <r.sricharan@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 9cf6063..4924b11 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -486,7 +486,23 @@ __fixup_smp:
>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
> -	moveq	pc, lr			@ yes, assume SMP
> +	bne    __fixup_smp_on_up	@ no, assume UP
> +
> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
> +	@ Cortex-A9 CPU is present but SMP operations fault.
> +	mov	r4, #0x41000000
> +	orr	r4, r4, #0x0000c000
> +	orr	r4, r4, #0x00000090
> +	teq	r3, r4			@ Check for ARM Cortex-A9
> +	movne	pc, lr			@ Not ARM Cortex-A9,
> +
> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
> +	teq	r0, #0x0		@ '0' on actual UP A9 hardware
> +	beq	__fixup_smp_on_up	@ So its an A9 UP

What if somebody builds an MP A9 with the private peripheral base address at
0x0?

Will

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Friday 02 August 2013 05:53 AM, Will Deacon wrote:
> On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
>> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>
>> The generic code is well equipped to differentiate between
>> SMP and UP configurations.However, there are some devices which
>> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
>> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
>> the SMP_ON_UP support, we need to additionally check the
>> number the cores in Cortex-A9 MPCore configuration. Without
>> such a check in place, the startup code tries to execute
>> ALT_SMP() set of instructions which lead to CPU faults.
>>
>> The issue was spotted on TI's Aegis device and this patch
>> makes now the device work with omap2plus_defconfig which
>> enables SMP by default. The change is kept limited to only
>> Cortex-A9 MPCore detection code.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>>
>> Acked-by: Sricharan R <r.sricharan@ti.com>
>> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> ---
>>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>>  1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index 9cf6063..4924b11 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
>> @@ -486,7 +486,23 @@ __fixup_smp:
>>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
>> -	moveq	pc, lr			@ yes, assume SMP
>> +	bne    __fixup_smp_on_up	@ no, assume UP
>> +
>> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
>> +	@ Cortex-A9 CPU is present but SMP operations fault.
>> +	mov	r4, #0x41000000
>> +	orr	r4, r4, #0x0000c000
>> +	orr	r4, r4, #0x00000090
>> +	teq	r3, r4			@ Check for ARM Cortex-A9
>> +	movne	pc, lr			@ Not ARM Cortex-A9,
>> +
>> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
>> +	teq	r0, #0x0		@ '0' on actual UP A9 hardware
>> +	beq	__fixup_smp_on_up	@ So its an A9 UP
> 
> What if somebody builds an MP A9 with the private peripheral base address at
> 0x0?
> 
Good point though we at least haven't seen one yet on the kernel lists.
Any other way to avoid A9 UP case proceeding to the actual address 0
read which might be anything on a SOC.

Regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Dave Martin]

On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
> 
> The generic code is well equipped to differentiate between
> SMP and UP configurations.However, there are some devices which
> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
> the SMP_ON_UP support, we need to additionally check the
> number the cores in Cortex-A9 MPCore configuration. Without
> such a check in place, the startup code tries to execute
> ALT_SMP() set of instructions which lead to CPU faults.
> 
> The issue was spotted on TI's Aegis device and this patch
> makes now the device work with omap2plus_defconfig which
> enables SMP by default. The change is kept limited to only
> Cortex-A9 MPCore detection code.

Is there a specific reason why this can't happen for other processors
such as A5/7/15?

Cheers
---Dave

> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> 
> Acked-by: Sricharan R <r.sricharan@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 9cf6063..4924b11 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -486,7 +486,23 @@ __fixup_smp:
>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
> -	moveq	pc, lr			@ yes, assume SMP
> +	bne    __fixup_smp_on_up	@ no, assume UP
> +
> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
> +	@ Cortex-A9 CPU is present but SMP operations fault.
> +	mov	r4, #0x41000000
> +	orr	r4, r4, #0x0000c000
> +	orr	r4, r4, #0x00000090
> +	teq	r3, r4			@ Check for ARM Cortex-A9
> +	movne	pc, lr			@ Not ARM Cortex-A9,
> +
> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
> +	teq	r0, #0x0		@ '0' on actual UP A9 hardware
> +	beq	__fixup_smp_on_up	@ So its an A9 UP
> +	ldr	r0, [r0, #4]		@ read SCU Config
> +	and	r0, r0, #0x3		@ number of CPUs
> +	teq	r0, #0x0		@ is 1?
> +	movne	pc, lr
>  
>  __fixup_smp_on_up:
>  	adr	r0, 1f
> -- 
> 1.7.9.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Friday 02 August 2013 10:18 AM, Dave Martin wrote:
> On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
>> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>
>> The generic code is well equipped to differentiate between
>> SMP and UP configurations.However, there are some devices which
>> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
>> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
>> the SMP_ON_UP support, we need to additionally check the
>> number the cores in Cortex-A9 MPCore configuration. Without
>> such a check in place, the startup code tries to execute
>> ALT_SMP() set of instructions which lead to CPU faults.
>>
>> The issue was spotted on TI's Aegis device and this patch
>> makes now the device work with omap2plus_defconfig which
>> enables SMP by default. The change is kept limited to only
>> Cortex-A9 MPCore detection code.
> 
> Is there a specific reason why this can't happen for other processors
> such as A5/7/15?
> 
The basic reason behind limiting to A9 was the SCU carrying
the no. of CPU information is specific to A9. A7/A15 have
that information encoded in L2 control register. Since
same code won't work for the other ARM versions and we
don't wanted to pollute the code much without need of it
those versions are not considered.

Regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Sudeep KarkadaNagesha]

On 01/08/13 19:17, Santosh Shilimkar wrote:
> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
> 
> The generic code is well equipped to differentiate between
> SMP and UP configurations.However, there are some devices which
> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
> the SMP_ON_UP support, we need to additionally check the
> number the cores in Cortex-A9 MPCore configuration. Without
> such a check in place, the startup code tries to execute
> ALT_SMP() set of instructions which lead to CPU faults.
> 
> The issue was spotted on TI's Aegis device and this patch
> makes now the device work with omap2plus_defconfig which
> enables SMP by default. The change is kept limited to only
> Cortex-A9 MPCore detection code.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> 
> Acked-by: Sricharan R <r.sricharan@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 9cf6063..4924b11 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -486,7 +486,23 @@ __fixup_smp:
>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
> -	moveq	pc, lr			@ yes, assume SMP
> +	bne    __fixup_smp_on_up	@ no, assume UP
> +
> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
> +	@ Cortex-A9 CPU is present but SMP operations fault.
> +	mov	r4, #0x41000000
> +	orr	r4, r4, #0x0000c000
> +	orr	r4, r4, #0x00000090
> +	teq	r3, r4			@ Check for ARM Cortex-A9
> +	movne	pc, lr			@ Not ARM Cortex-A9,
> +
> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
Correct me if I am interpreting this wrong, but CRn=15 here which is
IMPLEMENTATION DEFINED registers.

If not, then I wonder why few platform have to read SCU base from DT or
some header, why not this way ?

Regards,
Sudeep

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
> On 01/08/13 19:17, Santosh Shilimkar wrote:
>> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>
>> The generic code is well equipped to differentiate between
>> SMP and UP configurations.However, there are some devices which
>> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
>> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
>> the SMP_ON_UP support, we need to additionally check the
>> number the cores in Cortex-A9 MPCore configuration. Without
>> such a check in place, the startup code tries to execute
>> ALT_SMP() set of instructions which lead to CPU faults.
>>
>> The issue was spotted on TI's Aegis device and this patch
>> makes now the device work with omap2plus_defconfig which
>> enables SMP by default. The change is kept limited to only
>> Cortex-A9 MPCore detection code.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>>
>> Acked-by: Sricharan R <r.sricharan@ti.com>
>> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> ---
>>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>>  1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index 9cf6063..4924b11 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
>> @@ -486,7 +486,23 @@ __fixup_smp:
>>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
>> -	moveq	pc, lr			@ yes, assume SMP
>> +	bne    __fixup_smp_on_up	@ no, assume UP
>> +
>> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
>> +	@ Cortex-A9 CPU is present but SMP operations fault.
>> +	mov	r4, #0x41000000
>> +	orr	r4, r4, #0x0000c000
>> +	orr	r4, r4, #0x00000090
>> +	teq	r3, r4			@ Check for ARM Cortex-A9
>> +	movne	pc, lr			@ Not ARM Cortex-A9,
>> +
>> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
> Correct me if I am interpreting this wrong, but CRn=15 here which is
> IMPLEMENTATION DEFINED registers.
>
> If not, then I wonder why few platform have to read SCU base from DT or
> some header, why not this way ?
> 
I don't know if there is Cortex-A9 based SOC which don't implement SCU
CP15 base address register, so can't comment really why not always use
CP15 based method. I am not even sure if there are other reasons behind
DT usage.

Regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Sudeep KarkadaNagesha]

On 02/08/13 16:22, Santosh Shilimkar wrote:
> On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
>> On 01/08/13 19:17, Santosh Shilimkar wrote:
>>> From: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>>
>>> The generic code is well equipped to differentiate between
>>> SMP and UP configurations.However, there are some devices which
>>> use Cortex-A9 MP core IP with 1 CPU as configuration. To let
>>> these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
>>> the SMP_ON_UP support, we need to additionally check the
>>> number the cores in Cortex-A9 MPCore configuration. Without
>>> such a check in place, the startup code tries to execute
>>> ALT_SMP() set of instructions which lead to CPU faults.
>>>
>>> The issue was spotted on TI's Aegis device and this patch
>>> makes now the device work with omap2plus_defconfig which
>>> enables SMP by default. The change is kept limited to only
>>> Cortex-A9 MPCore detection code.
>>>
>>> Cc: Will Deacon <will.deacon@arm.com>
>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>
>>> Acked-by: Sricharan R <r.sricharan@ti.com>
>>> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> ---
>>>  arch/arm/kernel/head.S |   18 +++++++++++++++++-
>>>  1 file changed, 17 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>>> index 9cf6063..4924b11 100644
>>> --- a/arch/arm/kernel/head.S
>>> +++ b/arch/arm/kernel/head.S
>>> @@ -486,7 +486,23 @@ __fixup_smp:
>>>  	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
>>>  	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
>>>  	teq	r0, #0x80000000		@ not part of a uniprocessor system?
>>> -	moveq	pc, lr			@ yes, assume SMP
>>> +	bne    __fixup_smp_on_up	@ no, assume UP
>>> +
>>> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
>>> +	@ Cortex-A9 CPU is present but SMP operations fault.
>>> +	mov	r4, #0x41000000
>>> +	orr	r4, r4, #0x0000c000
>>> +	orr	r4, r4, #0x00000090
>>> +	teq	r3, r4			@ Check for ARM Cortex-A9
>>> +	movne	pc, lr			@ Not ARM Cortex-A9,
>>> +
>>> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
>> Correct me if I am interpreting this wrong, but CRn=15 here which is
>> IMPLEMENTATION DEFINED registers.
>>
>> If not, then I wonder why few platform have to read SCU base from DT or
>> some header, why not this way ?
>>
> I don't know if there is Cortex-A9 based SOC which don't implement SCU
> CP15 base address register, so can't comment really why not always use
> CP15 based method. I am not even sure if there are other reasons behind
> DT usage.
> 
I may be wrong, but it's just my understanding as I see that ARM ARM
clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we
can't expect it to work on all IMPLEMENTATIONS.

I just had a glance at all the usage of CR15 space of CP15 register, its
either platform specific or under specific errata/condition.

Will/Dave/Russell can confirm if it's safe to access these registers on
any implementation or you may need to make it conditional.

Regards,
Sudeep

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Will Deacon]

On Fri, Aug 02, 2013 at 04:45:46PM +0100, Sudeep KarkadaNagesha wrote:
> On 02/08/13 16:22, Santosh Shilimkar wrote:
> >>> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
> >>> +	@ Cortex-A9 CPU is present but SMP operations fault.
> >>> +	mov	r4, #0x41000000
> >>> +	orr	r4, r4, #0x0000c000
> >>> +	orr	r4, r4, #0x00000090
> >>> +	teq	r3, r4			@ Check for ARM Cortex-A9
> >>> +	movne	pc, lr			@ Not ARM Cortex-A9,
> >>> +
> >>> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
> >> Correct me if I am interpreting this wrong, but CRn=15 here which is
> >> IMPLEMENTATION DEFINED registers.
> >>
> >> If not, then I wonder why few platform have to read SCU base from DT or
> >> some header, why not this way ?
> >>
> > I don't know if there is Cortex-A9 based SOC which don't implement SCU
> > CP15 base address register, so can't comment really why not always use
> > CP15 based method. I am not even sure if there are other reasons behind
> > DT usage.
> > 
> I may be wrong, but it's just my understanding as I see that ARM ARM
> clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we
> can't expect it to work on all IMPLEMENTATIONS.
> 
> I just had a glance at all the usage of CR15 space of CP15 register, its
> either platform specific or under specific errata/condition.
> 
> Will/Dave/Russell can confirm if it's safe to access these registers on
> any implementation or you may need to make it conditional.

I think this an A9-specific register, which reads as 0 on UP A9 and reads as
some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
is zero.

Will

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

Will,

On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
> On Fri, Aug 02, 2013 at 04:45:46PM +0100, Sudeep KarkadaNagesha wrote:
>> On 02/08/13 16:22, Santosh Shilimkar wrote:
>>>>> +	@ Core indicates it is SMP.  Check for Aegis SOC where a single
>>>>> +	@ Cortex-A9 CPU is present but SMP operations fault.
>>>>> +	mov	r4, #0x41000000
>>>>> +	orr	r4, r4, #0x0000c000
>>>>> +	orr	r4, r4, #0x00000090
>>>>> +	teq	r3, r4			@ Check for ARM Cortex-A9
>>>>> +	movne	pc, lr			@ Not ARM Cortex-A9,
>>>>> +
>>>>> +	mrc	p15, 4, r0, c15, c0	@ get SCU base address
>>>> Correct me if I am interpreting this wrong, but CRn=15 here which is
>>>> IMPLEMENTATION DEFINED registers.
>>>>
>>>> If not, then I wonder why few platform have to read SCU base from DT or
>>>> some header, why not this way ?
>>>>
>>> I don't know if there is Cortex-A9 based SOC which don't implement SCU
>>> CP15 base address register, so can't comment really why not always use
>>> CP15 based method. I am not even sure if there are other reasons behind
>>> DT usage.
>>>
>> I may be wrong, but it's just my understanding as I see that ARM ARM
>> clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we
>> can't expect it to work on all IMPLEMENTATIONS.
>>
>> I just had a glance at all the usage of CR15 space of CP15 register, its
>> either platform specific or under specific errata/condition.
>>
>> Will/Dave/Russell can confirm if it's safe to access these registers on
>> any implementation or you may need to make it conditional.
> 
> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
> is zero.
> 
What do we do here ? Should we document this in the code and proceed ?
Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
I am open for any other alternative.

Regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Will Deacon]

On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
> > I think this an A9-specific register, which reads as 0 on UP A9 and reads as
> > some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
> > is zero.
> > 
> What do we do here ? Should we document this in the code and proceed ?
> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
> I am open for any other alternative.

The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.

Will

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
>>> is zero.
>>>
>> What do we do here ? Should we document this in the code and proceed ?
>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
>> I am open for any other alternative.
> 
> The only other alternative I can think of is forcing people to have
> CONFIG_SMP=n, but that blows away single zImage for your platform.
> 
Yep which surely we don't want considering after so much effort we
have it working first place. How about going ahead with assumption
that PERIPH_BASE = 0 case doesn't work.

Regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Sekhar Nori]

On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
>>>> is zero.
>>>>
>>> What do we do here ? Should we document this in the code and proceed ?
>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
>>> I am open for any other alternative.
>>
>> The only other alternative I can think of is forcing people to have
>> CONFIG_SMP=n, but that blows away single zImage for your platform.
>>
> Yep which surely we don't want considering after so much effort we
> have it working first place. How about going ahead with assumption
> that PERIPH_BASE = 0 case doesn't work.

I must be missing something but why cannot we use the SCU configuration
register "CPU number" field to determine that its a UP? I do not have an
OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.

Thanks,
Sekhar

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote:
> On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
>> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
>>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
>>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
>>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
>>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
>>>>> is zero.
>>>>>
>>>> What do we do here ? Should we document this in the code and proceed ?
>>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
>>>> I am open for any other alternative.
>>>
>>> The only other alternative I can think of is forcing people to have
>>> CONFIG_SMP=n, but that blows away single zImage for your platform.
>>>
>> Yep which surely we don't want considering after so much effort we
>> have it working first place. How about going ahead with assumption
>> that PERIPH_BASE = 0 case doesn't work.
> 
> I must be missing something but why cannot we use the SCU configuration
> register "CPU number" field to determine that its a UP? I do not have an
> OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.
> 
Thats what patch does. Yes, you are missing the point of dicussion. 
On real UP Cortex-A9, the base address read will return '0' which is
treated as invalid address in the patch. Will D pointed out that one
can build a SOC where PERIPH_BASE can be 0 so thats not safe.
Thats the only contention left here.

Will, Russell,
Am just re-asking the question about whether we can ignore PERIPH_BASE = 0
and just document in the code about the limitation.

regards,
Santosh

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Sekhar Nori]

On 8/23/2013 10:47 PM, Santosh Shilimkar wrote:
> On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote:
>> On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
>>> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
>>>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
>>>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
>>>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
>>>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
>>>>>> is zero.
>>>>>>
>>>>> What do we do here ? Should we document this in the code and proceed ?
>>>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
>>>>> I am open for any other alternative.
>>>>
>>>> The only other alternative I can think of is forcing people to have
>>>> CONFIG_SMP=n, but that blows away single zImage for your platform.
>>>>
>>> Yep which surely we don't want considering after so much effort we
>>> have it working first place. How about going ahead with assumption
>>> that PERIPH_BASE = 0 case doesn't work.
>>
>> I must be missing something but why cannot we use the SCU configuration
>> register "CPU number" field to determine that its a UP? I do not have an
>> OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.
>>
> Thats what patch does. Yes, you are missing the point of dicussion. 

Right, I see that now after actually reading the complete patch :)

> On real UP Cortex-A9, the base address read will return '0' which is
> treated as invalid address in the patch. Will D pointed out that one

Is this something defined by spec for all UP Cortex-A9 or just an
observation on AM437x implementation? It sounds like the later?

Thanks,
Sekhar

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Will Deacon]

Hi Santosh,

On Tue, Aug 13, 2013 at 02:31:04PM +0100, Santosh Shilimkar wrote:
> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
> > On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
> >> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
> >>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
> >>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
> >>> is zero.
> >>>
> >> What do we do here ? Should we document this in the code and proceed ?
> >> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
> >> I am open for any other alternative.
> > 
> > The only other alternative I can think of is forcing people to have
> > CONFIG_SMP=n, but that blows away single zImage for your platform.
> > 
> Yep which surely we don't want considering after so much effort we
> have it working first place. How about going ahead with assumption
> that PERIPH_BASE = 0 case doesn't work.

It's been over a month and I can't think of anything better than this
without jeopardising the single zImage effort. However, it also doesn't seem
fair if we rule out the possibility of single zImage for future SoCs which
use 0x0 as their PERIPH_BASE (I don't know of any at the moment).

So how about we go ahead with this, but add a big fat comment to the code in
head.S saying that, if a future SoC *does* use 0x0 as the PERIPH_BASE, then
the check will need to be #ifdef'd or equivalent for the Aegis platform?

Will

[PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices

[Santosh Shilimkar]

On Tuesday 24 September 2013 01:08 PM, Will Deacon wrote:
> Hi Santosh,
> 
> On Tue, Aug 13, 2013 at 02:31:04PM +0100, Santosh Shilimkar wrote:
>> On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
>>> On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
>>>> On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
>>>>> I think this an A9-specific register, which reads as 0 on UP A9 and reads as
>>>>> some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
>>>>> is zero.
>>>>>
>>>> What do we do here ? Should we document this in the code and proceed ?
>>>> Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but
>>>> I am open for any other alternative.
>>>
>>> The only other alternative I can think of is forcing people to have
>>> CONFIG_SMP=n, but that blows away single zImage for your platform.
>>>
>> Yep which surely we don't want considering after so much effort we
>> have it working first place. How about going ahead with assumption
>> that PERIPH_BASE = 0 case doesn't work.
> 
> It's been over a month and I can't think of anything better than this
> without jeopardising the single zImage effort. However, it also doesn't seem
> fair if we rule out the possibility of single zImage for future SoCs which
> use 0x0 as their PERIPH_BASE (I don't know of any at the moment).
> 
> So how about we go ahead with this, but add a big fat comment to the code in
> head.S saying that, if a future SoC *does* use 0x0 as the PERIPH_BASE, then
> the check will need to be #ifdef'd or equivalent for the Aegis platform?
> 
I agree. Updated patch end of the email. If you are fine with this version,
will stick it into RMK's patch system.

Regards,
Santosh

>From 05b1b43324f3e8d10a38f78dbcbf7632d4c3530c Mon Sep 17 00:00:00 2001
From: Vaibhav Bedia <vaibhav.bedia@ti.com>
Date: Thu, 18 Jul 2013 13:01:53 -0400
Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU
 devices

The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.

The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.

Note that if any future SoC *does* use 0x0 as the PERIPH_BASE, then
the SCU address check code needs to be #ifdef'd for for the Aegis
platform.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>

Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/kernel/head.S |   21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 2c7cc1e..476de57 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -487,7 +487,26 @@ __fixup_smp:
 	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
 	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
 	teq	r0, #0x80000000		@ not part of a uniprocessor system?
-	moveq	pc, lr			@ yes, assume SMP
+	bne    __fixup_smp_on_up	@ no, assume UP
+
+	@ Core indicates it is SMP. Check for Aegis SOC where a single
+	@ Cortex-A9 CPU is present but SMP operations fault.
+	mov	r4, #0x41000000
+	orr	r4, r4, #0x0000c000
+	orr	r4, r4, #0x00000090
+	teq	r3, r4			@ Check for ARM Cortex-A9
+	movne	pc, lr			@ Not ARM Cortex-A9,
+
+	@ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
+	@ below address check will need to be #ifdef'd or equivalent
+	@ for the Aegis platform.
+	mrc	p15, 4, r0, c15, c0	@ get SCU base address
+	teq	r0, #0x0		@ '0' on actual UP A9 hardware
+	beq	__fixup_smp_on_up	@ So its an A9 UP
+	ldr	r0, [r0, #4]		@ read SCU Config
+	and	r0, r0, #0x3		@ number of CPUs
+	teq	r0, #0x0		@ is 1?
+	movne	pc, lr
 
 __fixup_smp_on_up:
 	adr	r0, 1f
-- 
1.7.9.5