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From: liuj97@gmail.com (Jiang Liu)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFT PATCH v1 2/7] arm64: restore FPSIMD to default state for kernel and signal contexts
Date: Fri, 27 Sep 2013 21:20:04 +0800	[thread overview]
Message-ID: <52458604.7030902@gmail.com> (raw)
In-Reply-To: <20130927113507.GC11063@MacBook-Pro.local>

On 09/27/2013 07:35 PM, Catalin Marinas wrote:
> On Fri, Sep 27, 2013 at 09:04:42AM +0100, Jiang Liu wrote:
>> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
>> index bb785d2..12a25e5 100644
>> --- a/arch/arm64/kernel/fpsimd.c
>> +++ b/arch/arm64/kernel/fpsimd.c
>> @@ -80,9 +80,14 @@ void fpsimd_thread_switch(struct task_struct *next)
>>  
>>  void fpsimd_flush_thread(void)
>>  {
>> +	struct fpsimd_state *state = &current->thread.fpsimd_state;
>> +
>>  	preempt_disable();
>> -	memset(&current->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
>> -	fpsimd_load_state(&current->thread.fpsimd_state);
>> +	memset(state, 0, sizeof(struct fpsimd_state));
>> +#if (AARCH64_FPCR_DEFAULT_VAL != 0)
>> +	state->fpcr = AARCH64_FPCR_DEFAULT_VAL;
>> +#endif
>> +	fpsimd_load_state(state);
>>  	preempt_enable();
> 
> We can leave this to 0 as the default for user. Glibc already programs
> this register.
OK, will drop it.

> 
>>  }
>>  
>> @@ -99,6 +104,8 @@ void kernel_neon_begin(void)
>>  
>>  	if (current->mm)
>>  		fpsimd_save_state(&current->thread.fpsimd_state);
>> +
>> +	fpsimd_init_hw_state();
> 
> This function should indeed do some initialisation rather than relying
> on whatever the user set for FPCR.
> 
>> diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
>> index 890a591..6d80612 100644
>> --- a/arch/arm64/kernel/signal.c
>> +++ b/arch/arm64/kernel/signal.c
>> @@ -52,6 +52,7 @@ static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
>>  
>>  	/* dump the hardware registers to the fpsimd_state structure */
>>  	fpsimd_save_state(fpsimd);
>> +	fpsimd_init_hw_state();
> 
> Here I think we need to leave the default user setting for fpcr as
> decided by glibc (or libgcc) when an application starts.
OK, will keep FPCR and clear FPSR.

> 
>>  	/* copy the FP and status/control registers */
>>  	err = __copy_to_user(ctx->vregs, fpsimd->vregs, sizeof(fpsimd->vregs));
>> diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
>> index e393174..cb2cb41 100644
>> --- a/arch/arm64/kernel/signal32.c
>> +++ b/arch/arm64/kernel/signal32.c
>> @@ -248,6 +248,7 @@ static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
>>  	 * in AArch32.
>>  	 */
>>  	fpsimd_save_state(fpsimd);
>> +	fpsimd_init_hw_state();
> 
> Same here.
> 

  reply	other threads:[~2013-09-27 13:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-27  8:04 [RFT PATCH v1 0/7] enable FPSIMD lazy save and restore for arm64 Jiang Liu
2013-09-27  8:04 ` [RFT PATCH v1 1/7] arm64: fix possible invalid FPSIMD initialization state Jiang Liu
2013-09-27 10:59   ` Catalin Marinas
2013-09-27  8:04 ` [RFT PATCH v1 2/7] arm64: restore FPSIMD to default state for kernel and signal contexts Jiang Liu
2013-09-27 11:35   ` Catalin Marinas
2013-09-27 13:20     ` Jiang Liu [this message]
2013-09-27  8:04 ` [RFT PATCH v1 3/7] arm64: implement basic lazy save and restore for FPSIMD registers Jiang Liu
2013-09-27  8:04 ` [RFT PATCH v1 4/7] arm64: provide boot option "eagerfpu" to control FPSIMD restore policy Jiang Liu
2013-09-27  8:04 ` [RFT PATCH v1 5/7] arm64: reuse FPSIMD hardware context if possible Jiang Liu
2013-09-27  8:04 ` [RFT PATCH v1 6/7] amd64: avoid saving and restoring FPSIMD registers until threads access them Jiang Liu
2013-09-27 10:59   ` Will Deacon
2013-09-27 14:20     ` Jiang Liu
2013-09-30  9:34       ` Will Deacon
2013-09-27  8:04 ` [RFT PATCH v1 7/7] arm64: disable lazy load if FPSIMD registers are frequently used Jiang Liu
2013-09-27 10:50 ` [RFT PATCH v1 0/7] enable FPSIMD lazy save and restore for arm64 Catalin Marinas
2013-09-27 11:23   ` Will Deacon
2013-09-27 15:20     ` Jiang Liu
2013-09-27 16:16       ` Catalin Marinas

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