[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Sricharan R]

The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
host OS, as this will be propagated to the guests as well.

More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html

So configuring this secure register for all the cpus here.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
---
 arch/arm/mach-omap2/omap-secure.h |    2 ++
 arch/arm/mach-omap2/omap-smp.c    |    9 +++++++++
 arch/arm/mach-omap2/timer.c       |    6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index a171a5a..4de9a00 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -51,6 +51,8 @@
 
 #define OMAP5_MON_AMBA_IF_INDEX		0x108
 
+#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
+
 /* Secure PPA(Primary Protected Application) APIs */
 #define OMAP4_PPA_L2_POR_INDEX		0x23
 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 98a1146..00873b4 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -41,6 +41,8 @@
 
 u16 pm44xx_errata;
 
+extern unsigned long arch_timer_freq;
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -66,6 +68,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
 							4, 0, 0, 0, 0, 0);
 
 	/*
+	 * Configure the CNTFRQ register for the secondary cpu's which
+	 * indicates the frequency of the cpu local timers.
+	 */
+	if (soc_is_omap54xx() || soc_is_dra7xx())
+		omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
+
+	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index fd9238d..2c499f3 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -55,6 +55,7 @@
 #include "soc.h"
 #include "common.h"
 #include "powerdomain.h"
+#include "omap-secure.h"
 
 #define REALTIME_COUNTER_BASE				0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET			0x10
@@ -65,6 +66,7 @@
 
 static struct omap_dm_timer clkev;
 static struct clock_event_device clockevent_gpt;
+unsigned long arch_timer_freq;
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
@@ -546,7 +548,11 @@ static void __init realtime_counter_init(void)
 	reg |= den;
 	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 
+	arch_timer_freq = (rate / den) * num;
+
 	iounmap(base);
+
+	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
 }
 #else
 static inline void __init realtime_counter_init(void)
-- 
1.7.9.5

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Nishanth Menon]

On 16:53-20130918, Sricharan R wrote:
> The realtime counter called master counter, produces the count
> used by the private timer peripherals in the MPU_CLUSTER. The
> CNTFRQ per cpu register is used to denote the frequency of the counter.
> Currently the frequency value is passed from the
> DT file, but this is not scalable when we have other non-DT guest
> OS. This register must be set to the right value by the
> host OS, as this will be propagated to the guests as well.
> 
> More discussions and the reason for adding this in a non-DT
> way can be seen from below.
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
> 
> So configuring this secure register for all the cpus here.
> 
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>

Tested-by: Nishanth Menon <nm@ti.com>
thanks for a better alternative.

[...]

-- 
Regards,
Nishanth Menon

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Santosh Shilimkar]

On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
> The realtime counter called master counter, produces the count
> used by the private timer peripherals in the MPU_CLUSTER. The
> CNTFRQ per cpu register is used to denote the frequency of the counter.
> Currently the frequency value is passed from the
> DT file, but this is not scalable when we have other non-DT guest
> OS. This register must be set to the right value by the
> host OS, as this will be propagated to the guests as well.
> 
Its not host OS but ROM code/secure code. Host OS is not
ideal place to set it up.

> More discussions and the reason for adding this in a non-DT
> way can be seen from below.
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
> 
> So configuring this secure register for all the cpus here.
> 
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> ---
>  arch/arm/mach-omap2/omap-secure.h |    2 ++
>  arch/arm/mach-omap2/omap-smp.c    |    9 +++++++++
>  arch/arm/mach-omap2/timer.c       |    6 ++++++
>  3 files changed, 17 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
> index a171a5a..4de9a00 100644
> --- a/arch/arm/mach-omap2/omap-secure.h
> +++ b/arch/arm/mach-omap2/omap-secure.h
> @@ -51,6 +51,8 @@
>  
>  #define OMAP5_MON_AMBA_IF_INDEX		0x108
>  
> +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
> +
Nice. Looks like OMAP5 ES2.0 addition which I missed.

>  /* Secure PPA(Primary Protected Application) APIs */
>  #define OMAP4_PPA_L2_POR_INDEX		0x23
>  #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 98a1146..00873b4 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -41,6 +41,8 @@
>  
>  u16 pm44xx_errata;
>  
> +extern unsigned long arch_timer_freq;
> +
>  /* SCU base address */
>  static void __iomem *scu_base;
>  
> @@ -66,6 +68,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
>  							4, 0, 0, 0, 0, 0);
>  
>  	/*
> +	 * Configure the CNTFRQ register for the secondary cpu's which
> +	 * indicates the frequency of the cpu local timers.
> +	 */
> +	if (soc_is_omap54xx() || soc_is_dra7xx())
CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
of the reason this parameter came into picture. So you need to skip
the ES1.0 here. 

> +		omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
> +
> +	/*
>  	 * Synchronise with the boot thread.
>  	 */
>  	spin_lock(&boot_lock);
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index fd9238d..2c499f3 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -55,6 +55,7 @@
>  #include "soc.h"
>  #include "common.h"
>  #include "powerdomain.h"
> +#include "omap-secure.h"
>  
>  #define REALTIME_COUNTER_BASE				0x48243200
>  #define INCREMENTER_NUMERATOR_OFFSET			0x10
> @@ -65,6 +66,7 @@
>  
>  static struct omap_dm_timer clkev;
>  static struct clock_event_device clockevent_gpt;
> +unsigned long arch_timer_freq;
>  
>  static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
>  {
> @@ -546,7 +548,11 @@ static void __init realtime_counter_init(void)
>  	reg |= den;
>  	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
>  
> +	arch_timer_freq = (rate / den) * num;
> +
>  	iounmap(base);
> +
> +	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);

Few problems with this approach..

1. CNTFREQ needs to be programmed on all CPUs. Even though arch-timer
code uses boot-cpu now thats not safe for guest which can start on
secondary CPUs. So please update this in secondary boot path as well.

2. When you power cycle CPU, you will loose the value of this register
so you need to reprogram them on every CPU power up. Both DRA and OMAP5
doesn't support that part yet but do remember to patch that when
such support gets added.

Can you please fix above comments and repost. I will ack that then.

Regards,
Santosh

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Sricharan R]

On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
> On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
>> The realtime counter called master counter, produces the count
>> used by the private timer peripherals in the MPU_CLUSTER. The
>> CNTFRQ per cpu register is used to denote the frequency of the counter.
>> Currently the frequency value is passed from the
>> DT file, but this is not scalable when we have other non-DT guest
>> OS. This register must be set to the right value by the
>> host OS, as this will be propagated to the guests as well.
>>
> Its not host OS but ROM code/secure code. Host OS is not
> ideal place to set it up.
 ok, so you are suggesting to re word this right ?
>> More discussions and the reason for adding this in a non-DT
>> way can be seen from below.
>> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
>>
>> So configuring this secure register for all the cpus here.
>>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Nishanth Menon <nm@ti.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> ---
>>  arch/arm/mach-omap2/omap-secure.h |    2 ++
>>  arch/arm/mach-omap2/omap-smp.c    |    9 +++++++++
>>  arch/arm/mach-omap2/timer.c       |    6 ++++++
>>  3 files changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
>> index a171a5a..4de9a00 100644
>> --- a/arch/arm/mach-omap2/omap-secure.h
>> +++ b/arch/arm/mach-omap2/omap-secure.h
>> @@ -51,6 +51,8 @@
>>  
>>  #define OMAP5_MON_AMBA_IF_INDEX		0x108
>>  
>> +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
>> +
> Nice. Looks like OMAP5 ES2.0 addition which I missed.
>
>>  /* Secure PPA(Primary Protected Application) APIs */
>>  #define OMAP4_PPA_L2_POR_INDEX		0x23
>>  #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
>> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
>> index 98a1146..00873b4 100644
>> --- a/arch/arm/mach-omap2/omap-smp.c
>> +++ b/arch/arm/mach-omap2/omap-smp.c
>> @@ -41,6 +41,8 @@
>>  
>>  u16 pm44xx_errata;
>>  
>> +extern unsigned long arch_timer_freq;
>> +
>>  /* SCU base address */
>>  static void __iomem *scu_base;
>>  
>> @@ -66,6 +68,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
>>  							4, 0, 0, 0, 0, 0);
>>  
>>  	/*
>> +	 * Configure the CNTFRQ register for the secondary cpu's which
>> +	 * indicates the frequency of the cpu local timers.
>> +	 */
>> +	if (soc_is_omap54xx() || soc_is_dra7xx())
> CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
> of the reason this parameter came into picture. So you need to skip
> the ES1.0 here. 
 We do not intend to support ES1.0 right ? . ok then id.c needs to be
 cleaned up to remove ES1.0 traces.
>> +		omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
>> +
>> +	/*
>>  	 * Synchronise with the boot thread.
>>  	 */
>>  	spin_lock(&boot_lock);
>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>> index fd9238d..2c499f3 100644
>> --- a/arch/arm/mach-omap2/timer.c
>> +++ b/arch/arm/mach-omap2/timer.c
>> @@ -55,6 +55,7 @@
>>  #include "soc.h"
>>  #include "common.h"
>>  #include "powerdomain.h"
>> +#include "omap-secure.h"
>>  
>>  #define REALTIME_COUNTER_BASE				0x48243200
>>  #define INCREMENTER_NUMERATOR_OFFSET			0x10
>> @@ -65,6 +66,7 @@
>>  
>>  static struct omap_dm_timer clkev;
>>  static struct clock_event_device clockevent_gpt;
>> +unsigned long arch_timer_freq;
>>  
>>  static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
>>  {
>> @@ -546,7 +548,11 @@ static void __init realtime_counter_init(void)
>>  	reg |= den;
>>  	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
>>  
>> +	arch_timer_freq = (rate / den) * num;
>> +
>>  	iounmap(base);
>> +
>> +	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
> Few problems with this approach..
>
> 1. CNTFREQ needs to be programmed on all CPUs. Even though arch-timer
> code uses boot-cpu now thats not safe for guest which can start on
> secondary CPUs. So please update this in secondary boot path as well.
The patch is doing this for secondary cpu's as well in the
call back  omap4_secondary_init.

> 2. When you power cycle CPU, you will loose the value of this register
> so you need to reprogram them on every CPU power up. Both DRA and OMAP5
> doesn't support that part yet but do remember to patch that when
> such support gets added.
 oh ok. did not realize this. Will add the change for this then.
> Can you please fix above comments and repost. I will ack that then.
>
> Regards,
> Santosh
>
Regards,
 Sricharan

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Santosh Shilimkar]

On Wednesday 18 September 2013 09:44 AM, Sricharan R wrote:
> On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
>> On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
>>> The realtime counter called master counter, produces the count
>>> used by the private timer peripherals in the MPU_CLUSTER. The
>>> CNTFRQ per cpu register is used to denote the frequency of the counter.
>>> Currently the frequency value is passed from the
>>> DT file, but this is not scalable when we have other non-DT guest
>>> OS. This register must be set to the right value by the
>>> host OS, as this will be propagated to the guests as well.
>>>
>> Its not host OS but ROM code/secure code. Host OS is not
>> ideal place to set it up.
>  ok, so you are suggesting to re word this right ?
>>> More discussions and the reason for adding this in a non-DT
>>> way can be seen from below.
>>> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
>>>
>>> So configuring this secure register for all the cpus here.
>>>
>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Cc: Nishanth Menon <nm@ti.com>
>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Tony Lindgren <tony@atomide.com>
>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>>> ---
>>>  arch/arm/mach-omap2/omap-secure.h |    2 ++
>>>  arch/arm/mach-omap2/omap-smp.c    |    9 +++++++++
>>>  arch/arm/mach-omap2/timer.c       |    6 ++++++
>>>  3 files changed, 17 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
>>> index a171a5a..4de9a00 100644
>>> --- a/arch/arm/mach-omap2/omap-secure.h
>>> +++ b/arch/arm/mach-omap2/omap-secure.h
>>> @@ -51,6 +51,8 @@
>>>  
>>>  #define OMAP5_MON_AMBA_IF_INDEX		0x108
>>>  
>>> +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
>>> +
>> Nice. Looks like OMAP5 ES2.0 addition which I missed.
>>
>>>  /* Secure PPA(Primary Protected Application) APIs */
>>>  #define OMAP4_PPA_L2_POR_INDEX		0x23
>>>  #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
>>> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
>>> index 98a1146..00873b4 100644
>>> --- a/arch/arm/mach-omap2/omap-smp.c
>>> +++ b/arch/arm/mach-omap2/omap-smp.c
>>> @@ -41,6 +41,8 @@
>>>  
>>>  u16 pm44xx_errata;
>>>  
>>> +extern unsigned long arch_timer_freq;
>>> +
>>>  /* SCU base address */
>>>  static void __iomem *scu_base;
>>>  
>>> @@ -66,6 +68,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
>>>  							4, 0, 0, 0, 0, 0);
>>>  
>>>  	/*
>>> +	 * Configure the CNTFRQ register for the secondary cpu's which
>>> +	 * indicates the frequency of the cpu local timers.
>>> +	 */
>>> +	if (soc_is_omap54xx() || soc_is_dra7xx())
>> CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
>> of the reason this parameter came into picture. So you need to skip
>> the ES1.0 here. 
>  We do not intend to support ES1.0 right ? . ok then id.c needs to be
>  cleaned up to remove ES1.0 traces.
yes. With clean-up ES1.0, this can stay as is.

>>> +		omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
>>> +
>>> +	/*
>>>  	 * Synchronise with the boot thread.
>>>  	 */
>>>  	spin_lock(&boot_lock);
>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>>> index fd9238d..2c499f3 100644
>>> --- a/arch/arm/mach-omap2/timer.c
>>> +++ b/arch/arm/mach-omap2/timer.c
>>> @@ -55,6 +55,7 @@
>>>  #include "soc.h"
>>>  #include "common.h"
>>>  #include "powerdomain.h"
>>> +#include "omap-secure.h"
>>>  
>>>  #define REALTIME_COUNTER_BASE				0x48243200
>>>  #define INCREMENTER_NUMERATOR_OFFSET			0x10
>>> @@ -65,6 +66,7 @@
>>>  
>>>  static struct omap_dm_timer clkev;
>>>  static struct clock_event_device clockevent_gpt;
>>> +unsigned long arch_timer_freq;
>>>  
>>>  static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
>>>  {
>>> @@ -546,7 +548,11 @@ static void __init realtime_counter_init(void)
>>>  	reg |= den;
>>>  	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
>>>  
>>> +	arch_timer_freq = (rate / den) * num;
>>> +
>>>  	iounmap(base);
>>> +
>>> +	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
>> Few problems with this approach..
>>
>> 1. CNTFREQ needs to be programmed on all CPUs. Even though arch-timer
>> code uses boot-cpu now thats not safe for guest which can start on
>> secondary CPUs. So please update this in secondary boot path as well.
> The patch is doing this for secondary cpu's as well in the
> call back  omap4_secondary_init.
>
NM just pointed out this off-list.

 
>> 2. When you power cycle CPU, you will loose the value of this register
>> so you need to reprogram them on every CPU power up. Both DRA and OMAP5
>> doesn't support that part yet but do remember to patch that when
>> such support gets added.
>  oh ok. did not realize this. Will add the change for this then.
Since PM isn't supported for now, the patch looks alright with ES1.0
support gets dropped. Just fix the change-log.

Feel free to add my ack on updated version.

Regards,
Santosh

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Sricharan R]

On Wednesday 18 September 2013 07:19 PM, Santosh Shilimkar wrote:
> On Wednesday 18 September 2013 09:44 AM, Sricharan R wrote:
>> On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
>>> On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
>>>> The realtime counter called master counter, produces the count
>>>> used by the private timer peripherals in the MPU_CLUSTER. The
>>>> CNTFRQ per cpu register is used to denote the frequency of the counter.
>>>> Currently the frequency value is passed from the
>>>> DT file, but this is not scalable when we have other non-DT guest
>>>> OS. This register must be set to the right value by the
>>>> host OS, as this will be propagated to the guests as well.
>>>>
>>> Its not host OS but ROM code/secure code. Host OS is not
>>> ideal place to set it up.
>>  ok, so you are suggesting to re word this right ?
>>>> More discussions and the reason for adding this in a non-DT
>>>> way can be seen from below.
>>>> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
>>>>
>>>> So configuring this secure register for all the cpus here.
>>>>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Nishanth Menon <nm@ti.com>
>>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>>>> ---
>>>>  arch/arm/mach-omap2/omap-secure.h |    2 ++
>>>>  arch/arm/mach-omap2/omap-smp.c    |    9 +++++++++
>>>>  arch/arm/mach-omap2/timer.c       |    6 ++++++
>>>>  3 files changed, 17 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
>>>> index a171a5a..4de9a00 100644
>>>> --- a/arch/arm/mach-omap2/omap-secure.h
>>>> +++ b/arch/arm/mach-omap2/omap-secure.h
>>>> @@ -51,6 +51,8 @@
>>>>  
>>>>  #define OMAP5_MON_AMBA_IF_INDEX		0x108
>>>>  
>>>> +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
>>>> +
>>> Nice. Looks like OMAP5 ES2.0 addition which I missed.
>>>
>>>>  /* Secure PPA(Primary Protected Application) APIs */
>>>>  #define OMAP4_PPA_L2_POR_INDEX		0x23
>>>>  #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
>>>> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
>>>> index 98a1146..00873b4 100644
>>>> --- a/arch/arm/mach-omap2/omap-smp.c
>>>> +++ b/arch/arm/mach-omap2/omap-smp.c
>>>> @@ -41,6 +41,8 @@
>>>>  
>>>>  u16 pm44xx_errata;
>>>>  
>>>> +extern unsigned long arch_timer_freq;
>>>> +
>>>>  /* SCU base address */
>>>>  static void __iomem *scu_base;
>>>>  
>>>> @@ -66,6 +68,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
>>>>  							4, 0, 0, 0, 0, 0);
>>>>  
>>>>  	/*
>>>> +	 * Configure the CNTFRQ register for the secondary cpu's which
>>>> +	 * indicates the frequency of the cpu local timers.
>>>> +	 */
>>>> +	if (soc_is_omap54xx() || soc_is_dra7xx())
>>> CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
>>> of the reason this parameter came into picture. So you need to skip
>>> the ES1.0 here. 
>>  We do not intend to support ES1.0 right ? . ok then id.c needs to be
>>  cleaned up to remove ES1.0 traces.
> yes. With clean-up ES1.0, this can stay as is.
>
>>>> +		omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
>>>> +
>>>> +	/*
>>>>  	 * Synchronise with the boot thread.
>>>>  	 */
>>>>  	spin_lock(&boot_lock);
>>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>>>> index fd9238d..2c499f3 100644
>>>> --- a/arch/arm/mach-omap2/timer.c
>>>> +++ b/arch/arm/mach-omap2/timer.c
>>>> @@ -55,6 +55,7 @@
>>>>  #include "soc.h"
>>>>  #include "common.h"
>>>>  #include "powerdomain.h"
>>>> +#include "omap-secure.h"
>>>>  
>>>>  #define REALTIME_COUNTER_BASE				0x48243200
>>>>  #define INCREMENTER_NUMERATOR_OFFSET			0x10
>>>> @@ -65,6 +66,7 @@
>>>>  
>>>>  static struct omap_dm_timer clkev;
>>>>  static struct clock_event_device clockevent_gpt;
>>>> +unsigned long arch_timer_freq;
>>>>  
>>>>  static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
>>>>  {
>>>> @@ -546,7 +548,11 @@ static void __init realtime_counter_init(void)
>>>>  	reg |= den;
>>>>  	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
>>>>  
>>>> +	arch_timer_freq = (rate / den) * num;
>>>> +
>>>>  	iounmap(base);
>>>> +
>>>> +	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
>>> Few problems with this approach..
>>>
>>> 1. CNTFREQ needs to be programmed on all CPUs. Even though arch-timer
>>> code uses boot-cpu now thats not safe for guest which can start on
>>> secondary CPUs. So please update this in secondary boot path as well.
>> The patch is doing this for secondary cpu's as well in the
>> call back  omap4_secondary_init.
>>
> NM just pointed out this off-list.
>
>  
>>> 2. When you power cycle CPU, you will loose the value of this register
>>> so you need to reprogram them on every CPU power up. Both DRA and OMAP5
>>> doesn't support that part yet but do remember to patch that when
>>> such support gets added.
>>  oh ok. did not realize this. Will add the change for this then.
> Since PM isn't supported for now, the patch looks alright with ES1.0
> support gets dropped. Just fix the change-log.
>
> Feel free to add my ack on updated version.
 Thanks. Will repost with the updated log and ack.

Regards,
 Sricharan

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Nishanth Menon]

On 09/18/2013 08:31 AM, Santosh Shilimkar wrote:
> On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
[...]
						4, 0, 0, 0, 0, 0);
>>  
>>  	/*
>> +	 * Configure the CNTFRQ register for the secondary cpu's which
>> +	 * indicates the frequency of the cpu local timers.
>> +	 */
>> +	if (soc_is_omap54xx() || soc_is_dra7xx())
> CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
> of the reason this parameter came into picture. So you need to skip
> the ES1.0 here. 
> 
Even though ES1.0 is present in id.c, we have 0 support for ES1.0.

ES1.0 was more or less a test chip, no production devices were
manufactured with it, no public boards (including uevms) are available
to purchase with ES1.0. Further, inside TI, all ES1.0 samples and
boards have been scrapped and replaced with ES2.0 platforms.

In short, no users and dead code in kernel tree. I dont see why we
cant just cleanup OMAP5 ES1.0 entirely from kernel tree?

-- 
Regards,
Nishanth Menon

[PATCH] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Santosh Shilimkar]

On Wednesday 18 September 2013 09:44 AM, Nishanth Menon wrote:
> On 09/18/2013 08:31 AM, Santosh Shilimkar wrote:
>> On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
> [...]
> 						4, 0, 0, 0, 0, 0);
>>>  
>>>  	/*
>>> +	 * Configure the CNTFRQ register for the secondary cpu's which
>>> +	 * indicates the frequency of the cpu local timers.
>>> +	 */
>>> +	if (soc_is_omap54xx() || soc_is_dra7xx())
>> CNTFREQ programming was not supported on OMAP5 ES1.0 and that was one
>> of the reason this parameter came into picture. So you need to skip
>> the ES1.0 here. 
>>
> Even though ES1.0 is present in id.c, we have 0 support for ES1.0.
> 
> ES1.0 was more or less a test chip, no production devices were
> manufactured with it, no public boards (including uevms) are available
> to purchase with ES1.0. Further, inside TI, all ES1.0 samples and
> boards have been scrapped and replaced with ES2.0 platforms.
> 
> In short, no users and dead code in kernel tree. I dont see why we
> cant just cleanup OMAP5 ES1.0 entirely from kernel tree?
> 
Yes...There is no reason to keep broken ES1.0 support. Patch please ;-)

Regards,
Santosh

[PATCH] ARM: OMAP5: id: Remove ES1.0 support

[Nishanth Menon]

OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and platforms are supposed to have been
removed from circulation. Hence, there is no need to further retain
any resemblence of ES1.0 support in id detection code.

Remove the omap_revision handling and BUG() instead to prevent folks
who mistakenly try an older unsupported chip and report bogus errors.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
ref: http://marc.info/?l=linux-omap&m=137951198232339&w=2
based on 3.12-rc1 tag

 arch/arm/mach-omap2/id.c  |    8 ++++----
 arch/arm/mach-omap2/soc.h |    2 --
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0289adc..4f8f1cb 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -576,8 +576,8 @@ void __init omap5xxx_check_revision(void)
 	case 0xb942:
 		switch (rev) {
 		case 0:
-			omap_revision = OMAP5430_REV_ES1_0;
-			break;
+			/* No support for ES1.0 Test chip */
+			BUG();
 		case 1:
 		default:
 			omap_revision = OMAP5430_REV_ES2_0;
@@ -587,8 +587,8 @@ void __init omap5xxx_check_revision(void)
 	case 0xb998:
 		switch (rev) {
 		case 0:
-			omap_revision = OMAP5432_REV_ES1_0;
-			break;
+			/* No support for ES1.0 Test chip */
+			BUG();
 		case 1:
 		default:
 			omap_revision = OMAP5432_REV_ES2_0;
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 4588df1..076bd90 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -455,9 +455,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP4470_REV_ES1_0	(OMAP447X_CLASS | (0x10 << 8))
 
 #define OMAP54XX_CLASS		0x54000054
-#define OMAP5430_REV_ES1_0	(OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
 #define OMAP5430_REV_ES2_0	(OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
-#define OMAP5432_REV_ES1_0	(OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
 #define OMAP5432_REV_ES2_0	(OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
 
 void omap2xxx_check_revision(void);
-- 
1.7.9.5

[PATCH] ARM: OMAP5: id: Remove ES1.0 support

[Santosh Shilimkar]

On Wednesday 18 September 2013 10:05 AM, Nishanth Menon wrote:
> OMAP5 ES1.0 was intended as a test chip and has major register level
> differences w.r.t ES2.0 revision of the chip. All register defines,
> dts support has been solely added for ES2.0 version of the chip.
> Further, all ES1.0 chips and platforms are supposed to have been
> removed from circulation. Hence, there is no need to further retain
> any resemblence of ES1.0 support in id detection code.
> 
> Remove the omap_revision handling and BUG() instead to prevent folks
> who mistakenly try an older unsupported chip and report bogus errors.
> 
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> ref: http://marc.info/?l=linux-omap&m=137951198232339&w=2
> based on 3.12-rc1 tag
> 
That was quick ...
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

[PATCH] ARM: OMAP5: id: Remove ES1.0 support

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [130918 07:15]:
> On Wednesday 18 September 2013 10:05 AM, Nishanth Menon wrote:
> > OMAP5 ES1.0 was intended as a test chip and has major register level
> > differences w.r.t ES2.0 revision of the chip. All register defines,
> > dts support has been solely added for ES2.0 version of the chip.
> > Further, all ES1.0 chips and platforms are supposed to have been
> > removed from circulation. Hence, there is no need to further retain
> > any resemblence of ES1.0 support in id detection code.
> > 
> > Remove the omap_revision handling and BUG() instead to prevent folks
> > who mistakenly try an older unsupported chip and report bogus errors.
> > 
> > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > Signed-off-by: Nishanth Menon <nm@ti.com>
> > ---
> > ref: http://marc.info/?l=linux-omap&m=137951198232339&w=2
> > based on 3.12-rc1 tag
> > 
> That was quick ...
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Heh, it was made, but not supposed to be used, and still merged
to mainline kernel..

I guess this is the way to deal with this issue as we don't have
really any omap5 es1 support in place. So applying into
omap-for-v3.13/soc branch.

Tony

[PATCH] ARM: OMAP5: id: Remove ES1.0 support

[Santosh Shilimkar]

On Tuesday 08 October 2013 05:31 PM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [130918 07:15]:
>> On Wednesday 18 September 2013 10:05 AM, Nishanth Menon wrote:
>>> OMAP5 ES1.0 was intended as a test chip and has major register level
>>> differences w.r.t ES2.0 revision of the chip. All register defines,
>>> dts support has been solely added for ES2.0 version of the chip.
>>> Further, all ES1.0 chips and platforms are supposed to have been
>>> removed from circulation. Hence, there is no need to further retain
>>> any resemblence of ES1.0 support in id detection code.
>>>
>>> Remove the omap_revision handling and BUG() instead to prevent folks
>>> who mistakenly try an older unsupported chip and report bogus errors.
>>>
>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Signed-off-by: Nishanth Menon <nm@ti.com>
>>> ---
>>> ref: http://marc.info/?l=linux-omap&m=137951198232339&w=2
>>> based on 3.12-rc1 tag
>>>
>> That was quick ...
>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> 
> Heh, it was made, but not supposed to be used, and still merged
> to mainline kernel..
> 
You know the history. At least for this silicon we avoided
tons of datafiles merges for ES1.0 which changed completely for
ES2.0. At least during that period people had choice to merge
the data-files based on the board they have to test out ;-)

> I guess this is the way to deal with this issue as we don't have
> really any omap5 es1 support in place. So applying into
> omap-for-v3.13/soc branch.
> 
Thanks !!

Regards,
Santosh