[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Tero Kristo]

Hi,

A small cleanup set for CM. This basically gets rid of the omap2_cm_*
register accesses from the random code locations, and gathers these
under cm2xxx.c and cm3xxx.c. This is done in preparation for creating
a separate CM driver. The set also contains a couple of PRM cleanups
which I decided to take care of at the same time due to overlapping
code (PRCM interrupt handler + DSP reset.)

TODO: cleanup dsp bridge code (arch/arm/mach-omap2/dsp.c.)

Tested on OMAP3 beagle + 3.12-rc3.

If someone could verify the omap2 changes, that would be nice.

-Tero

[PATCH 01/11] ARM: OMAP2: CM/PM: remove direct register accesses outside CM code

[Tero Kristo]

Users of the CM funtionality should not access the CM registers directly
by themselves. Thus, added new CM driver APIs for the OMAP2 specific
functionalities which support the existing direct register accesses, and
changed the platform code to use these. This is done in preparation
for moving the CM code into its own individual driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clkt2xxx_apll.c          |    4 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c      |   11 ++---
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   24 +++------
 arch/arm/mach-omap2/cm2xxx.c                 |   67 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm2xxx.h                 |    8 +++
 arch/arm/mach-omap2/pm24xx.c                 |   24 +--------
 6 files changed, 89 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 25b1fee..c78e893 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
 
 	apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
-	r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+	r = omap2xxx_cm_get_pll_status();
 
 	return ((r & apll_mask) == apll_mask) ? true : false;
 }
@@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void)
 {
 	u32 aplls, srate = 0;
 
-	aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+	aplls = omap2xxx_cm_get_pll_config();
 	aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index d862010..3ff3254 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void)
 
 	core_clk = omap2_get_dpll_rate(dpll_core_ck);
 
-	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-	v &= OMAP24XX_CORE_CLK_SRC_MASK;
+	v = omap2xxx_cm_get_core_clk_src();
 
 	if (v == CORE_CLK_SRC_32K)
 		core_clk = 32768;
@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
 	u32 high, low, core_clk_src;
 
-	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+	core_clk_src = omap2xxx_cm_get_core_clk_src();
 
 	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
 		high = curr_prcm_set->dpll_speed * 2;
@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
 	const struct dpll_data *dd;
 
 	cur_rate = omap2xxx_clk_get_core_rate();
-	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+	mult = omap2xxx_cm_get_core_clk_src();
 
 	if ((rate == (cur_rate / 2)) && (mult == 2)) {
 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
 		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 					   dd->div1_mask);
 		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-		tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+		tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
 		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 		if (rate > low) {
 			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index ae2b35e..b935ed2 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
 			    unsigned long parent_rate)
 {
-	u32 cur_rate, done_rate, bypass = 0, tmp;
+	u32 cur_rate, done_rate, bypass = 0;
 	const struct prcm_config *prcm;
 	unsigned long found_speed = 0;
 	unsigned long flags;
@@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
 		else
 			done_rate = CORE_CLK_SRC_DPLL;
 
-		/* MPU divider */
-		omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
-		/* dsp + iva1 div(2420), iva2.1(2430) */
-		omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
-				 OMAP24XX_DSP_MOD, CM_CLKSEL);
-
-		omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
-		/* Major subsystem dividers */
-		tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-		omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
-				 CM_CLKSEL1);
-
-		if (cpu_is_omap2430())
-			omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
-					 OMAP2430_MDM_MOD, CM_CLKSEL);
+		omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
+					     prcm->cm_clksel_dsp,
+					     prcm->cm_clksel_gfx,
+					     prcm->cm_clksel1_core,
+					     prcm->cm_clksel_mdm);
 
 		/* x2 to enter omap2xxx_sdrc_init_params() */
 		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 6774a53..ce25abb 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -327,6 +327,73 @@ struct clkdm_ops omap2_clkdm_operations = {
 	.clkdm_clk_disable	= omap2xxx_clkdm_clk_disable,
 };
 
+int omap2xxx_cm_fclks_active(void)
+{
+	u32 f1, f2;
+
+	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+
+	return (f1 | f2) ? 1 : 0;
+}
+
+int omap2xxx_cm_mpu_retention_allowed(void)
+{
+	u32 l;
+
+	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
+	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
+		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
+		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
+		return 0;
+	/* Check for UART3. */
+	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+	if (l & OMAP24XX_EN_UART3_MASK)
+		return 0;
+
+	return 1;
+}
+
+u32 omap2xxx_cm_get_core_clk_src(void)
+{
+	u32 v;
+
+	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+	v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+	return v;
+}
+
+u32 omap2xxx_cm_get_core_pll_config(void)
+{
+	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+}
+
+u32 omap2xxx_cm_get_pll_config(void)
+{
+	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+}
+
+u32 omap2xxx_cm_get_pll_status(void)
+{
+	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+}
+
+void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
+{
+	u32 tmp;
+
+	omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
+	omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
+	omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
+	tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
+		OMAP24XX_CLKSEL_DSS2_MASK;
+	omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
+	if (cpu_is_omap2430())
+		omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 4cbb39b..891d81c 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -62,6 +62,14 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
 					 u8 idlest_shift);
 extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
 					s16 *prcm_inst, u8 *idlest_reg_id);
+extern int omap2xxx_cm_fclks_active(void);
+extern int omap2xxx_cm_mpu_retention_allowed(void);
+extern u32 omap2xxx_cm_get_core_clk_src(void);
+extern u32 omap2xxx_cm_get_core_pll_config(void);
+extern u32 omap2xxx_cm_get_pll_config(void);
+extern u32 omap2xxx_cm_get_pll_status(void);
+extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
+					 u32 mdm);
 
 extern int __init omap2xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index ce956b0..8c07594 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -62,16 +62,6 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
 
 static struct clk *osc_ck, *emul_ck;
 
-static int omap2_fclks_active(void)
-{
-	u32 f1, f2;
-
-	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-
-	return (f1 | f2) ? 1 : 0;
-}
-
 static int omap2_enter_full_retention(void)
 {
 	u32 l;
@@ -142,17 +132,7 @@ static int sti_console_enabled;
 
 static int omap2_allow_mpu_retention(void)
 {
-	u32 l;
-
-	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
-	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
-		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
-		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
-		return 0;
-	/* Check for UART3. */
-	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-	if (l & OMAP24XX_EN_UART3_MASK)
+	if (!omap2xxx_cm_mpu_retention_allowed())
 		return 0;
 	if (sti_console_enabled)
 		return 0;
@@ -188,7 +168,7 @@ static void omap2_enter_mpu_retention(void)
 
 static int omap2_can_sleep(void)
 {
-	if (omap2_fclks_active())
+	if (omap2xxx_cm_fclks_active())
 		return 0;
 	if (__clk_is_enabled(osc_ck))
 		return 0;
-- 
1.7.9.5

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Tero Kristo]

Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need to access CM registers directly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c |   38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/clock.h |    2 ++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..c7c5d31 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
 }
 
 /**
+ * omap2_clk_deny_idle - disable autoidle on an OMAP clock
+ * @clk: struct clk * to disable autoidle for
+ *
+ * Disable autoidle on an OMAP clock.
+ */
+int omap2_clk_deny_idle(struct clk *clk)
+{
+	struct clk_hw_omap *c;
+
+	if (__clk_get_flags(clk) & CLK_IS_BASIC)
+		return -EINVAL;
+
+	c = to_clk_hw_omap(__clk_get_hw(clk));
+	if (c->ops && c->ops->deny_idle)
+		c->ops->deny_idle(c);
+	return 0;
+}
+
+/**
+ * omap2_clk_allow_idle - enable autoidle on an OMAP clock
+ * @clk: struct clk * to enable autoidle for
+ *
+ * Enable autoidle on an OMAP clock.
+ */
+int omap2_clk_allow_idle(struct clk *clk)
+{
+	struct clk_hw_omap *c;
+
+	if (__clk_get_flags(clk) & CLK_IS_BASIC)
+		return -EINVAL;
+
+	c = to_clk_hw_omap(__clk_get_hw(clk));
+	if (c->ops && c->ops->allow_idle)
+		c->ops->allow_idle(c);
+	return 0;
+}
+
+/**
  * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
  * @clk_names: ptr to an array of strings of clock names to enable
  * @num_clocks: number of clock names in @clk_names
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..82916cc 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_disable_autoidle_all(void);
+int omap2_clk_allow_idle(struct clk *clk);
+int omap2_clk_deny_idle(struct clk *clk);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
-- 
1.7.9.5

[PATCH 03/11] ARM: OMAP3: McBSP: do not access CM register directly

[Tero Kristo]

McBSP driver require special hacks to enable/disable the autoidle feature
for its interface clock for the proper function of the sidetone hardware.
Currently the driver just writes CM registers directly, which should be
avoided. Thus, changed the driver to use the new deny/allow_autoidle
clock API calls.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/mcbsp.c |   16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 5d87680..b4ac3af 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,6 +25,7 @@
 
 #include "soc.h"
 #include "omap_device.h"
+#include "clock.h"
 
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
@@ -33,22 +34,18 @@
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 
+static struct clk *mcbsp_iclks[5];
+
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
-	unsigned int w;
-
 	/*
 	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
 	 * are enabled or sidetones start sounding ugly.
 	 */
-	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 	if (enable)
-		w &= ~(1 << (id - 2));
+		return omap2_clk_deny_idle(mcbsp_iclks[id]);
 	else
-		w |= 1 << (id - 2);
-	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
-
-	return 0;
+		return omap2_clk_allow_idle(mcbsp_iclks[id]);
 }
 
 static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
@@ -58,6 +55,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	struct omap_hwmod *oh_device[2];
 	struct omap_mcbsp_platform_data *pdata = NULL;
 	struct platform_device *pdev;
+	char clk_name[11];
 
 	sscanf(oh->name, "mcbsp%d", &id);
 
@@ -99,6 +97,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		oh_device[1] = omap_hwmod_lookup((
 		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
 		pdata->enable_st_clock = omap3_enable_st_clock;
+		sprintf(clk_name, "mcbsp%d_ick", id);
+		mcbsp_iclks[id] = clk_get(NULL, clk_name);
 		count++;
 	}
 	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
-- 
1.7.9.5

[PATCH 04/11] ARM: OMAP3: CM/control: move CM scratchpad save to CM driver

[Tero Kristo]

OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
registers within OMAP control module driver. However, as we are separating
CM code into its own driver, this must be moved also. This patch adds a
new API for saving the CM scratchpad contents and uses this from the high
level scratchpad save function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm3xxx.c  |   22 +++++++++++++++++++++
 arch/arm/mach-omap2/cm3xxx.h  |    1 +
 arch/arm/mach-omap2/control.c |   43 ++++-------------------------------------
 3 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 9061c30..f6f0288 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -636,6 +636,28 @@ void omap3_cm_restore_context(void)
 			       OMAP3_CM_CLKOUT_CTRL_OFFSET);
 }
 
+void omap3_cm_save_scratchpad_contents(u32 *ptr)
+{
+	*ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+	*ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+	/*
+	 * As per erratum i671, ROM code does not respect the PER DPLL
+	 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
+	 * Then,  in anycase, clear these bits to avoid extra latencies.
+	 */
+	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
+		~OMAP3430_AUTO_PERIPH_DPLL_MASK;
+	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
+	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
+	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
+	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
+	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
+	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index e8e146f..8224c91 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -83,6 +83,7 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
 
 extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
+extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
 
 extern int __init omap3xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31e0dfe..a597114 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -46,17 +46,7 @@ struct omap3_scratchpad {
 struct omap3_scratchpad_prcm_block {
 	u32 prm_clksrc_ctrl;
 	u32 prm_clksel;
-	u32 cm_clksel_core;
-	u32 cm_clksel_wkup;
-	u32 cm_clken_pll;
-	u32 cm_autoidle_pll;
-	u32 cm_clksel1_pll;
-	u32 cm_clksel2_pll;
-	u32 cm_clksel3_pll;
-	u32 cm_clken_pll_mpu;
-	u32 cm_autoidle_pll_mpu;
-	u32 cm_clksel1_pll_mpu;
-	u32 cm_clksel2_pll_mpu;
+	u32 cm_contents[11];
 	u32 prcm_block_size;
 };
 
@@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void)
 	prcm_block_contents.prm_clksel =
 		omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
 				       OMAP3_PRM_CLKSEL_OFFSET);
-	prcm_block_contents.cm_clksel_core =
-			omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
-	prcm_block_contents.cm_clksel_wkup =
-			omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
-	prcm_block_contents.cm_clken_pll =
-			omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-	/*
-	 * As per erratum i671, ROM code does not respect the PER DPLL
-	 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
-	 * Then,  in anycase, clear these bits to avoid extra latencies.
-	 */
-	prcm_block_contents.cm_autoidle_pll =
-			omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
-			~OMAP3430_AUTO_PERIPH_DPLL_MASK;
-	prcm_block_contents.cm_clksel1_pll =
-			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
-	prcm_block_contents.cm_clksel2_pll =
-			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
-	prcm_block_contents.cm_clksel3_pll =
-			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
-	prcm_block_contents.cm_clken_pll_mpu =
-			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
-	prcm_block_contents.cm_autoidle_pll_mpu =
-			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
-	prcm_block_contents.cm_clksel1_pll_mpu =
-			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
-	prcm_block_contents.cm_clksel2_pll_mpu =
-			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+
+	omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
+
 	prcm_block_contents.prcm_block_size = 0x0;
 
 	/* Populate the SDRC block contents */
-- 
1.7.9.5

[PATCH 05/11] ARM: OMAP3: CM/PM: add API for accessing module clock enable registers

[Tero Kristo]

PRCM chain handler needs these to properly acknowledge wakeup events.
Currently this functionality is implemented as direct register accesses,
but as the CM code should eventually move to its own driver, separate
API calls are now added for this purpose. PM core code is also changed
to use these APIs.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm3xxx.c |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm3xxx.h |    2 ++
 arch/arm/mach-omap2/pm34xx.c |   16 ++++++++--------
 3 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index f6f0288..f13742b 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -658,6 +658,34 @@ void omap3_cm_save_scratchpad_contents(u32 *ptr)
 	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 }
 
+static u32 omap3_cm_access_module_clken(s16 module, u8 regs, bool fck, u32 val,
+					bool write)
+{
+	u16 offset;
+
+	if (fck)
+		offset = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
+	else
+		offset = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
+
+	if (write)
+		omap2_cm_write_mod_reg(val, module, offset);
+	else
+		val = omap2_cm_read_mod_reg(module, offset);
+
+	return val;
+}
+
+u32 omap3_cm_read_module_clken(s16 module, u8 regs, bool fck)
+{
+	return omap3_cm_access_module_clken(module, regs, fck, 0, false);
+}
+
+u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val)
+{
+	return omap3_cm_access_module_clken(module, regs, fck, val, true);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 8224c91..2481781 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -84,6 +84,8 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
 extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
+extern u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val);
+extern u32 omap3_cm_read_module_clken(s16 module, u8 regs, bool fck);
 
 extern int __init omap3xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5a2d803..f3ba439 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -146,8 +146,6 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 {
 	u32 wkst, fclk, iclk, clken;
 	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
-	u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
-	u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 	u16 grpsel_off = (regs == 3) ?
 		OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 	int c = 0;
@@ -156,25 +154,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 	wkst &= ~ignore_bits;
 	if (wkst) {
-		iclk = omap2_cm_read_mod_reg(module, iclk_off);
-		fclk = omap2_cm_read_mod_reg(module, fclk_off);
+		iclk = omap3_cm_read_module_clken(module, regs, false);
+		fclk = omap3_cm_read_module_clken(module, regs, true);
 		while (wkst) {
 			clken = wkst;
-			omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
+			omap3_cm_write_module_clken(module, regs, false,
+						    iclk | clken);
 			/*
 			 * For USBHOST, we don't know whether HOST1 or
 			 * HOST2 woke us up, so enable both f-clocks
 			 */
 			if (module == OMAP3430ES2_USBHOST_MOD)
 				clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-			omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
+			omap3_cm_write_module_clken(module, regs, true,
+						    fclk | clken);
 			omap2_prm_write_mod_reg(wkst, module, wkst_off);
 			wkst = omap2_prm_read_mod_reg(module, wkst_off);
 			wkst &= ~ignore_bits;
 			c++;
 		}
-		omap2_cm_write_mod_reg(iclk, module, iclk_off);
-		omap2_cm_write_mod_reg(fclk, module, fclk_off);
+		omap3_cm_write_module_clken(module, regs, false, iclk);
+		omap3_cm_write_module_clken(module, regs, true, fclk);
 	}
 
 	return c;
-- 
1.7.9.5

[PATCH 06/11] ARM: OMAP3: CM/PM: add API for forcing IVA2 clk enable/disable

[Tero Kristo]

OMAP3 PM code directly writes to CM register space to enable/disable IVA2
clock during boot during the IVA2 reset. Direct access shall be avoided,
thus implement an API call for this, and change the PM core to use this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm3xxx.c |   10 ++++++++++
 arch/arm/mach-omap2/cm3xxx.h |    1 +
 arch/arm/mach-omap2/pm34xx.c |    7 +++----
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index f13742b..55bf939 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -686,6 +686,16 @@ u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val)
 	return omap3_cm_access_module_clken(module, regs, fck, val, true);
 }
 
+void omap3_cm_force_iva_clk(bool enable)
+{
+	u32 val = 0;
+
+	if (enable)
+		val = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK;
+
+	omap2_cm_write_mod_reg(val, OMAP3430_IVA2_MOD, CM_FCLKEN);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 2481781..61fdfc7 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -86,6 +86,7 @@ extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
 extern u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val);
 extern u32 omap3_cm_read_module_clken(s16 module, u8 regs, bool fck);
+extern void omap3_cm_force_iva_clk(bool enable);
 
 extern int __init omap3xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index f3ba439..ede058a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -412,7 +412,7 @@ restore:
 static void __init omap3_iva_idle(void)
 {
 	/* ensure IVA2 clock is disabled */
-	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+	omap3_cm_force_iva_clk(false);
 
 	/* if no clock activity, nothing else to do */
 	if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
@@ -426,8 +426,7 @@ static void __init omap3_iva_idle(void)
 			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
 	/* Enable IVA2 clock */
-	omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
-			 OMAP3430_IVA2_MOD, CM_FCLKEN);
+	omap3_cm_force_iva_clk(true);
 
 	/* Set IVA2 boot mode to 'idle' */
 	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
@@ -437,7 +436,7 @@ static void __init omap3_iva_idle(void)
 	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
 	/* Disable IVA2 clock */
-	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+	omap3_cm_force_iva_clk(false);
 
 	/* Reset IVA2 */
 	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
-- 
1.7.9.5

[PATCH 07/11] ARM: OMAP3: CM/PM: add new API for checking IVA2 idle status

[Tero Kristo]

OMAP3 PM code needs this functionality during the IVA2 reset, but is currently
using direct CM register accesses for this purpose. Implement a new API so
the PM code can use this instead.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm3xxx.c |    6 ++++++
 arch/arm/mach-omap2/cm3xxx.h |    1 +
 arch/arm/mach-omap2/pm34xx.c |    3 +--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 55bf939..b0509b9 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -696,6 +696,12 @@ void omap3_cm_force_iva_clk(bool enable)
 	omap2_cm_write_mod_reg(val, OMAP3430_IVA2_MOD, CM_FCLKEN);
 }
 
+bool omap3_cm_is_iva_active(void)
+{
+	return omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+		OMAP3430_CLKACTIVITY_IVA2_MASK;
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 61fdfc7..a944b5f 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -87,6 +87,7 @@ extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
 extern u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val);
 extern u32 omap3_cm_read_module_clken(s16 module, u8 regs, bool fck);
 extern void omap3_cm_force_iva_clk(bool enable);
+extern bool omap3_cm_is_iva_active(void);
 
 extern int __init omap3xxx_cm_init(void);
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ede058a..a73a012 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -415,8 +415,7 @@ static void __init omap3_iva_idle(void)
 	omap3_cm_force_iva_clk(false);
 
 	/* if no clock activity, nothing else to do */
-	if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
-	      OMAP3430_CLKACTIVITY_IVA2_MASK))
+	if (!omap3_cm_is_iva_active())
 		return;
 
 	/* Reset IVA2 */
-- 
1.7.9.5

[PATCH 08/11] ARM: OMAP3: control: add API for setting IVA bootmode

[Tero Kristo]

OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
a direct register write is used for this. Add a new ctrl API for this purpose
instead.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/control.c |   11 +++++++++++
 arch/arm/mach-omap2/control.h |    1 +
 arch/arm/mach-omap2/pm34xx.c  |    3 +--
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a597114..44bb4d5 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -569,4 +569,15 @@ int omap3_ctrl_save_padconf(void)
 	return 0;
 }
 
+/**
+ * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
+ *
+ * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
+ * force disable IVA2 so that it does not prevent any low-power states.
+ */
+void omap3_ctrl_set_iva_bootmode_idle(void)
+{
+	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
+			 OMAP343X_CONTROL_IVA2_BOOTMOD);
+}
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f7d7c2e..da05480 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -427,6 +427,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
+extern void omap3_ctrl_set_iva_bootmode_idle(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
 				      void __iomem *ctrl_pad);
 #else
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a73a012..a0c7e83 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -428,8 +428,7 @@ static void __init omap3_iva_idle(void)
 	omap3_cm_force_iva_clk(true);
 
 	/* Set IVA2 boot mode to 'idle' */
-	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
-			 OMAP343X_CONTROL_IVA2_BOOTMOD);
+	omap3_ctrl_set_iva_bootmode_idle();
 
 	/* Un-reset IVA2 */
 	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-- 
1.7.9.5

[PATCH 09/11] ARM: OMAP3: PRM: move iva2 force idle functionality to PRM driver

[Tero Kristo]

This is correct location for this instead of the PM core, as it is accessing
PRM registers directly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c  |   48 +----------------------------------------
 arch/arm/mach-omap2/prm3xxx.c |   45 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm3xxx.h |    2 ++
 3 files changed, 48 insertions(+), 47 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a0c7e83..4320541 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -398,51 +398,6 @@ restore:
 
 #endif /* CONFIG_SUSPEND */
 
-
-/**
- * omap3_iva_idle(): ensure IVA is in idle so it can be put into
- *                   retention
- *
- * In cases where IVA2 is activated by bootcode, it may prevent
- * full-chip retention or off-mode because it is not idle.  This
- * function forces the IVA2 into idle state so it can go
- * into retention/off and thus allow full-chip retention/off.
- *
- **/
-static void __init omap3_iva_idle(void)
-{
-	/* ensure IVA2 clock is disabled */
-	omap3_cm_force_iva_clk(false);
-
-	/* if no clock activity, nothing else to do */
-	if (!omap3_cm_is_iva_active())
-		return;
-
-	/* Reset IVA2 */
-	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
-			  OMAP3430_RST2_IVA2_MASK |
-			  OMAP3430_RST3_IVA2_MASK,
-			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-
-	/* Enable IVA2 clock */
-	omap3_cm_force_iva_clk(true);
-
-	/* Set IVA2 boot mode to 'idle' */
-	omap3_ctrl_set_iva_bootmode_idle();
-
-	/* Un-reset IVA2 */
-	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-
-	/* Disable IVA2 clock */
-	omap3_cm_force_iva_clk(false);
-
-	/* Reset IVA2 */
-	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
-			  OMAP3430_RST2_IVA2_MASK |
-			  OMAP3430_RST3_IVA2_MASK,
-			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
-}
-
 static void __init omap3_d2d_idle(void)
 {
 	u16 mask, padconf;
@@ -546,8 +501,7 @@ static void __init prcm_setup_regs(void)
 	/*
 	 * We need to idle iva2_pwrdm even on am3703 with no iva2.
 	 */
-	omap3_iva_idle();
-
+	omap3_prm_force_idle_iva();
 	omap3_d2d_idle();
 }
 
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 7721990..3813e9a 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -26,6 +26,8 @@
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
+#include "cm3xxx.h"
+#include "control.h"
 
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
 	OMAP_PRCM_IRQ("wkup",	0,	0),
@@ -396,6 +398,49 @@ struct pwrdm_ops omap3_pwrdm_operations = {
 	.pwrdm_wait_transition	= omap2_pwrdm_wait_transition,
 };
 
+/**
+ * omap3_prcm_force_idle_iva: ensure IVA is in idle so it can be put into
+ *                           retention
+ *
+ * In cases where IVA2 is activated by bootcode, it may prevent
+ * full-chip retention or off-mode because it is not idle.  This
+ * function forces the IVA2 into idle state so it can go
+ * into retention/off and thus allow full-chip retention/off.
+ */
+void __init omap3_prm_force_idle_iva(void)
+{
+	/* ensure IVA2 clock is disabled */
+	omap3_cm_force_iva_clk(false);
+
+	/* if no clock activity, nothing else to do */
+	if (!omap3_cm_is_iva_active())
+		return;
+
+	/* Reset IVA2 */
+	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+				OMAP3430_RST2_IVA2_MASK |
+				OMAP3430_RST3_IVA2_MASK,
+				OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+
+	/* Enable IVA2 clock */
+	omap3_cm_force_iva_clk(true);
+
+	/* Set IVA2 boot mode to 'idle' */
+	omap3_ctrl_set_iva_bootmode_idle();
+
+	/* Un-reset IVA2 */
+	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+
+	/* Disable IVA2 clock */
+	omap3_cm_force_iva_clk(false);
+
+	/* Reset IVA2 */
+	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+				OMAP3430_RST2_IVA2_MASK |
+				OMAP3430_RST3_IVA2_MASK,
+				OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+}
+
 /*
  *
  */
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 277f717..1befb23 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -154,6 +154,8 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 
 extern void omap3xxx_prm_dpll3_reset(void);
 
+extern void omap3_prm_force_idle_iva(void);
+
 extern int __init omap3xxx_prm_init(void);
 extern u32 omap3xxx_prm_get_reset_sources(void);
 
-- 
1.7.9.5

[PATCH 10/11] ARM: OMAP3: PRM: move PRCM interrupt handler helper to PRM driver

[Tero Kristo]

PM core code should not directly access PRM registers. Thus move the
PRCM interrupt handler helper out of the core PM code to PRM driver,
and use the new API from the core.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c  |   65 ++-------------------------------
 arch/arm/mach-omap2/prm3xxx.c |   79 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm3xxx.h |    2 ++
 3 files changed, 83 insertions(+), 63 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4320541..6a5302a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -132,60 +132,11 @@ static void omap3_save_secure_ram_context(void)
 	}
 }
 
-/*
- * PRCM Interrupt Handler Helper Function
- *
- * The purpose of this function is to clear any wake-up events latched
- * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
- * may occur whilst attempting to clear a PM_WKST_x register and thus
- * set another bit in this register. A while loop is used to ensure
- * that any peripheral wake-up events occurring while attempting to
- * clear the PM_WKST_x are detected and cleared.
- */
-static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
-{
-	u32 wkst, fclk, iclk, clken;
-	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
-	u16 grpsel_off = (regs == 3) ?
-		OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
-	int c = 0;
-
-	wkst = omap2_prm_read_mod_reg(module, wkst_off);
-	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-	wkst &= ~ignore_bits;
-	if (wkst) {
-		iclk = omap3_cm_read_module_clken(module, regs, false);
-		fclk = omap3_cm_read_module_clken(module, regs, true);
-		while (wkst) {
-			clken = wkst;
-			omap3_cm_write_module_clken(module, regs, false,
-						    iclk | clken);
-			/*
-			 * For USBHOST, we don't know whether HOST1 or
-			 * HOST2 woke us up, so enable both f-clocks
-			 */
-			if (module == OMAP3430ES2_USBHOST_MOD)
-				clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-			omap3_cm_write_module_clken(module, regs, true,
-						    fclk | clken);
-			omap2_prm_write_mod_reg(wkst, module, wkst_off);
-			wkst = omap2_prm_read_mod_reg(module, wkst_off);
-			wkst &= ~ignore_bits;
-			c++;
-		}
-		omap3_cm_write_module_clken(module, regs, false, iclk);
-		omap3_cm_write_module_clken(module, regs, true, fclk);
-	}
-
-	return c;
-}
-
 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
 	int c;
 
-	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-		~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
+	c = omap3_prcm_clear_io_irq();
 
 	return c ? IRQ_HANDLED : IRQ_NONE;
 }
@@ -194,19 +145,7 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 {
 	int c;
 
-	/*
-	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
-	 * these are handled in a separate handler to avoid acking
-	 * IO events before parsing in mux code
-	 */
-	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-		OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
-	c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
-	c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
-	if (omap_rev() > OMAP3430_REV_ES1_0) {
-		c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
-		c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
-	}
+	c = omap3_prcm_clear_wkup_irq();
 
 	return c ? IRQ_HANDLED : IRQ_NONE;
 }
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 3813e9a..50177e9 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -27,6 +27,7 @@
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
 #include "cm3xxx.h"
+#include "cm-regbits-34xx.h"
 #include "control.h"
 
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
@@ -399,6 +400,84 @@ struct pwrdm_ops omap3_pwrdm_operations = {
 };
 
 /**
+ * omap3_prcm_clear_mod_irqs: PRCM interrupt handler helper function
+ * @module: module offset
+ * @regs: register index
+ * @ignore_bits: bit-mask to ignore while checking wakeup status
+ *
+ * The purpose of this function is to clear any wake-up events latched
+ * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
+ * may occur whilst attempting to clear a PM_WKST_x register and thus
+ * set another bit in this register. A while loop is used to ensure
+ * that any peripheral wake-up events occurring while attempting to
+ * clear the PM_WKST_x are detected and cleared.
+ */
+static int omap3_prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+{
+	u32 wkst, fclk, iclk, clken;
+	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
+	u16 grpsel_off = (regs == 3) ?
+		OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
+	int c = 0;
+
+	wkst = omap2_prm_read_mod_reg(module, wkst_off);
+	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
+	wkst &= ~ignore_bits;
+	if (wkst) {
+		iclk = omap3_cm_read_module_clken(module, regs, false);
+		fclk = omap3_cm_read_module_clken(module, regs, true);
+		while (wkst) {
+			clken = wkst;
+			omap3_cm_write_module_clken(module, regs, false,
+						    iclk | clken);
+			/*
+			 * For USBHOST, we don't know whether HOST1 or
+			 * HOST2 woke us up, so enable both f-clocks
+			 */
+			if (module == OMAP3430ES2_USBHOST_MOD)
+				clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
+			omap3_cm_write_module_clken(module, regs, true,
+						    fclk | clken);
+			omap2_prm_write_mod_reg(wkst, module, wkst_off);
+			wkst = omap2_prm_read_mod_reg(module, wkst_off);
+			wkst &= ~ignore_bits;
+			c++;
+		}
+		omap3_cm_write_module_clken(module, regs, false, iclk);
+		omap3_cm_write_module_clken(module, regs, true, fclk);
+	}
+
+	return c;
+}
+
+int omap3_prcm_clear_io_irq(void)
+{
+	return omap3_prcm_clear_mod_irqs(WKUP_MOD, 1,
+		~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
+}
+
+int omap3_prcm_clear_wkup_irq(void)
+{
+	int c;
+
+	/*
+	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
+	 * these are handled in a separate handler to avoid acking
+	 * IO events before parsing in mux code
+	 */
+	c = omap3_prcm_clear_mod_irqs(WKUP_MOD, 1,
+		OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
+	c += omap3_prcm_clear_mod_irqs(CORE_MOD, 1, 0);
+	c += omap3_prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+	if (omap_rev() > OMAP3430_REV_ES1_0) {
+		c += omap3_prcm_clear_mod_irqs(CORE_MOD, 3, 0);
+		c += omap3_prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+	}
+
+	return c;
+}
+
+/**
  * omap3_prcm_force_idle_iva: ensure IVA is in idle so it can be put into
  *                           retention
  *
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 1befb23..c7d1616 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -154,6 +154,8 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 
 extern void omap3xxx_prm_dpll3_reset(void);
 
+extern int omap3_prcm_clear_io_irq(void);
+extern int omap3_prcm_clear_wkup_irq(void);
 extern void omap3_prm_force_idle_iva(void);
 
 extern int __init omap3xxx_prm_init(void);
-- 
1.7.9.5

[PATCH 11/11] ARM: OMAP2+: CM: move direct register write macros to internal header

[Tero Kristo]

The direct register access macros should not be exposed to CM clients.
Thus, move the register macros to their own file and only include these
to the cm_*.c files.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cm2xxx.c      |    1 +
 arch/arm/mach-omap2/cm2xxx_3xxx.h |   48 --------------------------
 arch/arm/mach-omap2/cm3xxx.c      |    1 +
 arch/arm/mach-omap2/cm_internal.h |   67 +++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cm_internal.h

diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ce25abb..c7facf1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -26,6 +26,7 @@
 #include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 #include "clockdomain.h"
+#include "cm_internal.h"
 
 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
 #define DPLL_AUTOIDLE_DISABLE				0x0
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index bfbd16f..b40b5bd 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -48,54 +48,6 @@
 
 #ifndef __ASSEMBLER__
 
-#include <linux/io.h>
-
-static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
-{
-	return __raw_readl(cm_base + module + idx);
-}
-
-static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-	__raw_writel(val, cm_base + module + idx);
-}
-
-/* Read-modify-write a register in a CM module. Caller must lock */
-static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
-					    s16 idx)
-{
-	u32 v;
-
-	v = omap2_cm_read_mod_reg(module, idx);
-	v &= ~mask;
-	v |= bits;
-	omap2_cm_write_mod_reg(v, module, idx);
-
-	return v;
-}
-
-/* Read a CM register, AND it, and shift the result down to bit 0 */
-static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-	u32 v;
-
-	v = omap2_cm_read_mod_reg(domain, idx);
-	v &= mask;
-	v >>= __ffs(mask);
-
-	return v;
-}
-
-static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
 extern int omap2xxx_cm_apll54_enable(void);
 extern void omap2xxx_cm_apll54_disable(void);
 extern int omap2xxx_cm_apll96_enable(void);
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index b0509b9..ccd29ba 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -26,6 +26,7 @@
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "clockdomain.h"
+#include "cm_internal.h"
 
 static const u8 omap3xxx_cm_idlest_offs[] = {
 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
diff --git a/arch/arm/mach-omap2/cm_internal.h b/arch/arm/mach-omap2/cm_internal.h
new file mode 100644
index 0000000..929157d
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_internal.h
@@ -0,0 +1,67 @@
+/*
+ * OMAP2+ Clock Management (CM) internal header
+ *
+ * Copyright (C) 2007-2013 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_INTERNAL_H
+#define __ARCH_ARM_MACH_OMAP2_CM_INTERNAL_H
+
+#include <linux/io.h>
+
+static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+	return __raw_readl(cm_base + module + idx);
+}
+
+static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+	__raw_writel(val, cm_base + module + idx);
+}
+
+/* Read-modify-write a register in a CM module. Caller must lock */
+static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
+					    s16 idx)
+{
+	u32 v;
+
+	v = omap2_cm_read_mod_reg(module, idx);
+	v &= ~mask;
+	v |= bits;
+	omap2_cm_write_mod_reg(v, module, idx);
+
+	return v;
+}
+
+/* Read a CM register, AND it, and shift the result down to bit 0 */
+static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+	u32 v;
+
+	v = omap2_cm_read_mod_reg(domain, idx);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+#endif
-- 
1.7.9.5

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [131011 09:24]:
> 
> If someone could verify the omap2 changes, that would be nice.

Seems to boot on my n800 just fine, dmesg below.

Tony


[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.12.0-rc4-00050-gf44928c (tmlind at muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #245 Fri Oct 11 17:03:03 PDT 2013
[    0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d
[    0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: Nokia N800
[    0.000000] Ignoring unrecognised tag 0x414f4d50
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] debug: ignoring loglevel setting.
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 32768
[    0.000000] free_area_init_node: node 0, pgdat c075891c, node_mem_map c0cb9000
[    0.000000]   Normal zone: 256 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 32768 pages, LIFO batch:7
[    0.000000] CPU: All CPU(s) started in SVC mode.
[    0.000000] OMAP2420
[    0.000000] 
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
[    0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel
[    0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Memory: 116864K/131072K available (5069K kernel code, 344K rwdata, 1812K rodata, 271K init, 5489K bss, 14208K reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc8800000 - 0xff000000   ( 872 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc06c06d0   (6882 kB)
[    0.000000]       .init : 0xc06c1000 - 0xc0704ddc   ( 272 kB)
[    0.000000]       .data : 0xc0706000 - 0xc075c200   ( 345 kB)
[    0.000000]        .bss : 0xc075c200 - 0xc0cb8808   (5490 kB)
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz
[    0.000000] OMAP clockevent source: timer1 at 32768 Hz
[    0.000000] omap2_sync32k_clocksource_init: failed to get counter_32k resource
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
[    0.000000] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present.
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.070000] Calibrating delay loop... 217.49 BogoMIPS (lpj=1087488)
[    0.150000] pid_max: default: 32768 minimum: 301
[    0.150000] Security Framework initialized
[    0.160000] Mount-cache hash table entries: 512
[    0.170000] CPU: Testing write buffer coherency: ok
[    0.180000] Setting up static identity map for 0xc04d3518 - 0xc04d3588
[    0.210000] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2
[    0.260000] pinctrl core: initialized pinctrl subsystem
[    0.280000] regulator-dummy: no parameters
[    0.290000] NET: Registered protocol family 16
[    0.300000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.310000] omap-gpmc omap-gpmc: GPMC revision 2.0
[    0.340000] omap_gpio omap_gpio.0: Could not get gpio dbck
[    0.350000] gpiochip_add: registered GPIOs 0 to 31 on device: gpio
[    0.360000] OMAP GPIO hardware version 1.8
[    0.360000] omap_gpio omap_gpio.1: Could not get gpio dbck
[    0.370000] gpiochip_add: registered GPIOs 32 to 63 on device: gpio
[    0.380000] omap_gpio omap_gpio.2: Could not get gpio dbck
[    0.390000] gpiochip_add: registered GPIOs 64 to 95 on device: gpio
[    0.400000] omap_gpio omap_gpio.3: Could not get gpio dbck
[    0.410000] gpiochip_add: registered GPIOs 96 to 127 on device: gpio
[    0.440000] omap_mux_init: Add partition: #1: core, flags: b
[    0.510000]  mmci-omap.0: alias fck already exists
[    0.530000] TUSB 6010
[    0.530000] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
[    0.540000] hw-breakpoint: maximum watchpoint size is 4 bytes.
[    0.590000] OMAP DMA hardware revision 2.0
[    0.600000] Missing cpus node, bailing out
[    0.830000] bio: create slab <bio-0> at 0
[    1.100000] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    1.120000] SCSI subsystem initialized
[    1.130000] usbcore: registered new interface driver usbfs
[    1.140000] usbcore: registered new interface driver hub
[    1.150000] usbcore: registered new device driver usb
[    1.170000] omap_i2c omap_i2c.1: bus 1 rev3.3 at 400 kHz
[    1.180000] omap_i2c omap_i2c.2: bus 2 rev3.3 at 400 kHz
[    1.560000] NET: Registered protocol family 2
[    1.570000] TCP established hash table entries: 1024 (order: 1, 8192 bytes)
[    1.580000] TCP bind hash table entries: 1024 (order: 3, 36864 bytes)
[    1.590000] TCP: Hash tables configured (established 1024 bind 1024)
[    1.600000] TCP: reno registered
[    1.600000] UDP hash table entries: 256 (order: 2, 20480 bytes)
[    1.610000] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[    1.620000] NET: Registered protocol family 1
[    1.630000] RPC: Registered named UNIX socket transport module.
[    1.630000] RPC: Registered udp transport module.
[    1.640000] RPC: Registered tcp transport module.
[    1.640000] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.660000] NetWinder Floating Point Emulator V0.97 (double precision)
[    1.660000] CPU PMU: probing PMU on CPU 0
[    1.670000] hw perfevents: enabled with v6 PMU driver, 3 counters available
[    2.230000] VFS: Disk quotas dquot_6.5.2
[    2.230000] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    2.250000] NFS: Registering the id_resolver key type
[    2.250000] Key type id_resolver registered
[    2.260000] Key type id_legacy registered
[    2.260000] jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
[    2.270000] msgmni has been set to 228
[    2.290000] io scheduler noop registered
[    2.290000] io scheduler deadline registered
[    2.300000] io scheduler cfq registered (default)
[    2.310000] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    2.340000] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[    2.360000] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[    2.370000] omap_uart.2: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2
[    2.380000] console [ttyO2] enabled, bootconsole disabled
[    2.380000] console [ttyO2] enabled, bootconsole disabled
[    2.400000] omap_rng omap_rng: OMAP Random Number Generator ver. 40
[    2.500000] brd: module loaded
[    2.550000] loop: module loaded
[    2.560000] Menelaus rev 2.2
[    2.600000] mtdoops: mtd device (mtddev=name/number) must be supplied
[    2.610000] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz
[    2.620000] OneNAND Manufacturer: Samsung (0xec)
[    2.620000] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48)
[    2.630000] OneNAND version = 0x0011
[    2.630000] Chip support all block unlock
[    2.640000] onenand_wait: controller error! state 15 ctrl 0x0400 intr 0x8000
[    2.650000] Scanning device for bad blocks
[    2.910000] Creating 5 MTD partitions on "omap2-onenand":
[    2.920000] 0x000000000000-0x000000020000 : "bootloader"
[    2.940000] 0x000000020000-0x000000080000 : "config"
[    2.960000] 0x000000080000-0x000000280000 : "kernel"
[    2.970000] 0x000000280000-0x000000680000 : "initfs"
[    2.990000] 0x000000680000-0x000010000000 : "rootfs"
[    3.040000] omap-dma-engine omap-dma-engine: allocating channel for 44
[    3.050000] omap-dma-engine omap-dma-engine: allocating channel for 43
[    3.080000] usbcore: registered new interface driver asix
[    3.090000] usbcore: registered new interface driver ax88179_178a
[    3.100000] usbcore: registered new interface driver cdc_ether
[    3.100000] usbcore: registered new interface driver r815x
[    3.110000] usbcore: registered new interface driver smsc95xx
[    3.120000] usbcore: registered new interface driver net1080
[    3.130000] usbcore: registered new interface driver cdc_subset
[    3.140000] usbcore: registered new interface driver zaurus
[    3.140000] usbcore: registered new interface driver cdc_ncm
[    3.150000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.160000] ehci_hcd: block sizes: qh 64 qtd 96 itd 160 sitd 96
[    3.170000] ehci-omap: OMAP-EHCI Host Controller driver
[    3.180000] usbcore: registered new interface driver cdc_wdm
[    3.180000] usbcore: registered new interface driver usb-storage
[    3.190000] usbcore: registered new interface driver usbtest
[    3.230000] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1
[    3.230000] drivers/usb/musb/tusb6010.c tusb_musb_disable: dma still active
[    3.240000] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn)
[    3.250000] musb-hdrc: MHDRC RTL version 1.400 
[    3.250000] musb-hdrc: setup fifo_mode 4
[    3.260000] musb-hdrc: 28/31 max ep, 16384/16384 memory
[    3.260000] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
[    3.280000] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
[    3.280000] musb-hdrc musb-hdrc.0.auto: supports USB remote wakeup
[    3.300000] usb usb1: default language 0x0409
[    3.300000] usb usb1: udev 1, busnum 1, minor = 0
[    3.310000] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    3.310000] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.320000] usb usb1: Product: MUSB HDRC host driver
[    3.330000] usb usb1: Manufacturer: Linux 3.12.0-rc4-00050-gf44928c musb-hcd
[    3.330000] usb usb1: SerialNumber: musb-hdrc.0.auto
[    3.350000] usb usb1: usb_probe_device
[    3.350000] usb usb1: configuration #1 chosen from 1 choice
[    3.360000] usb usb1: adding 1-0:1.0 (config #1, interface 0)
[    3.370000] hub 1-0:1.0: usb_probe_interface
[    3.370000] hub 1-0:1.0: usb_probe_interface - got id
[    3.380000] hub 1-0:1.0: USB hub found
[    3.380000] hub 1-0:1.0: 1 port detected
[    3.390000] hub 1-0:1.0: standalone hub
[    3.390000] hub 1-0:1.0: individual port power switching
[    3.400000] hub 1-0:1.0: no over-current protection
[    3.400000] hub 1-0:1.0: Single TT
[    3.410000] hub 1-0:1.0: TT requires at most 8 FS bit times (666 ns)
[    3.410000] hub 1-0:1.0: power on to power good time: 10ms
[    3.420000] hub 1-0:1.0: 200mA bus power budget for each child
[    3.430000] hub 1-0:1.0: local power source is good
[    3.440000] hub 1-0:1.0: enabling power on all ports
[    3.440000] drivers/usb/musb/tusb6010.c tusb_musb_enable: dma not reactivated
[    3.470000] udc musb-hdrc.0.auto: registering UDC driver [g_ether]
[    3.480000] using random self ethernet address
[    3.480000] using random host ethernet address
[    3.490000] usb0: HOST MAC b2:a6:82:3d:61:d2
[    3.500000] usb0: MAC ba:a4:f3:92:f4:6a
[    3.500000] using random self ethernet address
[    3.510000] using random host ethernet address
[    3.510000] g_ether gadget: adding config #2 'RNDIS'/c074c92c
[    3.520000] rndis_register: configNr = 0
[    3.520000] g_ether gadget: adding 'rndis'/c7b379c0 to config 'RNDIS'/c074c92c
[    3.530000] rndis_set_param_medium: 0 0
[    3.540000] g_ether gadget: RNDIS: dual speed IN/ep1in OUT/ep1out NOTIFY/ep2in
[    3.540000] g_ether gadget: cfg 2/c074c92c speeds: high full
[    3.550000] g_ether gadget:   interface 0 = rndis/c7b379c0
[    3.560000] g_ether gadget:   interface 1 = rndis/c7b379c0
[    3.560000] g_ether gadget: adding config #1 'CDC Ethernet (EEM)'/c074c8b8
[    3.570000] g_ether gadget: adding 'cdc_eem'/c7b37900 to config 'CDC Ethernet (EEM)'/c074c8b8
[    3.580000] g_ether gadget: CDC Ethernet (EEM): dual speed IN/ep1in OUT/ep1out
[    3.590000] g_ether gadget: cfg 1/c074c8b8 speeds: high full
[    3.590000] g_ether gadget:   interface 0 = cdc_eem/c7b37900
[    3.600000] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[    3.610000] g_ether gadget: g_ether ready
[    3.620000] mousedev: PS/2 mouse device common for all mice
[    3.640000] i2c /dev entries driver
[    3.670000] retu-mfd 3-0001: Retu & Vilma v1.5 found
[    3.690000] input: retu-pwrbutton as /devices/platform/i2c-cbus-gpio.3/i2c-3/3-0001/retu-pwrbutton/input/input0
[    3.710000] Driver for 1-wire Dallas network protocol.
[    3.720000] omap_wdt: OMAP Watchdog Timer Rev 0x11: initial timeout 60 sec
[    3.740000] omap-dma-engine omap-dma-engine: allocating channel for 61
[    3.750000] omap-dma-engine omap-dma-engine: allocating channel for 62
[    3.760000] hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0000
[    3.770000] hub 1-0:1.0: hub_suspend
[    3.770000] usb usb1: bus auto-suspend, wakeup 1
[    3.890000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    3.900000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    3.930000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.930000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.940000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.950000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.970000] usbcore: registered new interface driver usbhid
[    3.980000] usbhid: USB HID core driver
[    3.990000] oprofile: using arm/armv6
[    3.990000] TCP: cubic registered
[    4.000000] Initializing XFRM netlink socket
[    4.000000] NET: Registered protocol family 17
[    4.010000] NET: Registered protocol family 15
[    4.010000] Key type dns_resolver registered
[    4.030000] mux: Failed to setup hwmod io irq -22
[    4.040000] Power Management for OMAP2 initializing
[    4.050000] PRCM revision 1.0
[    4.070000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    4.090000] Waiting for root device /dev/mmcblk0p2...
[    4.110000] mmc0: host does not support reading read-only switch. assuming write-enable.
[    4.120000] mmc0: new SDHC card at address ea4d
[    4.130000] mmcblk0: mmc0:ea4d SU04G 3.79 GiB 
[    4.150000]  mmcblk0: p1 p2
[    4.160000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    4.170000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    4.180000] mmci-omap mmci-omap.0: command timeout (CMD8)
[    4.190000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.190000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.210000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.220000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.230000] mmci-omap mmci-omap.0: command timeout (CMD8)
[    4.320000] mmc1: SD Status: Invalid Allocation Unit size.
[    4.330000] mmc1: host does not support reading read-only switch. assuming write-enable.
[    4.340000] mmc1: new SD card at address e624
[    4.370000] mmcblk1: mmc1:e624 SD128 120 MiB 
[    4.390000]  mmcblk1: p1
[    5.790000] kjournald starting.  Commit interval 5 seconds
[    5.800000] EXT3-fs (mmcblk0p2): warning: maximal mount count reached, running e2fsck is recommended
[    5.960000] EXT3-fs (mmcblk0p2): using internal journal
[    5.970000] EXT3-fs (mmcblk0p2): recovery complete
[    5.980000] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
[    5.990000] VFS: Mounted root (ext3 filesystem) on device 179:2.
[    6.000000] Freeing unused kernel memory: 268K (c06c1000 - c0704000)

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [131011 17:18]:
> * Tero Kristo <t-kristo@ti.com> [131011 09:24]:
> > 
> > If someone could verify the omap2 changes, that would be nice.
> 
> Seems to boot on my n800 just fine, dmesg below.

Sorry that was the log without these patches, still boots
fine with the patches too though. Bootlog with your
patches below, at least now you can diff them after removing
the time stamps :)

Regards,

Tony


[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.12.0-rc4-00061-gb99884a (tmlind at muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #247 Fri Oct 11 17:14:37 PDT 2013
[    0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d
[    0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: Nokia N800
[    0.000000] Ignoring unrecognised tag 0x414f4d50
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] debug: ignoring loglevel setting.
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 32768
[    0.000000] free_area_init_node: node 0, pgdat c075891c, node_mem_map c0cb9000
[    0.000000]   Normal zone: 256 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 32768 pages, LIFO batch:7
[    0.000000] CPU: All CPU(s) started in SVC mode.
[    0.000000] OMAP2420
[    0.000000] 
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
[    0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel
[    0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Memory: 116864K/131072K available (5069K kernel code, 344K rwdata, 1812K rodata, 271K init, 5489K bss, 14208K reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc8800000 - 0xff000000   ( 872 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc06c0700   (6882 kB)
[    0.000000]       .init : 0xc06c1000 - 0xc0704ddc   ( 272 kB)
[    0.000000]       .data : 0xc0706000 - 0xc075c200   ( 345 kB)
[    0.000000]        .bss : 0xc075c200 - 0xc0cb8808   (5490 kB)
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz
[    0.000000] OMAP clockevent source: timer1 at 32768 Hz
[    0.000000] omap2_sync32k_clocksource_init: failed to get counter_32k resource
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
[    0.000000] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present.
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.070000] Calibrating delay loop... 217.49 BogoMIPS (lpj=1087488)
[    0.150000] pid_max: default: 32768 minimum: 301
[    0.150000] Security Framework initialized
[    0.160000] Mount-cache hash table entries: 512
[    0.170000] CPU: Testing write buffer coherency: ok
[    0.180000] Setting up static identity map for 0xc04d3618 - 0xc04d3688
[    0.210000] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2
[    0.260000] pinctrl core: initialized pinctrl subsystem
[    0.280000] regulator-dummy: no parameters
[    0.290000] NET: Registered protocol family 16
[    0.300000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.310000] omap-gpmc omap-gpmc: GPMC revision 2.0
[    0.340000] omap_gpio omap_gpio.0: Could not get gpio dbck
[    0.350000] gpiochip_add: registered GPIOs 0 to 31 on device: gpio
[    0.360000] OMAP GPIO hardware version 1.8
[    0.360000] omap_gpio omap_gpio.1: Could not get gpio dbck
[    0.370000] gpiochip_add: registered GPIOs 32 to 63 on device: gpio
[    0.380000] omap_gpio omap_gpio.2: Could not get gpio dbck
[    0.390000] gpiochip_add: registered GPIOs 64 to 95 on device: gpio
[    0.400000] omap_gpio omap_gpio.3: Could not get gpio dbck
[    0.410000] gpiochip_add: registered GPIOs 96 to 127 on device: gpio
[    0.440000] omap_mux_init: Add partition: #1: core, flags: b
[    0.500000]  mmci-omap.0: alias fck already exists
[    0.530000] TUSB 6010
[    0.530000] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers.
[    0.540000] hw-breakpoint: maximum watchpoint size is 4 bytes.
[    0.590000] OMAP DMA hardware revision 2.0
[    0.600000] Missing cpus node, bailing out
[    0.830000] bio: create slab <bio-0> at 0
[    1.100000] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    1.120000] SCSI subsystem initialized
[    1.130000] usbcore: registered new interface driver usbfs
[    1.140000] usbcore: registered new interface driver hub
[    1.140000] usbcore: registered new device driver usb
[    1.170000] omap_i2c omap_i2c.1: bus 1 rev3.3 at 400 kHz
[    1.180000] omap_i2c omap_i2c.2: bus 2 rev3.3 at 400 kHz
[    1.560000] NET: Registered protocol family 2
[    1.570000] TCP established hash table entries: 1024 (order: 1, 8192 bytes)
[    1.570000] TCP bind hash table entries: 1024 (order: 3, 36864 bytes)
[    1.580000] TCP: Hash tables configured (established 1024 bind 1024)
[    1.590000] TCP: reno registered
[    1.590000] UDP hash table entries: 256 (order: 2, 20480 bytes)
[    1.600000] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[    1.610000] NET: Registered protocol family 1
[    1.620000] RPC: Registered named UNIX socket transport module.
[    1.620000] RPC: Registered udp transport module.
[    1.630000] RPC: Registered tcp transport module.
[    1.630000] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.650000] NetWinder Floating Point Emulator V0.97 (double precision)
[    1.660000] CPU PMU: probing PMU on CPU 0
[    1.660000] hw perfevents: enabled with v6 PMU driver, 3 counters available
[    2.220000] VFS: Disk quotas dquot_6.5.2
[    2.220000] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    2.240000] NFS: Registering the id_resolver key type
[    2.240000] Key type id_resolver registered
[    2.250000] Key type id_legacy registered
[    2.250000] jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
[    2.260000] msgmni has been set to 228
[    2.280000] io scheduler noop registered
[    2.280000] io scheduler deadline registered
[    2.290000] io scheduler cfq registered (default)
[    2.300000] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    2.330000] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[    2.340000] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[    2.360000] omap_uart.2: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2
[    2.370000] console [ttyO2] enabled, bootconsole disabled
[    2.370000] console [ttyO2] enabled, bootconsole disabled
[    2.390000] omap_rng omap_rng: OMAP Random Number Generator ver. 40
[    2.480000] brd: module loaded
[    2.530000] loop: module loaded
[    2.540000] Menelaus rev 2.2
[    2.580000] mtdoops: mtd device (mtddev=name/number) must be supplied
[    2.590000] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz
[    2.600000] OneNAND Manufacturer: Samsung (0xec)
[    2.600000] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48)
[    2.610000] OneNAND version = 0x0011
[    2.610000] Chip support all block unlock
[    2.620000] onenand_wait: controller error! state 15 ctrl 0x0400 intr 0x8000
[    2.630000] Scanning device for bad blocks
[    2.880000] Creating 5 MTD partitions on "omap2-onenand":
[    2.890000] 0x000000000000-0x000000020000 : "bootloader"
[    2.910000] 0x000000020000-0x000000080000 : "config"
[    2.930000] 0x000000080000-0x000000280000 : "kernel"
[    2.940000] 0x000000280000-0x000000680000 : "initfs"
[    2.960000] 0x000000680000-0x000010000000 : "rootfs"
[    3.010000] omap-dma-engine omap-dma-engine: allocating channel for 44
[    3.020000] omap-dma-engine omap-dma-engine: allocating channel for 43
[    3.040000] usbcore: registered new interface driver asix
[    3.050000] usbcore: registered new interface driver ax88179_178a
[    3.060000] usbcore: registered new interface driver cdc_ether
[    3.070000] usbcore: registered new interface driver r815x
[    3.080000] usbcore: registered new interface driver smsc95xx
[    3.080000] usbcore: registered new interface driver net1080
[    3.090000] usbcore: registered new interface driver cdc_subset
[    3.100000] usbcore: registered new interface driver zaurus
[    3.110000] usbcore: registered new interface driver cdc_ncm
[    3.120000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.130000] ehci_hcd: block sizes: qh 64 qtd 96 itd 160 sitd 96
[    3.130000] ehci-omap: OMAP-EHCI Host Controller driver
[    3.140000] usbcore: registered new interface driver cdc_wdm
[    3.150000] usbcore: registered new interface driver usb-storage
[    3.160000] usbcore: registered new interface driver usbtest
[    3.190000] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1
[    3.190000] drivers/usb/musb/tusb6010.c tusb_musb_disable: dma still active
[    3.200000] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn)
[    3.210000] musb-hdrc: MHDRC RTL version 1.400 
[    3.210000] musb-hdrc: setup fifo_mode 4
[    3.220000] musb-hdrc: 28/31 max ep, 16384/16384 memory
[    3.220000] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
[    3.240000] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
[    3.240000] musb-hdrc musb-hdrc.0.auto: supports USB remote wakeup
[    3.260000] usb usb1: default language 0x0409
[    3.260000] usb usb1: udev 1, busnum 1, minor = 0
[    3.270000] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    3.270000] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.280000] usb usb1: Product: MUSB HDRC host driver
[    3.290000] usb usb1: Manufacturer: Linux 3.12.0-rc4-00061-gb99884a musb-hcd
[    3.290000] usb usb1: SerialNumber: musb-hdrc.0.auto
[    3.310000] usb usb1: usb_probe_device
[    3.310000] usb usb1: configuration #1 chosen from 1 choice
[    3.320000] usb usb1: adding 1-0:1.0 (config #1, interface 0)
[    3.330000] hub 1-0:1.0: usb_probe_interface
[    3.330000] hub 1-0:1.0: usb_probe_interface - got id
[    3.340000] hub 1-0:1.0: USB hub found
[    3.340000] hub 1-0:1.0: 1 port detected
[    3.350000] hub 1-0:1.0: standalone hub
[    3.350000] hub 1-0:1.0: individual port power switching
[    3.360000] hub 1-0:1.0: no over-current protection
[    3.360000] hub 1-0:1.0: Single TT
[    3.370000] hub 1-0:1.0: TT requires at most 8 FS bit times (666 ns)
[    3.370000] hub 1-0:1.0: power on to power good time: 10ms
[    3.380000] hub 1-0:1.0: 200mA bus power budget for each child
[    3.390000] hub 1-0:1.0: local power source is good
[    3.400000] hub 1-0:1.0: enabling power on all ports
[    3.400000] drivers/usb/musb/tusb6010.c tusb_musb_enable: dma not reactivated
[    3.430000] udc musb-hdrc.0.auto: registering UDC driver [g_ether]
[    3.440000] using random self ethernet address
[    3.440000] using random host ethernet address
[    3.450000] usb0: HOST MAC 66:06:ef:28:8c:1b
[    3.460000] usb0: MAC ca:88:a1:22:1b:cd
[    3.460000] using random self ethernet address
[    3.470000] using random host ethernet address
[    3.470000] g_ether gadget: adding config #2 'RNDIS'/c074c92c
[    3.480000] rndis_register: configNr = 0
[    3.480000] g_ether gadget: adding 'rndis'/c7b379c0 to config 'RNDIS'/c074c92c
[    3.490000] rndis_set_param_medium: 0 0
[    3.500000] g_ether gadget: RNDIS: dual speed IN/ep1in OUT/ep1out NOTIFY/ep2in
[    3.500000] g_ether gadget: cfg 2/c074c92c speeds: high full
[    3.510000] g_ether gadget:   interface 0 = rndis/c7b379c0
[    3.520000] g_ether gadget:   interface 1 = rndis/c7b379c0
[    3.520000] g_ether gadget: adding config #1 'CDC Ethernet (EEM)'/c074c8b8
[    3.530000] g_ether gadget: adding 'cdc_eem'/c7b37900 to config 'CDC Ethernet (EEM)'/c074c8b8
[    3.540000] g_ether gadget: CDC Ethernet (EEM): dual speed IN/ep1in OUT/ep1out
[    3.550000] g_ether gadget: cfg 1/c074c8b8 speeds: high full
[    3.550000] g_ether gadget:   interface 0 = cdc_eem/c7b37900
[    3.560000] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[    3.570000] g_ether gadget: g_ether ready
[    3.580000] mousedev: PS/2 mouse device common for all mice
[    3.600000] i2c /dev entries driver
[    3.630000] retu-mfd 3-0001: Retu & Vilma v1.5 found
[    3.650000] input: retu-pwrbutton as /devices/platform/i2c-cbus-gpio.3/i2c-3/3-0001/retu-pwrbutton/input/input0
[    3.670000] Driver for 1-wire Dallas network protocol.
[    3.680000] omap_wdt: OMAP Watchdog Timer Rev 0x11: initial timeout 60 sec
[    3.700000] omap-dma-engine omap-dma-engine: allocating channel for 61
[    3.710000] omap-dma-engine omap-dma-engine: allocating channel for 62
[    3.720000] hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0000
[    3.730000] hub 1-0:1.0: hub_suspend
[    3.730000] usb usb1: bus auto-suspend, wakeup 1
[    3.850000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    3.860000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    3.890000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.890000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.900000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.910000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    3.930000] usbcore: registered new interface driver usbhid
[    3.940000] usbhid: USB HID core driver
[    3.950000] oprofile: using arm/armv6
[    3.950000] TCP: cubic registered
[    3.960000] Initializing XFRM netlink socket
[    3.960000] NET: Registered protocol family 17
[    3.970000] NET: Registered protocol family 15
[    3.970000] Key type dns_resolver registered
[    3.990000] mux: Failed to setup hwmod io irq -22
[    4.000000] Power Management for OMAP2 initializing
[    4.010000] PRCM revision 1.0
[    4.030000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    4.050000] Waiting for root device /dev/mmcblk0p2...
[    4.070000] mmc0: host does not support reading read-only switch. assuming write-enable.
[    4.080000] mmc0: new SDHC card at address ea4d
[    4.090000] mmcblk0: mmc0:ea4d SU04G 3.79 GiB 
[    4.110000]  mmcblk0: p1 p2
[    4.120000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    4.130000] mmci-omap mmci-omap.0: command timeout (CMD52)
[    4.140000] mmci-omap mmci-omap.0: command timeout (CMD8)
[    4.140000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.150000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.170000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.180000] mmci-omap mmci-omap.0: command timeout (CMD5)
[    4.200000] mmci-omap mmci-omap.0: command timeout (CMD8)
[    4.200000] kjournald starting.  Commit interval 5 seconds
[    4.210000] EXT3-fs (mmcblk0p2): warning: maximal mount count reached, running e2fsck is recommended
[    4.230000] EXT3-fs (mmcblk0p2): using internal journal
[    4.230000] EXT3-fs (mmcblk0p2): recovery complete
[    4.240000] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
[    4.250000] VFS: Mounted root (ext3 filesystem) on device 179:2.
[    4.260000] Freeing unused kernel memory: 268K (c06c1000 - c0704000)
[    4.330000] mmc1: SD Status: Invalid Allocation Unit size.
[    4.340000] mmc1: host does not support reading read-only switch. assuming write-enable.
[    4.360000] mmc1: new SD card at address e624
[    4.370000] mmcblk1: mmc1:e624 SD128 120 MiB 
[    4.400000]  mmcblk1: p1

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Paul Walmsley]

Hi

On Fri, 11 Oct 2013, Tero Kristo wrote:

> A small cleanup set for CM. This basically gets rid of the omap2_cm_*
> register accesses from the random code locations, and gathers these
> under cm2xxx.c and cm3xxx.c. This is done in preparation for creating
> a separate CM driver. The set also contains a couple of PRM cleanups
> which I decided to take care of at the same time due to overlapping
> code (PRCM interrupt handler + DSP reset.)
> 
> TODO: cleanup dsp bridge code (arch/arm/mach-omap2/dsp.c.)
> 
> Tested on OMAP3 beagle + 3.12-rc3.

Looks like at least one patch has a dependency on your DT clk patches:

Importing patch "clk-ti-add-dt-alias-clock" ... 
error: drivers/clk/ti/Makefile: does not exist in index
error: include/linux/clk/ti.h: does not exist in index
stg import: Diff does not apply cleanly

Tried compiling the rest, but the build broke:

arch/arm/mach-omap2/mcbsp.c: In function 'omap3_enable_st_clock':
arch/arm/mach-omap2/mcbsp.c:46:3: error: implicit declaration of function 'omap2_clk_deny_idle'
arch/arm/mach-omap2/mcbsp.c:48:3: error: implicit declaration of function 'omap2_clk_allow_idle'
make[1]: *** [arch/arm/mach-omap2/mcbsp.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
make: *** Waiting for unfinished jobs....


- Paul

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Tero Kristo]

On 10/12/2013 05:19 AM, Paul Walmsley wrote:
> Hi
>
> On Fri, 11 Oct 2013, Tero Kristo wrote:
>
>> A small cleanup set for CM. This basically gets rid of the omap2_cm_*
>> register accesses from the random code locations, and gathers these
>> under cm2xxx.c and cm3xxx.c. This is done in preparation for creating
>> a separate CM driver. The set also contains a couple of PRM cleanups
>> which I decided to take care of at the same time due to overlapping
>> code (PRCM interrupt handler + DSP reset.)
>>
>> TODO: cleanup dsp bridge code (arch/arm/mach-omap2/dsp.c.)
>>
>> Tested on OMAP3 beagle + 3.12-rc3.
>
> Looks like at least one patch has a dependency on your DT clk patches:
>
> Importing patch "clk-ti-add-dt-alias-clock" ...
> error: drivers/clk/ti/Makefile: does not exist in index
> error: include/linux/clk/ti.h: does not exist in index
> stg import: Diff does not apply cleanly

Hmm what? No it doesn't have any dependency. At most, there could be 
merge conflicts between the two, as this is completely separated set.

-Tero

>
> Tried compiling the rest, but the build broke:
>
> arch/arm/mach-omap2/mcbsp.c: In function 'omap3_enable_st_clock':
> arch/arm/mach-omap2/mcbsp.c:46:3: error: implicit declaration of function 'omap2_clk_deny_idle'
> arch/arm/mach-omap2/mcbsp.c:48:3: error: implicit declaration of function 'omap2_clk_allow_idle'
> make[1]: *** [arch/arm/mach-omap2/mcbsp.o] Error 1
> make: *** [arch/arm/mach-omap2] Error 2
> make: *** Waiting for unfinished jobs....
>
>
> - Paul
>

[PATCH 00/11] ARM: OMAP2+: CM cleanup series

[Paul Walmsley]

Hi

On Sat, 12 Oct 2013, Tero Kristo wrote:

> Hmm what? No it doesn't have any dependency. At most, there could be merge
> conflicts between the two, as this is completely separated set.

Thanks, looks like I accidentally mixed this set with your other one.


- Paul

[PATCH 01/11] ARM: OMAP2: CM/PM: remove direct register accesses outside CM code

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> Users of the CM funtionality should not access the CM registers directly
> by themselves. Thus, added new CM driver APIs for the OMAP2 specific
> functionalities which support the existing direct register accesses, and
> changed the platform code to use these. This is done in preparation
> for moving the CM code into its own individual driver.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Thanks, queued.  Not thrilled about returning register bitfields directly 
from these CM functions, but it's incrementally better than what's there.


- Paul

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> Some drivers require direct access to the autoidle functionality of the
> interface clocks. Added clock APIs for these, so that the drivers do not
> need to access CM registers directly.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Thanks, queued.  Please coordinate with Mike to get 
allow_idle/deny_idle-type interfaces into the Common Clock Framework, so 
these can be replaced with standard CCF-type allow_idle() & deny_idle() 
functions.  That interface should include use-counting so multiple callers 
can use allow_idle() and deny_idle() without stomping on each other.


- Paul

> ---
>  arch/arm/mach-omap2/clock.c |   38 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/clock.h |    2 ++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 0c38ca9..c7c5d31 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
>  }
>  
>  /**
> + * omap2_clk_deny_idle - disable autoidle on an OMAP clock
> + * @clk: struct clk * to disable autoidle for
> + *
> + * Disable autoidle on an OMAP clock.
> + */
> +int omap2_clk_deny_idle(struct clk *clk)
> +{
> +	struct clk_hw_omap *c;
> +
> +	if (__clk_get_flags(clk) & CLK_IS_BASIC)
> +		return -EINVAL;
> +
> +	c = to_clk_hw_omap(__clk_get_hw(clk));
> +	if (c->ops && c->ops->deny_idle)
> +		c->ops->deny_idle(c);
> +	return 0;
> +}
> +
> +/**
> + * omap2_clk_allow_idle - enable autoidle on an OMAP clock
> + * @clk: struct clk * to enable autoidle for
> + *
> + * Enable autoidle on an OMAP clock.
> + */
> +int omap2_clk_allow_idle(struct clk *clk)
> +{
> +	struct clk_hw_omap *c;
> +
> +	if (__clk_get_flags(clk) & CLK_IS_BASIC)
> +		return -EINVAL;
> +
> +	c = to_clk_hw_omap(__clk_get_hw(clk));
> +	if (c->ops && c->ops->allow_idle)
> +		c->ops->allow_idle(c);
> +	return 0;
> +}
> +
> +/**
>   * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
>   * @clk_names: ptr to an array of strings of clock names to enable
>   * @num_clocks: number of clock names in @clk_names
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index 7aa32cd..82916cc 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>  void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>  int omap2_clk_enable_autoidle_all(void);
>  int omap2_clk_disable_autoidle_all(void);
> +int omap2_clk_allow_idle(struct clk *clk);
> +int omap2_clk_deny_idle(struct clk *clk);
>  void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>  int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>  void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
> -- 
> 1.7.9.5
> 


- Paul

[PATCH 03/11] ARM: OMAP3: McBSP: do not access CM register directly

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> McBSP driver require special hacks to enable/disable the autoidle feature
> for its interface clock for the proper function of the sidetone hardware.
> Currently the driver just writes CM registers directly, which should be
> avoided. Thus, changed the driver to use the new deny/allow_autoidle
> clock API calls.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>

Thanks, queued.


- Paul

[PATCH 04/11] ARM: OMAP3: CM/control: move CM scratchpad save to CM driver

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
> registers within OMAP control module driver. However, as we are separating
> CM code into its own driver, this must be moved also. This patch adds a
> new API for saving the CM scratchpad contents and uses this from the high
> level scratchpad save function.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Thanks, queued.


- Paul

[PATCH 08/11] ARM: OMAP3: control: add API for setting IVA bootmode

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
> a direct register write is used for this. Add a new ctrl API for this purpose
> instead.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Thanks, queued.


- Paul

[PATCH 06/11] ARM: OMAP3: CM/PM: add API for forcing IVA2 clk enable/disable

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> OMAP3 PM code directly writes to CM register space to enable/disable IVA2
> clock during boot during the IVA2 reset. Direct access shall be avoided,
> thus implement an API call for this, and change the PM core to use this.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Seems like this type of clock forcing needs to be coordinated with the 
clock framework.  Could you please work with Mike to get a decent 
interface implemented for this?


- Paul

[PATCH 06/11] ARM: OMAP3: CM/PM: add API for forcing IVA2 clk enable/disable

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> OMAP3 PM code directly writes to CM register space to enable/disable IVA2
> clock during boot during the IVA2 reset. Direct access shall be avoided,
> thus implement an API call for this, and change the PM core to use this.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-omap2/cm3xxx.c |   10 ++++++++++
>  arch/arm/mach-omap2/cm3xxx.h |    1 +
>  arch/arm/mach-omap2/pm34xx.c |    7 +++----
>  3 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
> index f13742b..55bf939 100644
> --- a/arch/arm/mach-omap2/cm3xxx.c
> +++ b/arch/arm/mach-omap2/cm3xxx.c
> @@ -686,6 +686,16 @@ u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val)
>  	return omap3_cm_access_module_clken(module, regs, fck, val, true);
>  }
>  
> +void omap3_cm_force_iva_clk(bool enable)
> +{
> +	u32 val = 0;
> +
> +	if (enable)
> +		val = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK;
> +
> +	omap2_cm_write_mod_reg(val, OMAP3430_IVA2_MOD, CM_FCLKEN);
> +}
> +

Please implement this as a generic clockdomain API that can be called for 
any clockdomain.


- Paul

[PATCH 09/11] ARM: OMAP3: PRM: move iva2 force idle functionality to PRM driver

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> This is correct location for this instead of the PM core, as it is accessing
> PRM registers directly.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

This is custom reset code for the IVA2, not specifically PRM code, so it 
should go into a separate arch/arm/mach-omap2/iva2.c file, before it gets 
moved out into drivers/.  (Similar to what's been done for 
mach-omap2/i2c.c and mach-omap2/hdq1w.c, etc.)  Unfortunately, this is 
going to require separate interfaces for all of those direct PRM register 
accesses as well.


- Paul

[PATCH 11/11] ARM: OMAP2+: CM: move direct register write macros to internal header

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> The direct register access macros should not be exposed to CM clients.
> Thus, move the register macros to their own file and only include these
> to the cm_*.c files.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

The basic idea here looks great, obviously we can't merge it yet...

- Paul

[PATCH 05/11] ARM: OMAP3: CM/PM: add API for accessing module clock enable registers

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> PRCM chain handler needs these to properly acknowledge wakeup events.
> Currently this functionality is implemented as direct register accesses,
> but as the CM code should eventually move to its own driver, separate
> API calls are now added for this purpose. PM core code is also changed
> to use these APIs.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

In theory, shouldn't the clock code know which clocks are enabled and 
disabled?  Seems like if it can use standard CCF code for this, this code 
might also be able to avoid slow PRM/CM register accesses.  
That prcm_clear_mod_irqs() function should probably be a hwmod-based 
interface anyway...


- Paul

[PATCH 07/11] ARM: OMAP3: CM/PM: add new API for checking IVA2 idle status

[Paul Walmsley]

On Fri, 11 Oct 2013, Tero Kristo wrote:

> OMAP3 PM code needs this functionality during the IVA2 reset, but is currently
> using direct CM register accesses for this purpose. Implement a new API so
> the PM code can use this instead.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-omap2/cm3xxx.c |    6 ++++++
>  arch/arm/mach-omap2/cm3xxx.h |    1 +
>  arch/arm/mach-omap2/pm34xx.c |    3 +--
>  3 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
> index 55bf939..b0509b9 100644
> --- a/arch/arm/mach-omap2/cm3xxx.c
> +++ b/arch/arm/mach-omap2/cm3xxx.c
> @@ -696,6 +696,12 @@ void omap3_cm_force_iva_clk(bool enable)
>  	omap2_cm_write_mod_reg(val, OMAP3430_IVA2_MOD, CM_FCLKEN);
>  }
>  
> +bool omap3_cm_is_iva_active(void)
> +{
> +	return omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
> +		OMAP3430_CLKACTIVITY_IVA2_MASK;
> +}
> +

Please implement this as a generic clockdomain API that can be called for 
any clockdomain.



- Paul

[PATCH 06/11] ARM: OMAP3: CM/PM: add API for forcing IVA2 clk enable/disable

[Paul Walmsley]

On Sat, 19 Oct 2013, Paul Walmsley wrote:

> On Fri, 11 Oct 2013, Tero Kristo wrote:
> 
> > OMAP3 PM code directly writes to CM register space to enable/disable IVA2
> > clock during boot during the IVA2 reset. Direct access shall be avoided,
> > thus implement an API call for this, and change the PM core to use this.
> > 
> > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > ---
> >  arch/arm/mach-omap2/cm3xxx.c |   10 ++++++++++
> >  arch/arm/mach-omap2/cm3xxx.h |    1 +
> >  arch/arm/mach-omap2/pm34xx.c |    7 +++----
> >  3 files changed, 14 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
> > index f13742b..55bf939 100644
> > --- a/arch/arm/mach-omap2/cm3xxx.c
> > +++ b/arch/arm/mach-omap2/cm3xxx.c
> > @@ -686,6 +686,16 @@ u32 omap3_cm_write_module_clken(s16 module, u8 regs, bool fck, u32 val)
> >  	return omap3_cm_access_module_clken(module, regs, fck, val, true);
> >  }
> >  
> > +void omap3_cm_force_iva_clk(bool enable)
> > +{
> > +	u32 val = 0;
> > +
> > +	if (enable)
> > +		val = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK;
> > +
> > +	omap2_cm_write_mod_reg(val, OMAP3430_IVA2_MOD, CM_FCLKEN);
> > +}
> > +
> 
> Please implement this as a generic clockdomain API that can be called for 
> any clockdomain.

Oops, please ignore this comment for this patch; it was intended to be in 
regards to the CLKSTST-reading patch, & have responded appropriately to 
that patch.


- Paul

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Mike Turquette]

Quoting Paul Walmsley (2013-10-19 10:16:50)
> On Fri, 11 Oct 2013, Tero Kristo wrote:
> 
> > Some drivers require direct access to the autoidle functionality of the
> > interface clocks. Added clock APIs for these, so that the drivers do not
> > need to access CM registers directly.
> > 
> > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> 
> Thanks, queued.  Please coordinate with Mike to get 
> allow_idle/deny_idle-type interfaces into the Common Clock Framework, so 
> these can be replaced with standard CCF-type allow_idle() & deny_idle() 
> functions.  That interface should include use-counting so multiple callers 
> can use allow_idle() and deny_idle() without stomping on each other.

Where and when are these functions called? IIRC these are only accessed
at boot/init time, though I may be wrong. If they are a boot-time thing
then the .init callback provided in struct clk may be sufficient.

Regards,
Mike

> 
> 
> - Paul
> 
> > ---
> >  arch/arm/mach-omap2/clock.c |   38 ++++++++++++++++++++++++++++++++++++++
> >  arch/arm/mach-omap2/clock.h |    2 ++
> >  2 files changed, 40 insertions(+)
> > 
> > diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> > index 0c38ca9..c7c5d31 100644
> > --- a/arch/arm/mach-omap2/clock.c
> > +++ b/arch/arm/mach-omap2/clock.c
> > @@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
> >  }
> >  
> >  /**
> > + * omap2_clk_deny_idle - disable autoidle on an OMAP clock
> > + * @clk: struct clk * to disable autoidle for
> > + *
> > + * Disable autoidle on an OMAP clock.
> > + */
> > +int omap2_clk_deny_idle(struct clk *clk)
> > +{
> > +     struct clk_hw_omap *c;
> > +
> > +     if (__clk_get_flags(clk) & CLK_IS_BASIC)
> > +             return -EINVAL;
> > +
> > +     c = to_clk_hw_omap(__clk_get_hw(clk));
> > +     if (c->ops && c->ops->deny_idle)
> > +             c->ops->deny_idle(c);
> > +     return 0;
> > +}
> > +
> > +/**
> > + * omap2_clk_allow_idle - enable autoidle on an OMAP clock
> > + * @clk: struct clk * to enable autoidle for
> > + *
> > + * Enable autoidle on an OMAP clock.
> > + */
> > +int omap2_clk_allow_idle(struct clk *clk)
> > +{
> > +     struct clk_hw_omap *c;
> > +
> > +     if (__clk_get_flags(clk) & CLK_IS_BASIC)
> > +             return -EINVAL;
> > +
> > +     c = to_clk_hw_omap(__clk_get_hw(clk));
> > +     if (c->ops && c->ops->allow_idle)
> > +             c->ops->allow_idle(c);
> > +     return 0;
> > +}
> > +
> > +/**
> >   * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
> >   * @clk_names: ptr to an array of strings of clock names to enable
> >   * @num_clocks: number of clock names in @clk_names
> > diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> > index 7aa32cd..82916cc 100644
> > --- a/arch/arm/mach-omap2/clock.h
> > +++ b/arch/arm/mach-omap2/clock.h
> > @@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
> >  void omap2_init_clk_hw_omap_clocks(struct clk *clk);
> >  int omap2_clk_enable_autoidle_all(void);
> >  int omap2_clk_disable_autoidle_all(void);
> > +int omap2_clk_allow_idle(struct clk *clk);
> > +int omap2_clk_deny_idle(struct clk *clk);
> >  void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
> >  int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
> >  void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
> > -- 
> > 1.7.9.5
> > 
> 
> 
> - Paul

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Paul Walmsley]

On Mon, 21 Oct 2013, Mike Turquette wrote:

> Quoting Paul Walmsley (2013-10-19 10:16:50)
> > On Fri, 11 Oct 2013, Tero Kristo wrote:
> > 
> > > Some drivers require direct access to the autoidle functionality of the
> > > interface clocks. Added clock APIs for these, so that the drivers do not
> > > need to access CM registers directly.
> > > 
> > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > 
> > Thanks, queued.  Please coordinate with Mike to get 
> > allow_idle/deny_idle-type interfaces into the Common Clock Framework, so 
> > these can be replaced with standard CCF-type allow_idle() & deny_idle() 
> > functions.  That interface should include use-counting so multiple callers 
> > can use allow_idle() and deny_idle() without stomping on each other.
> 
> Where and when are these functions called? IIRC these are only accessed
> at boot/init time, though I may be wrong. If they are a boot-time thing
> then the .init callback provided in struct clk may be sufficient.

They are called dynamically at runtime when the McBSP goes active and 
inactive.  It's in the next patch in this series.  I'm fairly sure at 
least one other IP block needs this workaround also.

- Paul

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Rajendra Nayak]

On Monday 21 October 2013 05:56 PM, Mike Turquette wrote:
> Quoting Paul Walmsley (2013-10-19 10:16:50)
>> On Fri, 11 Oct 2013, Tero Kristo wrote:
>>
>>> Some drivers require direct access to the autoidle functionality of the
>>> interface clocks. Added clock APIs for these, so that the drivers do not
>>> need to access CM registers directly.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>
>> Thanks, queued.  Please coordinate with Mike to get 
>> allow_idle/deny_idle-type interfaces into the Common Clock Framework, so 
>> these can be replaced with standard CCF-type allow_idle() & deny_idle() 
>> functions.  That interface should include use-counting so multiple callers 
>> can use allow_idle() and deny_idle() without stomping on each other.
> 
> Where and when are these functions called? IIRC these are only accessed
> at boot/init time, though I may be wrong. If they are a boot-time thing
> then the .init callback provided in struct clk may be sufficient.

deny_idle() gets called early during clock init to disable all hardware
level idling (during boot) and allow_idle() is called during late init
(after PM init) to allow hardware idling.

> 
> Regards,
> Mike
> 
>>
>>
>> - Paul
>>
>>> ---
>>>  arch/arm/mach-omap2/clock.c |   38 ++++++++++++++++++++++++++++++++++++++
>>>  arch/arm/mach-omap2/clock.h |    2 ++
>>>  2 files changed, 40 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>> index 0c38ca9..c7c5d31 100644
>>> --- a/arch/arm/mach-omap2/clock.c
>>> +++ b/arch/arm/mach-omap2/clock.c
>>> @@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
>>>  }
>>>  
>>>  /**
>>> + * omap2_clk_deny_idle - disable autoidle on an OMAP clock
>>> + * @clk: struct clk * to disable autoidle for
>>> + *
>>> + * Disable autoidle on an OMAP clock.
>>> + */
>>> +int omap2_clk_deny_idle(struct clk *clk)
>>> +{
>>> +     struct clk_hw_omap *c;
>>> +
>>> +     if (__clk_get_flags(clk) & CLK_IS_BASIC)
>>> +             return -EINVAL;
>>> +
>>> +     c = to_clk_hw_omap(__clk_get_hw(clk));
>>> +     if (c->ops && c->ops->deny_idle)
>>> +             c->ops->deny_idle(c);
>>> +     return 0;
>>> +}
>>> +
>>> +/**
>>> + * omap2_clk_allow_idle - enable autoidle on an OMAP clock
>>> + * @clk: struct clk * to enable autoidle for
>>> + *
>>> + * Enable autoidle on an OMAP clock.
>>> + */
>>> +int omap2_clk_allow_idle(struct clk *clk)
>>> +{
>>> +     struct clk_hw_omap *c;
>>> +
>>> +     if (__clk_get_flags(clk) & CLK_IS_BASIC)
>>> +             return -EINVAL;
>>> +
>>> +     c = to_clk_hw_omap(__clk_get_hw(clk));
>>> +     if (c->ops && c->ops->allow_idle)
>>> +             c->ops->allow_idle(c);
>>> +     return 0;
>>> +}
>>> +
>>> +/**
>>>   * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
>>>   * @clk_names: ptr to an array of strings of clock names to enable
>>>   * @num_clocks: number of clock names in @clk_names
>>> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
>>> index 7aa32cd..82916cc 100644
>>> --- a/arch/arm/mach-omap2/clock.h
>>> +++ b/arch/arm/mach-omap2/clock.h
>>> @@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>>>  void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>>>  int omap2_clk_enable_autoidle_all(void);
>>>  int omap2_clk_disable_autoidle_all(void);
>>> +int omap2_clk_allow_idle(struct clk *clk);
>>> +int omap2_clk_deny_idle(struct clk *clk);
>>>  void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>>>  int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>>>  void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>>> -- 
>>> 1.7.9.5
>>>
>>
>>
>> - Paul
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH 02/11] ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock

[Paul Walmsley]

On Mon, 21 Oct 2013, Paul Walmsley wrote:

> On Mon, 21 Oct 2013, Mike Turquette wrote:
> 
> > Quoting Paul Walmsley (2013-10-19 10:16:50)
> > > On Fri, 11 Oct 2013, Tero Kristo wrote:
> > > 
> > > > Some drivers require direct access to the autoidle functionality of the
> > > > interface clocks. Added clock APIs for these, so that the drivers do not
> > > > need to access CM registers directly.
> > > > 
> > > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > 
> > > Thanks, queued.  Please coordinate with Mike to get 
> > > allow_idle/deny_idle-type interfaces into the Common Clock Framework, so 
> > > these can be replaced with standard CCF-type allow_idle() & deny_idle() 
> > > functions.  That interface should include use-counting so multiple callers 
> > > can use allow_idle() and deny_idle() without stomping on each other.
> > 
> > Where and when are these functions called? IIRC these are only accessed
> > at boot/init time, though I may be wrong. If they are a boot-time thing
> > then the .init callback provided in struct clk may be sufficient.
> 
> They are called dynamically at runtime when the McBSP goes active and 
> inactive.  It's in the next patch in this series.  I'm fairly sure at 
> least one other IP block needs this workaround also.

By the way, here's that patch:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg97004.html

- Paul