[RFC PATCH 0/4] Big Endian support for ARM64 kernel

[RFC PATCH 0/4] Big Endian support for ARM64 kernel

[Ankit Jindal]

This patchset adds support for using Big Endian mode of AArch64 CPUs

All patches have been tested on APM X-Gene Storm SOC.

The Big Endian toolchain used for development can be found at:
http://cbuild.validation.linaro.org/snapshots/big_endian

We have tested both 32bit BE and 64bit BE root filesystems with these
patches.

The 64bit BE root filesystem was build manually using busybox-1.21.1 and
above mentioned toolchain.

The 32bit BE root filesystem was readily available from Linaro releases
located at: http://snapshots.linaro.org/openembedded/images

Ankit Jindal (4):
  ARM64: Add Kconfig option to enable Big Endian kernel
  ARM64: Include appropriate byteorder for Big Endian
  ARM64: Big Endian fixes for kernel booting
  ARM64: Support for 32-bit big endian userspace

 arch/arm64/Kconfig                      |    2 ++
 arch/arm64/Makefile                     |    7 +++++++
 arch/arm64/include/asm/assembler.h      |    7 +++++++
 arch/arm64/include/asm/processor.h      |    3 +++
 arch/arm64/include/uapi/asm/byteorder.h |    4 ++++
 arch/arm64/kernel/head.S                |   34 +++++++++++++++++++++++++++++++
 arch/arm64/kernel/setup.c               |   19 +++++++++++++----
 arch/arm64/kernel/signal32.c            |    4 ++++
 arch/arm64/kernel/smp_spin_table.c      |    5 +++--
 arch/arm64/mm/Kconfig                   |    7 +++++++
 arch/arm64/mm/proc.S                    |    2 +-
 11 files changed, 87 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm64/mm/Kconfig

-- 
1.7.9.5

[RFC PATCH 1/4] ARM64: Add Kconfig option to enable Big Endian kernel

[Ankit Jindal]

This patch adds Kconfig options and relevant Big Endian compiler flags.

Signed-off-by: Ankit Jindal <ankit.jindal@linaro.org>
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
---
 arch/arm64/Kconfig    |    2 ++
 arch/arm64/Makefile   |    7 +++++++
 arch/arm64/mm/Kconfig |    7 +++++++
 3 files changed, 16 insertions(+)
 create mode 100644 arch/arm64/mm/Kconfig

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f558058..2214ab9 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -285,6 +285,8 @@ config SYSVIPC_COMPAT
 
 endmenu
 
+source "arch/arm64/mm/Kconfig"
+
 source "net/Kconfig"
 
 source "drivers/Kconfig"
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index d90cf79..c92b0f9 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -20,9 +20,16 @@ LIBGCC 		:= $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
 KBUILD_DEFCONFIG := defconfig
 
 KBUILD_CFLAGS	+= -mgeneral-regs-only
+
+ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
+KBUILD_CPPFLAGS += -mbig-endian
+AS              += -EB
+LD              += -EB
+else
 KBUILD_CPPFLAGS	+= -mlittle-endian
 AS		+= -EL
 LD		+= -EL
+endif
 
 comma = ,
 
diff --git a/arch/arm64/mm/Kconfig b/arch/arm64/mm/Kconfig
new file mode 100644
index 0000000..e4122ac
--- /dev/null
+++ b/arch/arm64/mm/Kconfig
@@ -0,0 +1,7 @@
+config CPU_BIG_ENDIAN
+        bool "Build big-endian kernel"
+        help
+          Say Y if you plan on running a kernel in big-endian mode.
+          Note that your board must be properly built and your board
+          port must properly enable any big-endian related features
+          of your chipset/board/processor.
-- 
1.7.9.5

[RFC PATCH 2/4] ARM64: Include appropriate byteorder for Big Endian

[Ankit Jindal]

Use generic big_endian.h when using big endian compiler.

Signed-off-by: Ankit Jindal <ankit.jindal@linaro.org>
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
---
 arch/arm64/include/uapi/asm/byteorder.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/include/uapi/asm/byteorder.h b/arch/arm64/include/uapi/asm/byteorder.h
index 2b92046..dc19e95 100644
--- a/arch/arm64/include/uapi/asm/byteorder.h
+++ b/arch/arm64/include/uapi/asm/byteorder.h
@@ -16,6 +16,10 @@
 #ifndef __ASM_BYTEORDER_H
 #define __ASM_BYTEORDER_H
 
+#ifdef __AARCH64EB__
+#include <linux/byteorder/big_endian.h>
+#else
 #include <linux/byteorder/little_endian.h>
+#endif
 
 #endif	/* __ASM_BYTEORDER_H */
-- 
1.7.9.5

[RFC PATCH 3/4] ARM64: Big Endian fixes for kernel booting

[Ankit Jindal]

- Enable appropriate bits for big endian kernel in SYSCTLR.EL2 and
  SYSCTLR.EL1 registers
- Swap entry point for secondary core for big endian kernel
- Set machine type to "aarch64b" for big endian and "aarch64l"
  for little endian.

Signed-off-by: Ankit Jindal <ankit.jindal@linaro.org>
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
---
 arch/arm64/include/asm/assembler.h |    7 +++++++
 arch/arm64/kernel/head.S           |   34 ++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/setup.c          |   19 +++++++++++++++----
 arch/arm64/kernel/smp_spin_table.c |    5 +++--
 arch/arm64/mm/proc.S               |    2 +-
 5 files changed, 60 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 5aceb83..473faf3 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -22,6 +22,13 @@
 
 #include <asm/ptrace.h>
 
+/* Select code for any configuration running in BE mode */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ARM_BE(code...) code
+#else
+#define ARM_BE(code...)
+#endif
+
 /*
  * Stack pushing/popping (register pairs only). Equivalent to store decrement
  * before, load increment after.
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7090c12..45dc50d 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -122,6 +122,7 @@
 	.word	0				// reserved
 
 ENTRY(stext)
+	ARM_BE(bl      setend_be)
 	mov	x21, x0				// x21=FDT
 	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
 	bl	el2_setup			// Drop to EL1
@@ -148,6 +149,34 @@ ENTRY(stext)
 ENDPROC(stext)
 
 /*
+ * Set el0-el1-el2 to Big endian
+ */
+
+#if defined(CONFIG_CPU_BIG_ENDIAN)
+ENTRY(setend_be)
+	mrs     x21, CurrentEL
+        cmp     x21, #PSR_MODE_EL2t
+	b.ne  	setend_be_el1_el0
+
+setend_be_el2:
+	mrs     x21, sctlr_el2
+        mov     x22, #(1<<25)
+        orr     x21, x21, x22
+        msr     sctlr_el2, x21
+	isb
+
+setend_be_el1_el0:
+	mrs     x21, sctlr_el1
+        mov     x22, #(3<<24)
+        orr     x21, x21, x22
+        msr     sctlr_el1, x21
+	isb
+
+	ret
+ENDPROC(setend_be)
+#endif /* defined(CONFIG_CPU_BIG_ENDIAN) */
+
+/*
  * If we're fortunate enough to boot@EL2, ensure that the world is
  * sane before dropping to EL1.
  */
@@ -181,7 +210,11 @@ ENTRY(el2_setup)
 
 	/* sctlr_el1 */
 	mov	x0, #0x0800			// Set/clear RES{1,0} bits
+#if defined(CONFIG_CPU_BIG_ENDIAN)
+	movk	x0, #0x33d0, lsl #16
+#else
 	movk	x0, #0x30d0, lsl #16
+#endif
 	msr	sctlr_el1, x0
 
 	/* Coprocessor traps. */
@@ -235,6 +268,7 @@ ENTRY(__boot_cpu_mode)
 	 * cores are held until we're ready for them to initialise.
 	 */
 ENTRY(secondary_holding_pen)
+	ARM_BE(bl 	setend_be)
 	bl	__calc_phys_offset		// x24=phys offset
 	bl	el2_setup			// Drop to EL1
 	mrs	x0, mpidr_el1
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 055cfb8..d47ae6d 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -64,6 +64,9 @@ static const char *cpu_name;
 static const char *machine_name;
 phys_addr_t __fdt_pointer __initdata;
 
+static union { char c[8]; unsigned long l; } endian_test = { { 'l', '?', '?',  '?', '?', '?', '?','b' } };
+#define ENDIANNESS ((char)endian_test.l)
+
 /*
  * Standard memory resources
  */
@@ -117,8 +120,10 @@ static void __init setup_processor(void)
 
 	printk("CPU: %s [%08x] revision %d\n",
 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
-
-	sprintf(init_utsname()->machine, "aarch64");
+	
+	snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
+                 "aarch64", ENDIANNESS);
+	
 	elf_hwcap = 0;
 }
 
@@ -310,9 +315,15 @@ static const char *hwcap_str[] = {
 static int c_show(struct seq_file *m, void *v)
 {
 	int i;
+#if 0
+	int num = 1;
+	char c;
+	char *cptr = (char *)&num;
+	c = (*cptr) ? 'l' : 'b';
+#endif
 
-	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
+	seq_printf(m, "Processor\t: %s rev %d (%s%c)\n",
+		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM, ENDIANNESS);
 
 	for_each_online_cpu(i) {
 		/*
diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c
index 7c35fa6..7ad68bc 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -46,9 +46,10 @@ static int __init smp_spin_table_prepare_cpu(int cpu)
 
 	if (!cpu_release_addr[cpu])
 		return -ENODEV;
-
+	
 	release_addr = __va(cpu_release_addr[cpu]);
-	release_addr[0] = (void *)__pa(secondary_holding_pen);
+	release_addr[0] = (void *)cpu_to_le64(__pa(secondary_holding_pen));	
+
 	__flush_dcache_area(release_addr, sizeof(release_addr[0]));
 
 	/*
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index b1b31bb..380a707 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -166,5 +166,5 @@ ENDPROC(__cpu_setup)
 	 */
 	.type	crval, #object
 crval:
-	.word	0x030802e2			// clear
+	.word	0x000802e2			// clear
 	.word	0x0405d11d			// set
-- 
1.7.9.5

[RFC PATCH 4/4] ARM64: Support for 32-bit big endian userspace

[Ankit Jindal]

Set PSTATE.E for compatible binaries when using 64-bit BE kernel

Signed-off-by: Ankit Jindal <ankit.jindal@linaro.org>
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
---
 arch/arm64/include/asm/processor.h |    3 +++
 arch/arm64/kernel/signal32.c       |    4 ++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index ab239b2..d72f5c0 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -107,6 +107,9 @@ static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
 	regs->pstate = COMPAT_PSR_MODE_USR;
 	if (pc & 1)
 		regs->pstate |= COMPAT_PSR_T_BIT;
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	regs->pstate |= COMPAT_PSR_E_BIT;
+#endif
 	regs->compat_sp = sp;
 }
 #endif
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index e393174..8f5b72e 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -481,6 +481,10 @@ static void compat_setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 		spsr &= ~COMPAT_PSR_T_BIT;
 	}
 
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	spsr |= COMPAT_PSR_E_BIT;
+#endif
+
 	if (ka->sa.sa_flags & SA_RESTORER) {
 		retcode = ptr_to_compat(ka->sa.sa_restorer);
 	} else {
-- 
1.7.9.5

[RFC PATCH 3/4] ARM64: Big Endian fixes for kernel booting

[Ankit Jindal]

On 11 October 2013 17:52, Ankit Jindal <ankit.jindal@linaro.org> wrote:
>
> - Enable appropriate bits for big endian kernel in SYSCTLR.EL2 and
>   SYSCTLR.EL1 registers
> - Swap entry point for secondary core for big endian kernel
> - Set machine type to "aarch64b" for big endian and "aarch64l"
>   for little endian.
>
> Signed-off-by: Ankit Jindal <ankit.jindal@linaro.org>
> Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
> ---
>  arch/arm64/include/asm/assembler.h |    7 +++++++
>  arch/arm64/kernel/head.S           |   34 ++++++++++++++++++++++++++++++++++
>  arch/arm64/kernel/setup.c          |   19 +++++++++++++++----
>  arch/arm64/kernel/smp_spin_table.c |    5 +++--
>  arch/arm64/mm/proc.S               |    2 +-
>  5 files changed, 60 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index 5aceb83..473faf3 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -22,6 +22,13 @@
>
>  #include <asm/ptrace.h>
>
> +/* Select code for any configuration running in BE mode */
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +#define ARM_BE(code...) code
> +#else
> +#define ARM_BE(code...)
> +#endif
> +
>  /*
>   * Stack pushing/popping (register pairs only). Equivalent to store decrement
>   * before, load increment after.
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 7090c12..45dc50d 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -122,6 +122,7 @@
>         .word   0                               // reserved
>
>  ENTRY(stext)
> +       ARM_BE(bl      setend_be)
>         mov     x21, x0                         // x21=FDT
>         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
>         bl      el2_setup                       // Drop to EL1
> @@ -148,6 +149,34 @@ ENTRY(stext)
>  ENDPROC(stext)
>
>  /*
> + * Set el0-el1-el2 to Big endian
> + */
> +
> +#if defined(CONFIG_CPU_BIG_ENDIAN)
> +ENTRY(setend_be)
> +       mrs     x21, CurrentEL
> +        cmp     x21, #PSR_MODE_EL2t
> +       b.ne    setend_be_el1_el0
> +
> +setend_be_el2:
> +       mrs     x21, sctlr_el2
> +        mov     x22, #(1<<25)
> +        orr     x21, x21, x22
> +        msr     sctlr_el2, x21
> +       isb
> +
> +setend_be_el1_el0:
> +       mrs     x21, sctlr_el1
> +        mov     x22, #(3<<24)
> +        orr     x21, x21, x22
> +        msr     sctlr_el1, x21
> +       isb
> +
> +       ret
> +ENDPROC(setend_be)
> +#endif /* defined(CONFIG_CPU_BIG_ENDIAN) */
> +
> +/*
>   * If we're fortunate enough to boot at EL2, ensure that the world is
>   * sane before dropping to EL1.
>   */
> @@ -181,7 +210,11 @@ ENTRY(el2_setup)
>
>         /* sctlr_el1 */
>         mov     x0, #0x0800                     // Set/clear RES{1,0} bits
> +#if defined(CONFIG_CPU_BIG_ENDIAN)
> +       movk    x0, #0x33d0, lsl #16
> +#else
>         movk    x0, #0x30d0, lsl #16
> +#endif
>         msr     sctlr_el1, x0
>
>         /* Coprocessor traps. */
> @@ -235,6 +268,7 @@ ENTRY(__boot_cpu_mode)
>          * cores are held until we're ready for them to initialise.
>          */
>  ENTRY(secondary_holding_pen)
> +       ARM_BE(bl       setend_be)
>         bl      __calc_phys_offset              // x24=phys offset
>         bl      el2_setup                       // Drop to EL1
>         mrs     x0, mpidr_el1
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index 055cfb8..d47ae6d 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -64,6 +64,9 @@ static const char *cpu_name;
>  static const char *machine_name;
>  phys_addr_t __fdt_pointer __initdata;
>
> +static union { char c[8]; unsigned long l; } endian_test = { { 'l', '?', '?',  '?', '?', '?', '?','b' } };
> +#define ENDIANNESS ((char)endian_test.l)
> +
>  /*
>   * Standard memory resources
>   */
> @@ -117,8 +120,10 @@ static void __init setup_processor(void)
>
>         printk("CPU: %s [%08x] revision %d\n",
>                cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
> -
> -       sprintf(init_utsname()->machine, "aarch64");
> +
> +       snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
> +                 "aarch64", ENDIANNESS);
> +
>         elf_hwcap = 0;
>  }
>
> @@ -310,9 +315,15 @@ static const char *hwcap_str[] = {
>  static int c_show(struct seq_file *m, void *v)
>  {
>         int i;
> +#if 0
> +       int num = 1;
> +       char c;
> +       char *cptr = (char *)&num;
> +       c = (*cptr) ? 'l' : 'b';
> +#endif

Oops, forgot to remove this #if 0. Please ignore this small change.

>
> -       seq_printf(m, "Processor\t: %s rev %d (%s)\n",
> -                  cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
> +       seq_printf(m, "Processor\t: %s rev %d (%s%c)\n",
> +                  cpu_name, read_cpuid_id() & 15, ELF_PLATFORM, ENDIANNESS);
>
>         for_each_online_cpu(i) {
>                 /*
> diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c
> index 7c35fa6..7ad68bc 100644
> --- a/arch/arm64/kernel/smp_spin_table.c
> +++ b/arch/arm64/kernel/smp_spin_table.c
> @@ -46,9 +46,10 @@ static int __init smp_spin_table_prepare_cpu(int cpu)
>
>         if (!cpu_release_addr[cpu])
>                 return -ENODEV;
> -
> +
>         release_addr = __va(cpu_release_addr[cpu]);
> -       release_addr[0] = (void *)__pa(secondary_holding_pen);
> +       release_addr[0] = (void *)cpu_to_le64(__pa(secondary_holding_pen));
> +
>         __flush_dcache_area(release_addr, sizeof(release_addr[0]));
>
>         /*
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index b1b31bb..380a707 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -166,5 +166,5 @@ ENDPROC(__cpu_setup)
>          */
>         .type   crval, #object
>  crval:
> -       .word   0x030802e2                      // clear
> +       .word   0x000802e2                      // clear
>         .word   0x0405d11d                      // set
> --
> 1.7.9.5
>

[RFC PATCH 1/4] ARM64: Add Kconfig option to enable Big Endian kernel

[Christopher Covington]

Hi Ankit,

On 10/11/2013 08:22 AM, Ankit Jindal wrote:
> This patch adds Kconfig options and relevant Big Endian compiler flags.
[...]
> diff --git a/arch/arm64/mm/Kconfig b/arch/arm64/mm/Kconfig
> new file mode 100644
> index 0000000..e4122ac
> --- /dev/null
> +++ b/arch/arm64/mm/Kconfig
> @@ -0,0 +1,7 @@
> +config CPU_BIG_ENDIAN
> +        bool "Build big-endian kernel"
> +        help
> +          Say Y if you plan on running a kernel in big-endian mode.
> +          Note that your board must be properly built [...]

What makes a board properly built and how can a user determine whether their
board is?

> +                                                [...] and your board
> +          port must properly enable any big-endian related features
> +          of your chipset/board/processor.

What is a board port for arm64?

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.

[RFC PATCH 0/4] Big Endian support for ARM64 kernel

[Christopher Covington]

Hi Ankit,

On 10/11/2013 08:22 AM, Ankit Jindal wrote:
> This patchset adds support for using Big Endian mode of AArch64 CPUs
> 
> All patches have been tested on APM X-Gene Storm SOC.
> 
> The Big Endian toolchain used for development can be found at:
> http://cbuild.validation.linaro.org/snapshots/big_endian

At this URL I see:

404 Not Found

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.

[RFC PATCH 3/4] ARM64: Big Endian fixes for kernel booting

[Christopher Covington]

Hi Ankit,

On 10/11/2013 08:22 AM, Ankit Jindal wrote:
> - Enable appropriate bits for big endian kernel in SYSCTLR.EL2 and
>   SYSCTLR.EL1 registers
> - Swap entry point for secondary core for big endian kernel
> - Set machine type to "aarch64b" for big endian and "aarch64l"
>   for little endian.
[...]
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -122,6 +122,7 @@
>  	.word	0				// reserved
>  
>  ENTRY(stext)
> +	ARM_BE(bl      setend_be)
>  	mov	x21, x0				// x21=FDT
>  	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
>  	bl	el2_setup			// Drop to EL1
> @@ -148,6 +149,34 @@ ENTRY(stext)
>  ENDPROC(stext)
>  
>  /*
> + * Set el0-el1-el2 to Big endian
> + */

It might be helpful to say why this has to be done (each level needs to be set
up before it's used?) and maybe list them in the order they're set up in.

> +#if defined(CONFIG_CPU_BIG_ENDIAN)
> +ENTRY(setend_be)
> +	mrs     x21, CurrentEL
> +        cmp     x21, #PSR_MODE_EL2t
> +	b.ne  	setend_be_el1_el0

Make sure to use tabs rather than spaces and run checkpatch.pl.

> +
> +setend_be_el2:
> +	mrs     x21, sctlr_el2
> +        mov     x22, #(1<<25)
> +        orr     x21, x21, x22
> +        msr     sctlr_el2, x21
> +	isb
> +
> +setend_be_el1_el0:
> +	mrs     x21, sctlr_el1
> +        mov     x22, #(3<<24)
> +        orr     x21, x21, x22
> +        msr     sctlr_el1, x21
> +	isb
> +
> +	ret
> +ENDPROC(setend_be)
> +#endif /* defined(CONFIG_CPU_BIG_ENDIAN) */
> +
> +/*
>   * If we're fortunate enough to boot at EL2, ensure that the world is
>   * sane before dropping to EL1.
>   */
> @@ -181,7 +210,11 @@ ENTRY(el2_setup)
>  
>  	/* sctlr_el1 */
>  	mov	x0, #0x0800			// Set/clear RES{1,0} bits
> +#if defined(CONFIG_CPU_BIG_ENDIAN)
> +	movk	x0, #0x33d0, lsl #16
> +#else
>  	movk	x0, #0x30d0, lsl #16
> +#endif
>  	msr	sctlr_el1, x0

This may be easier to read if the magic number were ifdef'ed instead of the code.

[...]

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.

[RFC PATCH 1/4] ARM64: Add Kconfig option to enable Big Endian kernel

[Tushar Jagad]

Hi Christopher,

On 10/15/2013 11:39 PM, Christopher Covington wrote:

> What makes a board properly built and how can a user determine whether their
> board is?

As of now this flag assumes that the bootloader is in LE mode. It is 
left to the kernel to switch to BE mode. This flag makes the kernel set 
necessary flags in SCTLR registers on entry.
>
>> +                                                [...] and your board
>> +          port must properly enable any big-endian related features
>> +          of your chipset/board/processor.
>
> What is a board port for arm64?

This is a generic patch for the architecture. Each driver needs to make 
necessary changes keeping the kernel endianness in mind. We have tested 
these patches on our X-Gene platform.
-- 
Regards,
Tushar

[RFC PATCH 3/4] ARM64: Big Endian fixes for kernel booting

[Tushar Jagad]

Hi Christopher,

On 10/15/2013 11:54 PM, Christopher Covington wrote:
>>   /*
>> + * Set el0-el1-el2 to Big endian
>> + */
>
> It might be helpful to say why this has to be done (each level needs to be set
> up before it's used?) and maybe list them in the order they're set up in.

Sure will cover more details in the comment.

>> +#if defined(CONFIG_CPU_BIG_ENDIAN)
>> +ENTRY(setend_be)
>> +	mrs     x21, CurrentEL
>> +        cmp     x21, #PSR_MODE_EL2t
>> +	b.ne  	setend_be_el1_el0
>
> Make sure to use tabs rather than spaces and run checkpatch.pl.

Somehow this got skipped. Thanks for pointing it out.

>
>> +
>> +setend_be_el2:
>> +	mrs     x21, sctlr_el2
>> +        mov     x22, #(1<<25)
>> +        orr     x21, x21, x22
>> +        msr     sctlr_el2, x21
>> +	isb
>> +
>> +setend_be_el1_el0:
>> +	mrs     x21, sctlr_el1
>> +        mov     x22, #(3<<24)
>> +        orr     x21, x21, x22
>> +        msr     sctlr_el1, x21
>> +	isb
>> +
>> +	ret
>> +ENDPROC(setend_be)
>> +#endif /* defined(CONFIG_CPU_BIG_ENDIAN) */
>> +
>> +/*
>>    * If we're fortunate enough to boot at EL2, ensure that the world is
>>    * sane before dropping to EL1.
>>    */
>> @@ -181,7 +210,11 @@ ENTRY(el2_setup)
>>
>>   	/* sctlr_el1 */
>>   	mov	x0, #0x0800			// Set/clear RES{1,0} bits
>> +#if defined(CONFIG_CPU_BIG_ENDIAN)
>> +	movk	x0, #0x33d0, lsl #16
>> +#else
>>   	movk	x0, #0x30d0, lsl #16
>> +#endif
>>   	msr	sctlr_el1, x0
>
> This may be easier to read if the magic number were ifdef'ed instead of the code.

Will change this as well.
-- 
Regards,
Tushar

[RFC PATCH 0/4] Big Endian support for ARM64 kernel

[Tushar Jagad]

Hi Christopher,

On 10/15/2013 11:39 PM, Christopher Covington wrote:
> Hi Ankit,
>
> On 10/11/2013 08:22 AM, Ankit Jindal wrote:
>> This patchset adds support for using Big Endian mode of AArch64 CPUs
>>
>> All patches have been tested on APM X-Gene Storm SOC.
>>
>> The Big Endian toolchain used for development can be found at:
>> http://cbuild.validation.linaro.org/snapshots/big_endian
>
> At this URL I see:
>
> 404 Not Found

For now you can get a copy of the BE toolchains from

https://launchpad.net/linaro-toolchain-binaries/+milestone/2013.09
-- 
Regards,
Tushar

[RFC PATCH 1/4] ARM64: Add Kconfig option to enable Big Endian kernel

[Christopher Covington]

Hi Tushar,

On 10/16/2013 02:49 AM, Tushar Jagad wrote:
> Hi Christopher,
> 
> On 10/15/2013 11:39 PM, Christopher Covington wrote:
> 
>> What makes a board properly built and how can a user determine whether their
>> board is?
> 
> As of now this flag assumes that the bootloader is in LE mode. It is left to
> the kernel to switch to BE mode. This flag makes the kernel set necessary
> flags in SCTLR registers on entry.

I would suggest that you say that instead. The existing wording makes it sound
strictly hardware related.

>>
>>> +                                                [...] and your board
>>> +          port must properly enable any big-endian related features
>>> +          of your chipset/board/processor.
>>
>> What is a board port for arm64?
> 
> This is a generic patch for the architecture. Each driver needs to make
> necessary changes keeping the kernel endianness in mind. We have tested these
> patches on our X-Gene platform.

Perhaps it would be clearer to say "drivers" instead of "board ports" then. I
thought the comment was referring to code inside mach-* or plat-* directories.

Regards,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.

[RFC PATCH 0/4] Big Endian support for ARM64 kernel

[Christopher Covington]

On 10/16/2013 04:05 AM, Tushar Jagad wrote:
[...]
> 
> For now you can get a copy of the BE toolchains from
> 
> https://launchpad.net/linaro-toolchain-binaries/+milestone/2013.09

Excellent, thanks!

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.