[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tomi Valkeinen]

Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index b237950..ec0dc0b 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
 		OMAP4430_CM_DSS_DSS_CLKCTRL,
 		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
 
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
+		CLK_SET_RATE_PARENT,
 		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
 		0x0, NULL);
 
-- 
1.8.1.2

[PATCH 2/3] ARM: OMAP3: use CLK_SET_RATE_PARENT for dss clocks

[Tomi Valkeinen]

Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 334b767..a51dd75 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -869,7 +869,8 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = {
 	.clkdm_name	= "dpll4_clkdm",
 };
 
-DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
+DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
+		dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 
 static struct clk dpll4_m4x2_ck_3630 = {
 	.name		= "dpll4_m4x2_ck",
@@ -877,6 +878,7 @@ static struct clk dpll4_m4x2_ck_3630 = {
 	.parent_names	= dpll4_m4x2_ck_parent_names,
 	.num_parents	= ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
 	.ops		= &dpll4_m5x2_ck_3630_ops,
+	.flags		= CLK_SET_RATE_PARENT,
 };
 
 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
@@ -968,8 +970,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
 	.clkdm_name	= "dss_clkdm",
 };
 
-DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
-		  aes2_ick_ops);
+DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
+		dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
+		CLK_SET_RATE_PARENT);
 
 static struct clk dss1_alwon_fck_3430es2;
 
@@ -983,8 +986,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
 	.clkdm_name	= "dss_clkdm",
 };
 
-DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
-		  aes2_ick_ops);
+DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
+		dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
+		CLK_SET_RATE_PARENT);
 
 static struct clk dss2_alwon_fck;
 
-- 
1.8.1.2

[PATCH 3/3] ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers

[Tomi Valkeinen]

dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.

I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them, I didn't touch them.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c | 44 +++++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index a51dd75..e94d635 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -381,6 +381,42 @@ static struct clk_hw_omap dpll4_ck_hw = {
 
 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
 
+static const struct clk_div_table dpll4_mx_ck_div_table[] = {
+	{ .div = 1, .val = 1 },
+	{ .div = 2, .val = 2 },
+	{ .div = 3, .val = 3 },
+	{ .div = 4, .val = 4 },
+	{ .div = 5, .val = 5 },
+	{ .div = 6, .val = 6 },
+	{ .div = 7, .val = 7 },
+	{ .div = 8, .val = 8 },
+	{ .div = 9, .val = 9 },
+	{ .div = 10, .val = 10 },
+	{ .div = 11, .val = 11 },
+	{ .div = 12, .val = 12 },
+	{ .div = 13, .val = 13 },
+	{ .div = 14, .val = 14 },
+	{ .div = 15, .val = 15 },
+	{ .div = 16, .val = 16 },
+	{ .div = 17, .val = 17 },
+	{ .div = 18, .val = 18 },
+	{ .div = 19, .val = 19 },
+	{ .div = 20, .val = 20 },
+	{ .div = 21, .val = 21 },
+	{ .div = 22, .val = 22 },
+	{ .div = 23, .val = 23 },
+	{ .div = 24, .val = 24 },
+	{ .div = 25, .val = 25 },
+	{ .div = 26, .val = 26 },
+	{ .div = 27, .val = 27 },
+	{ .div = 28, .val = 28 },
+	{ .div = 29, .val = 29 },
+	{ .div = 30, .val = 30 },
+	{ .div = 31, .val = 31 },
+	{ .div = 32, .val = 32 },
+	{ .div = 0 },
+};
+
 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
 		   OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 		   OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
@@ -524,10 +560,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
 	{ .div = 0 }
 };
 
-DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
+DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
 		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 		   OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
+		   0, dpll4_mx_ck_div_table, NULL);
 
 static struct clk dpll4_m3x2_ck;
 
@@ -847,10 +883,10 @@ static struct clk dpll3_m3x2_ck_3630 = {
 
 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
 
-DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
+DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
 		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 		   OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
+		   0, dpll4_mx_ck_div_table, NULL);
 
 static struct clk dpll4_m4x2_ck;
 
-- 
1.8.1.2

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tero Kristo]

On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
> be configured without the need to get the parent of the fclk.

I wouldn't touch this file right now, as we are trying to move the clock 
data over to DT. Legacy boot support probably requires to do this 
update, but I would rather wait a bit and do the modifications to both 
DT clock data and this file in the same patch. Same applies for other 
patches also.

-Tero

>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>   arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> index b237950..ec0dc0b 100644
> --- a/arch/arm/mach-omap2/cclock44xx_data.c
> +++ b/arch/arm/mach-omap2/cclock44xx_data.c
> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
>   		OMAP4430_CM_DSS_DSS_CLKCTRL,
>   		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
>
> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
> +		CLK_SET_RATE_PARENT,
>   		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
>   		0x0, NULL);
>
>

[PATCH 3/3] ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers

[Tero Kristo]

On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
> dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
> wide. However, only values from 1 to 32 are allowed. This means we have
> to add a divider tables and list the dividers explicitly.
>
> I believe the same issue is there for other dpll4_mx_ck clocks, but as
> I'm not familiar with them, I didn't touch them.

I think you can limit the max value with a mask only, no need to define 
new tables.

Also similar comment regarding dts vs legacy clock data as for patch #1.

-Tero

>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>   arch/arm/mach-omap2/cclock3xxx_data.c | 44 +++++++++++++++++++++++++++++++----
>   1 file changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
> index a51dd75..e94d635 100644
> --- a/arch/arm/mach-omap2/cclock3xxx_data.c
> +++ b/arch/arm/mach-omap2/cclock3xxx_data.c
> @@ -381,6 +381,42 @@ static struct clk_hw_omap dpll4_ck_hw = {
>
>   DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
>
> +static const struct clk_div_table dpll4_mx_ck_div_table[] = {
> +	{ .div = 1, .val = 1 },
> +	{ .div = 2, .val = 2 },
> +	{ .div = 3, .val = 3 },
> +	{ .div = 4, .val = 4 },
> +	{ .div = 5, .val = 5 },
> +	{ .div = 6, .val = 6 },
> +	{ .div = 7, .val = 7 },
> +	{ .div = 8, .val = 8 },
> +	{ .div = 9, .val = 9 },
> +	{ .div = 10, .val = 10 },
> +	{ .div = 11, .val = 11 },
> +	{ .div = 12, .val = 12 },
> +	{ .div = 13, .val = 13 },
> +	{ .div = 14, .val = 14 },
> +	{ .div = 15, .val = 15 },
> +	{ .div = 16, .val = 16 },
> +	{ .div = 17, .val = 17 },
> +	{ .div = 18, .val = 18 },
> +	{ .div = 19, .val = 19 },
> +	{ .div = 20, .val = 20 },
> +	{ .div = 21, .val = 21 },
> +	{ .div = 22, .val = 22 },
> +	{ .div = 23, .val = 23 },
> +	{ .div = 24, .val = 24 },
> +	{ .div = 25, .val = 25 },
> +	{ .div = 26, .val = 26 },
> +	{ .div = 27, .val = 27 },
> +	{ .div = 28, .val = 28 },
> +	{ .div = 29, .val = 29 },
> +	{ .div = 30, .val = 30 },
> +	{ .div = 31, .val = 31 },
> +	{ .div = 32, .val = 32 },
> +	{ .div = 0 },
> +};
> +
>   DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
>   		   OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
>   		   OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
> @@ -524,10 +560,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
>   	{ .div = 0 }
>   };
>
> -DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
> +DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
>   		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>   		   OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
> -		   CLK_DIVIDER_ONE_BASED, NULL);
> +		   0, dpll4_mx_ck_div_table, NULL);
>
>   static struct clk dpll4_m3x2_ck;
>
> @@ -847,10 +883,10 @@ static struct clk dpll3_m3x2_ck_3630 = {
>
>   DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
>
> -DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
> +DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
>   		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
>   		   OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
> -		   CLK_DIVIDER_ONE_BASED, NULL);
> +		   0, dpll4_mx_ck_div_table, NULL);
>
>   static struct clk dpll4_m4x2_ck;
>
>

[PATCH 3/3] ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers

[Tomi Valkeinen]

On 09/10/13 16:22, Tero Kristo wrote:
> On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
>> dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
>> wide. However, only values from 1 to 32 are allowed. This means we have
>> to add a divider tables and list the dividers explicitly.
>>
>> I believe the same issue is there for other dpll4_mx_ck clocks, but as
>> I'm not familiar with them, I didn't touch them.
> 
> I think you can limit the max value with a mask only, no need to define
> new tables.

The bit field is 6 bits wide, so the mask is correct. It's just that the
biggest allowed value is 32, which takes 6 bits, not 63.

Changing the mask to 5 bits would limit the divider to 31, wouldn't it?

 Tomi


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[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tomi Valkeinen]

On 09/10/13 16:22, Tero Kristo wrote:
> On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
>> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
>> be configured without the need to get the parent of the fclk.
> 
> I wouldn't touch this file right now, as we are trying to move the clock
> data over to DT. Legacy boot support probably requires to do this
> update, but I would rather wait a bit and do the modifications to both
> DT clock data and this file in the same patch. Same applies for other
> patches also.

Sounds good. I don't have any particular wishes how this is done, but
I'd really like these to go into 3.13.

The fclk handling in omapdss is quite a mess, and these flags would make
it possible to clean it up. And the reason it's important to clean up
the fclk handling ASAP is AM43xx, which has yet another clocking scheme.

If these get only to 3.14, then I can fix the fclk handling only on 3.15.

 Tomi


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[PATCH 3/3] ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers

[Tero Kristo]

On 10/09/2013 04:33 PM, Tomi Valkeinen wrote:
> On 09/10/13 16:22, Tero Kristo wrote:
>> On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
>>> dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
>>> wide. However, only values from 1 to 32 are allowed. This means we have
>>> to add a divider tables and list the dividers explicitly.
>>>
>>> I believe the same issue is there for other dpll4_mx_ck clocks, but as
>>> I'm not familiar with them, I didn't touch them.
>>
>> I think you can limit the max value with a mask only, no need to define
>> new tables.
>
> The bit field is 6 bits wide, so the mask is correct. It's just that the
> biggest allowed value is 32, which takes 6 bits, not 63.
>
> Changing the mask to 5 bits would limit the divider to 31, wouldn't it?

Oh true. Sucks with legacy clocks then.

For dt clocks, you should be able to declare max / min divider values 
for ti,divider-clock type which would take care of this case. Just 
change the ti,max-div = <63>; field to ... = <32>;

-Tero

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tomi Valkeinen]

Hi Tony, Tero,

On 09/10/13 16:12, Tomi Valkeinen wrote:
> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
> be configured without the need to get the parent of the fclk.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>  arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> index b237950..ec0dc0b 100644
> --- a/arch/arm/mach-omap2/cclock44xx_data.c
> +++ b/arch/arm/mach-omap2/cclock44xx_data.c
> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
>  		OMAP4430_CM_DSS_DSS_CLKCTRL,
>  		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
>  
> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
> +		CLK_SET_RATE_PARENT,
>  		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
>  		0x0, NULL);

I was discussing with Tero about these three patches, and he was ok with
them being merged.

Tony, it'd be great to have these for 3.13, so that I can start cleaning
up the DSS driver's fclk management.

 Tomi


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[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tero Kristo]

On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
> Hi Tony, Tero,
>
> On 09/10/13 16:12, Tomi Valkeinen wrote:
>> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
>> be configured without the need to get the parent of the fclk.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> ---
>>   arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
>> index b237950..ec0dc0b 100644
>> --- a/arch/arm/mach-omap2/cclock44xx_data.c
>> +++ b/arch/arm/mach-omap2/cclock44xx_data.c
>> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
>>   		OMAP4430_CM_DSS_DSS_CLKCTRL,
>>   		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
>>
>> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
>> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
>> +		CLK_SET_RATE_PARENT,
>>   		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
>>   		0x0, NULL);
>
> I was discussing with Tero about these three patches, and he was ok with
> them being merged.
>
> Tony, it'd be great to have these for 3.13, so that I can start cleaning
> up the DSS driver's fclk management.

Yea, am ok with these, I can incorporate the changes to my DT clk series.

-Tero

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [131024 06:23]:
> On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
> >Hi Tony, Tero,
> >
> >On 09/10/13 16:12, Tomi Valkeinen wrote:
> >>Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
> >>be configured without the need to get the parent of the fclk.
> >>
> >>Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >>---
> >>  arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
> >>  1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >>diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> >>index b237950..ec0dc0b 100644
> >>--- a/arch/arm/mach-omap2/cclock44xx_data.c
> >>+++ b/arch/arm/mach-omap2/cclock44xx_data.c
> >>@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
> >>  		OMAP4430_CM_DSS_DSS_CLKCTRL,
> >>  		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
> >>
> >>-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
> >>+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
> >>+		CLK_SET_RATE_PARENT,
> >>  		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
> >>  		0x0, NULL);
> >
> >I was discussing with Tero about these three patches, and he was ok with
> >them being merged.
> >
> >Tony, it'd be great to have these for 3.13, so that I can start cleaning
> >up the DSS driver's fclk management.
> 
> Yea, am ok with these, I can incorporate the changes to my DT clk series.

OK. If you have fixes that should go in earlier, please put those into
a separate branch.

Regards,

Tony

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tero Kristo]

On 10/24/2013 04:28 PM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [131024 06:23]:
>> On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
>>> Hi Tony, Tero,
>>>
>>> On 09/10/13 16:12, Tomi Valkeinen wrote:
>>>> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
>>>> be configured without the need to get the parent of the fclk.
>>>>
>>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>>>> ---
>>>>   arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
>>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
>>>> index b237950..ec0dc0b 100644
>>>> --- a/arch/arm/mach-omap2/cclock44xx_data.c
>>>> +++ b/arch/arm/mach-omap2/cclock44xx_data.c
>>>> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
>>>>   		OMAP4430_CM_DSS_DSS_CLKCTRL,
>>>>   		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
>>>>
>>>> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
>>>> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
>>>> +		CLK_SET_RATE_PARENT,
>>>>   		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
>>>>   		0x0, NULL);
>>>
>>> I was discussing with Tero about these three patches, and he was ok with
>>> them being merged.
>>>
>>> Tony, it'd be great to have these for 3.13, so that I can start cleaning
>>> up the DSS driver's fclk management.
>>
>> Yea, am ok with these, I can incorporate the changes to my DT clk series.
>
> OK. If you have fixes that should go in earlier, please put those into
> a separate branch.

This is for Paul I guess, I meant I will do the changes needed for the 
DT series to get same fixes there.

-Tero

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [131024 06:32]:
> On 10/24/2013 04:28 PM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [131024 06:23]:
> >>On 10/24/2013 11:03 AM, Tomi Valkeinen wrote:
> >>>Hi Tony, Tero,
> >>>
> >>>On 09/10/13 16:12, Tomi Valkeinen wrote:
> >>>>Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
> >>>>be configured without the need to get the parent of the fclk.
> >>>>
> >>>>Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >>>>---
> >>>>  arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
> >>>>  1 file changed, 2 insertions(+), 1 deletion(-)
> >>>>
> >>>>diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> >>>>index b237950..ec0dc0b 100644
> >>>>--- a/arch/arm/mach-omap2/cclock44xx_data.c
> >>>>+++ b/arch/arm/mach-omap2/cclock44xx_data.c
> >>>>@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
> >>>>  		OMAP4430_CM_DSS_DSS_CLKCTRL,
> >>>>  		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
> >>>>
> >>>>-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
> >>>>+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
> >>>>+		CLK_SET_RATE_PARENT,
> >>>>  		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
> >>>>  		0x0, NULL);
> >>>
> >>>I was discussing with Tero about these three patches, and he was ok with
> >>>them being merged.
> >>>
> >>>Tony, it'd be great to have these for 3.13, so that I can start cleaning
> >>>up the DSS driver's fclk management.
> >>
> >>Yea, am ok with these, I can incorporate the changes to my DT clk series.
> >
> >OK. If you have fixes that should go in earlier, please put those into
> >a separate branch.
> 
> This is for Paul I guess, I meant I will do the changes needed for
> the DT series to get same fixes there.

OK, Paul care to take a look and queue or ack if it looks OK to you?

Regards,

Tony

[PATCH 1/3] ARM: OMAP4: use CLK_SET_RATE_PARENT for dss_dss_clk

[Paul Walmsley]

On Wed, 9 Oct 2013, Tomi Valkeinen wrote:

> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
> be configured without the need to get the parent of the fclk.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

Thanks, queued.

- Paul

[PATCH 2/3] ARM: OMAP3: use CLK_SET_RATE_PARENT for dss clocks

[Paul Walmsley]

On Wed, 9 Oct 2013, Tomi Valkeinen wrote:

> Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
> dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
> configured without the need to get the parent's parent of the fclk.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

Thanks, queued.

- Paul

[PATCH 3/3] ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers

[Paul Walmsley]

On Wed, 9 Oct 2013, Tomi Valkeinen wrote:

> dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
> wide. However, only values from 1 to 32 are allowed. This means we have
> to add a divider tables and list the dividers explicitly.
> 
> I believe the same issue is there for other dpll4_mx_ck clocks, but as
> I'm not familiar with them, I didn't touch them.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

Thanks, queued.  Does anyone out there want to take care of patching the 
remaining DPLL output clocks that suffer from the same problem?


- Paul