[PATCH 0/8] ARM: imx: add IMX50 SoC support

[PATCH 0/8] ARM: imx: add IMX50 SoC support

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

This set of patches is the code and device tree support for the Freescale
IMX50 SoC. This part is similar to the IMX53 SoC family, and I have resued
as much of its support as possible. These patches are against 3.12-rc5.

With these changes you can load and run on the Freescale IMX50-EVK board.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/Kconfig.debug              |    9 
 arch/arm/boot/dts/Makefile          |    1 
 arch/arm/boot/dts/imx50-evk.dts     |   89 +++
 arch/arm/boot/dts/imx50-pinfunc.h   |  923 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx50.dtsi        |  659 +++++++++++++++++++++++++
 arch/arm/include/debug/imx-uart.h   |   10 
 arch/arm/mach-imx/Kconfig           |    9 
 arch/arm/mach-imx/Makefile          |    1 
 arch/arm/mach-imx/clk-imx51-imx53.c |   79 +++
 arch/arm/mach-imx/common.h          |    3 
 arch/arm/mach-imx/mach-imx50.c      |   52 ++
 drivers/pinctrl/Kconfig             |    8 
 drivers/pinctrl/Makefile            |    1 
 drivers/pinctrl/pinctrl-imx50.c     |  426 ++++++++++++++++
 14 files changed, 2270 insertions(+)

[PATCH 1/8] ARM: imx: add debug uart support for IMX50 SoC

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add appropriate UART address definitions and support defines for using the
UARTs of the Freescale IMX50 SoC as debug ports.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/Kconfig.debug            |  9 +++++++++
 arch/arm/include/debug/imx-uart.h | 10 ++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9762c84..b9c6c9b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -255,6 +255,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX35.
 
+	config DEBUG_IMX50_UART
+		bool "i.MX50 Debug UART"
+		depends on SOC_IMX50
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on i.MX50.
+
 	config DEBUG_IMX51_UART
 		bool "i.MX51 Debug UART"
 		depends on SOC_IMX51
@@ -862,6 +869,7 @@ config DEBUG_IMX_UART_PORT
 						DEBUG_IMX21_IMX27_UART || \
 						DEBUG_IMX31_UART || \
 						DEBUG_IMX35_UART || \
+						DEBUG_IMX50_UART || \
 						DEBUG_IMX51_UART || \
 						DEBUG_IMX53_UART || \
 						DEBUG_IMX6Q_UART || \
@@ -891,6 +899,7 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_IMX21_IMX27_UART || \
 				 DEBUG_IMX31_UART || \
 				 DEBUG_IMX35_UART || \
+				 DEBUG_IMX50_UART || \
 				 DEBUG_IMX51_UART || \
 				 DEBUG_IMX53_UART ||\
 				 DEBUG_IMX6Q_UART || \
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 29da84e..42b823c 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -43,6 +43,14 @@
 #define IMX35_UART_BASE_ADDR(n)	IMX35_UART##n##_BASE_ADDR
 #define IMX35_UART_BASE(n)	IMX35_UART_BASE_ADDR(n)
 
+#define IMX50_UART1_BASE_ADDR	0x53fbc000
+#define IMX50_UART2_BASE_ADDR	0x53fc0000
+#define IMX50_UART3_BASE_ADDR	0x5000c000
+#define IMX50_UART4_BASE_ADDR	0x53ff0000
+#define IMX50_UART5_BASE_ADDR	0x63f90000
+#define IMX50_UART_BASE_ADDR(n)	IMX50_UART##n##_BASE_ADDR
+#define IMX50_UART_BASE(n)	IMX50_UART_BASE_ADDR(n)
+
 #define IMX51_UART1_BASE_ADDR	0x73fbc000
 #define IMX51_UART2_BASE_ADDR	0x73fc0000
 #define IMX51_UART3_BASE_ADDR	0x7000c000
@@ -85,6 +93,8 @@
 #define UART_PADDR	IMX_DEBUG_UART_BASE(IMX31)
 #elif defined(CONFIG_DEBUG_IMX35_UART)
 #define UART_PADDR	IMX_DEBUG_UART_BASE(IMX35)
+#elif defined(CONFIG_DEBUG_IMX50_UART)
+#define UART_PADDR	IMX_DEBUG_UART_BASE(IMX50)
 #elif defined(CONFIG_DEBUG_IMX51_UART)
 #define UART_PADDR	IMX_DEBUG_UART_BASE(IMX51)
 #elif defined(CONFIG_DEBUG_IMX53_UART)
-- 
1.8.1.4

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add code to support the specific clock tree of the Freescale IMX50 SoC.
It can use much of the common IMX51/IMX53 clocking code.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/mach-imx/clk-imx51-imx53.c | 79 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/common.h          |  3 ++
 2 files changed, 82 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 7c0dc45..ea4523a 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -363,6 +363,80 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
 }
 
+int __init mx50_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+			unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+	int i;
+	unsigned long r;
+	struct device_node *np;
+
+	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+
+	clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+	clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
+	clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
+	clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+	clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
+	clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
+	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+
+	clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
+				mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
+	clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
+	clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
+
+	clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
+				mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
+	clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
+	clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+
+	for (i = 0; i < ARRAY_SIZE(clk); i++)
+		if (IS_ERR(clk[i]))
+			pr_err("i.MX50 clk %d: register failed with %ld\n",
+				i, PTR_ERR(clk[i]));
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx50-ccm");
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+	clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
+	clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
+	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
+	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx50.0");
+	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.0");
+	clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx50.0");
+	clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx50.1");
+	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.1");
+	clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx50.1");
+	clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx50.2");
+	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.2");
+	clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx50.2");
+	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx50.3");
+	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.3");
+	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx50.3");
+
+	/* set SDHC root clock to 200MHZ*/
+	clk_set_rate(clk[esdhc_a_podf], 200000000);
+	clk_set_rate(clk[esdhc_b_podf], 200000000);
+
+	/* System timer */
+	mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
+
+	clk_prepare_enable(clk[iim_gate]);
+	imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
+	clk_disable_unprepare(clk[iim_gate]);
+
+	r = clk_round_rate(clk[usboh3_per_gate], 54000000);
+	clk_set_rate(clk[usboh3_per_gate], r);
+
+	return 0;
+}
+
 int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 			unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
@@ -570,6 +644,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	return 0;
 }
 
+int __init mx50_clocks_init_dt(void)
+{
+	return mx50_clocks_init(0, 0, 0, 0);
+}
+
 int __init mx51_clocks_init_dt(void)
 {
 	return mx51_clocks_init(0, 0, 0, 0);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4517fd7..afa56cb 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -61,6 +61,8 @@ extern int mx25_clocks_init(void);
 extern int mx27_clocks_init(unsigned long fref);
 extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
+extern int mx50_clocks_init(unsigned long ckil, unsigned long osc,
+			unsigned long ckih1, unsigned long ckih2);
 extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
@@ -68,6 +70,7 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
 extern int mx25_clocks_init_dt(void);
 extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
+extern int mx50_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
-- 
1.8.1.4

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Sascha Hauer]

Hi Greg,

On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Add code to support the specific clock tree of the Freescale IMX50 SoC.
> It can use much of the common IMX51/IMX53 clocking code.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
> +	clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
> +	clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
> +	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
> +	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx50.3");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.3");
> +	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx50.3");

The above shouldn't be needed with dt-only support. On i.MX51/53 these
are only needed for platform based support.

Sascha

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[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Greg Ungerer]

Hi Sascha,

On 22/10/13 22:27, Sascha Hauer wrote:
> Hi Greg,
> 
> On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> Add code to support the specific clock tree of the Freescale IMX50 SoC.
>> It can use much of the common IMX51/IMX53 clocking code.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>> +	clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
>> +	clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
>> +	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
>> +	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx50.0");
>> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.0");
>> +	clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx50.0");
>> +	clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx50.1");
>> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.1");
>> +	clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx50.1");
>> +	clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx50.2");
>> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.2");
>> +	clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx50.2");
>> +	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx50.3");
>> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.3");
>> +	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx50.3");
> 
> The above shouldn't be needed with dt-only support. On i.MX51/53 these
> are only needed for platform based support.

Ok, thanks. I'll remove them.

Regards
Greg

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Jason Cooper]

Greg,

On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Add code to support the specific clock tree of the Freescale IMX50 SoC.
> It can use much of the common IMX51/IMX53 clocking code.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c | 79 +++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/common.h          |  3 ++
>  2 files changed, 82 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index 7c0dc45..ea4523a 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -363,6 +363,80 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
>  }
>  
> +int __init mx50_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
> +			unsigned long rate_ckih1, unsigned long rate_ckih2)
> +{
> +	int i;
> +	unsigned long r;
> +	struct device_node *np;
> +
> +	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
> +	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
> +	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);

What about the apll and it's derivatives?

thx,

Jason.

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Greg Ungerer]

Hi Jason,

On 23/10/13 19:19, Jason Cooper wrote:
> Greg,
>
> On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> Add code to support the specific clock tree of the Freescale IMX50 SoC.
>> It can use much of the common IMX51/IMX53 clocking code.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>>   arch/arm/mach-imx/clk-imx51-imx53.c | 79 +++++++++++++++++++++++++++++++++++++
>>   arch/arm/mach-imx/common.h          |  3 ++
>>   2 files changed, 82 insertions(+)
>>
>> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
>> index 7c0dc45..ea4523a 100644
>> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
>> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
>> @@ -363,6 +363,80 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>>   	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
>>   }
>>
>> +int __init mx50_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>> +			unsigned long rate_ckih1, unsigned long rate_ckih2)
>> +{
>> +	int i;
>> +	unsigned long r;
>> +	struct device_node *np;
>> +
>> +	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
>> +	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
>> +	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
>
> What about the apll and it's derivatives?

The IMX50RM.pdf seems light on details on the apll. Is it any different
to the imx51 and imx53 families?

Regards
Greg

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Jason Cooper]

On Wed, Oct 23, 2013 at 10:44:22PM +1000, Greg Ungerer wrote:
> Hi Jason,
> 
> On 23/10/13 19:19, Jason Cooper wrote:
> >Greg,
> >
> >On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
> >>From: Greg Ungerer <gerg@uclinux.org>
> >>
> >>Add code to support the specific clock tree of the Freescale IMX50 SoC.
> >>It can use much of the common IMX51/IMX53 clocking code.
> >>
> >>Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> >>---
> >>  arch/arm/mach-imx/clk-imx51-imx53.c | 79 +++++++++++++++++++++++++++++++++++++
> >>  arch/arm/mach-imx/common.h          |  3 ++
> >>  2 files changed, 82 insertions(+)
> >>
> >>diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> >>index 7c0dc45..ea4523a 100644
> >>--- a/arch/arm/mach-imx/clk-imx51-imx53.c
> >>+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> >>@@ -363,6 +363,80 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
> >>  	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
> >>  }
> >>
> >>+int __init mx50_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
> >>+			unsigned long rate_ckih1, unsigned long rate_ckih2)
> >>+{
> >>+	int i;
> >>+	unsigned long r;
> >>+	struct device_node *np;
> >>+
> >>+	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
> >>+	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
> >>+	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
> >
> >What about the apll and it's derivatives?
> 
> The IMX50RM.pdf seems light on details on the apll. Is it any different
> to the imx51 and imx53 families?

yes, see 5.3.1.4:

"""
There is a fixed 480 MHz PLL that feeds eight independent Phase
Fractional Dividers (PFDs). The PFDs allow multiple fractional clocks to
be generated from one PLL without the trouble of relocking the PLL each
time.
"""

Now, after discussing this with MikeT and a few others at the ARM
mini-summit, I've learned that my naive assumption of a completely
described clock tree is wrong.  We basically just describe what we need to
get the job done. ie, the leaves and the core.

So I'm sure this is fine as is if you are successfully booting it on
your board.  My question was more focused on learning what advantage the
apll and the pfds may provide that would make it worth describing the
full tree.

thx,

Jason.

[PATCH 2/8] ARM: imx: add clocking support code for the IMX50 SoC

[Shawn Guo]

On Fri, Oct 18, 2013 at 04:04:14PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Add code to support the specific clock tree of the Freescale IMX50 SoC.
> It can use much of the common IMX51/IMX53 clocking code.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c | 79 +++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/common.h          |  3 ++
>  2 files changed, 82 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index 7c0dc45..ea4523a 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -363,6 +363,80 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
>  }
>  
> +int __init mx50_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
> +			unsigned long rate_ckih1, unsigned long rate_ckih2)
> +{
> +	int i;
> +	unsigned long r;
> +	struct device_node *np;
> +
> +	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
> +	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
> +	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
> +
> +	clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
> +	clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
> +	clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
> +	clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
> +	clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
> +	clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
> +	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
> +
> +	clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
> +				mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
> +	clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
> +	clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
> +
> +	clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
> +				mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
> +	clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
> +	clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
> +
> +	for (i = 0; i < ARRAY_SIZE(clk); i++)
> +		if (IS_ERR(clk[i]))
> +			pr_err("i.MX50 clk %d: register failed with %ld\n",
> +				i, PTR_ERR(clk[i]));
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,imx50-ccm");
> +	clk_data.clks = clk;
> +	clk_data.clk_num = ARRAY_SIZE(clk);
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> +	mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
> +
> +	clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
> +	clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
> +	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
> +	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx50.0");
> +	clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx50.1");
> +	clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx50.2");
> +	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx50.3");
> +	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx50.3");
> +	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx50.3");
> +
> +	/* set SDHC root clock to 200MHZ*/
> +	clk_set_rate(clk[esdhc_a_podf], 200000000);
> +	clk_set_rate(clk[esdhc_b_podf], 200000000);
> +
> +	/* System timer */
> +	mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);

Oh, no.  These macros will eventually go away.  For device tree platform,
all these resources should be retrieved from device tree.  If you look
at clk-imx51-imx53.c on my for-next branch, you will see imx53 clock
code has been updated regarding that.

> +
> +	clk_prepare_enable(clk[iim_gate]);
> +	imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
> +	clk_disable_unprepare(clk[iim_gate]);
> +
> +	r = clk_round_rate(clk[usboh3_per_gate], 54000000);
> +	clk_set_rate(clk[usboh3_per_gate], r);
> +
> +	return 0;
> +}
> +
>  int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  			unsigned long rate_ckih1, unsigned long rate_ckih2)
>  {
> @@ -570,6 +644,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  	return 0;
>  }
>  
> +int __init mx50_clocks_init_dt(void)
> +{
> +	return mx50_clocks_init(0, 0, 0, 0);
> +}
> +

As Rob has just pointed out, we should use CLK_OF_DECLARE() for clock
initialization, so that .init_timer hook can be saved for DT machines.
Again, take a look at the imx53 code on my for-next branch for example.

Shawn

>  int __init mx51_clocks_init_dt(void)
>  {
>  	return mx51_clocks_init(0, 0, 0, 0);
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 4517fd7..afa56cb 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -61,6 +61,8 @@ extern int mx25_clocks_init(void);
>  extern int mx27_clocks_init(unsigned long fref);
>  extern int mx31_clocks_init(unsigned long fref);
>  extern int mx35_clocks_init(void);
> +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc,
> +			unsigned long ckih1, unsigned long ckih2);
>  extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
>  			unsigned long ckih1, unsigned long ckih2);
>  extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
> @@ -68,6 +70,7 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
>  extern int mx25_clocks_init_dt(void);
>  extern int mx27_clocks_init_dt(void);
>  extern int mx31_clocks_init_dt(void);
> +extern int mx50_clocks_init_dt(void);
>  extern int mx51_clocks_init_dt(void);
>  extern int mx53_clocks_init_dt(void);
>  extern struct platform_device *mxc_register_gpio(char *name, int id,
> -- 
> 1.8.1.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/8] ARM: imx: add pinctrl support code for the IMX50 SoC

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add code to support the specific pin arrangements of the Freescale IMX50 SoC.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 drivers/pinctrl/Kconfig         |   8 +
 drivers/pinctrl/Makefile        |   1 +
 drivers/pinctrl/pinctrl-imx50.c | 426 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-imx50.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6e864e..530cc8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -88,6 +88,14 @@ config PINCTRL_IMX35
 	help
 	  Say Y here to enable the imx35 pinctrl driver
 
+config PINCTRL_IMX50
+	bool "IMX50 pinctrl driver"
+	depends on OF
+	depends on SOC_IMX50
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx50 pinctrl driver
+
 config PINCTRL_IMX51
 	bool "IMX51 pinctrl driver"
 	depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 496d9bf..cfff09e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)	+= pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BAYTRAIL)	+= pinctrl-baytrail.o
 obj-$(CONFIG_PINCTRL_IMX)	+= pinctrl-imx.o
 obj-$(CONFIG_PINCTRL_IMX35)	+= pinctrl-imx35.o
+obj-$(CONFIG_PINCTRL_IMX50)	+= pinctrl-imx50.o
 obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6q.o
diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c
new file mode 100644
index 0000000..b06feed
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx50.c
@@ -0,0 +1,426 @@
+/*
+ * imx50 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx50_pads {
+	MX50_PAD_RESERVE0 = 0,
+	MX50_PAD_RESERVE1 = 1,
+	MX50_PAD_RESERVE2 = 2,
+	MX50_PAD_RESERVE3 = 3,
+	MX50_PAD_RESERVE4 = 4,
+	MX50_PAD_RESERVE5 = 5,
+	MX50_PAD_RESERVE6 = 6,
+	MX50_PAD_RESERVE7 = 7,
+	MX50_PAD_KEY_COL0 = 8,
+	MX50_PAD_KEY_ROW0 = 9,
+	MX50_PAD_KEY_COL1 = 10,
+	MX50_PAD_KEY_ROW1 = 11,
+	MX50_PAD_KEY_COL2 = 12,
+	MX50_PAD_KEY_ROW2 = 13,
+	MX50_PAD_KEY_COL3 = 14,
+	MX50_PAD_KEY_ROW3 = 15,
+	MX50_PAD_I2C1_SCL = 16,
+	MX50_PAD_I2C1_SDA = 17,
+	MX50_PAD_I2C2_SCL = 18,
+	MX50_PAD_I2C2_SDA = 19,
+	MX50_PAD_I2C3_SCL = 20,
+	MX50_PAD_I2C3_SDA = 21,
+	MX50_PAD_PWM1 = 22,
+	MX50_PAD_PWM2 = 23,
+	MX50_PAD_0WIRE = 24,
+	MX50_PAD_EPITO = 25,
+	MX50_PAD_WDOG = 26,
+	MX50_PAD_SSI_TXFS = 27,
+	MX50_PAD_SSI_TXC = 28,
+	MX50_PAD_SSI_TXD = 29,
+	MX50_PAD_SSI_RXD = 30,
+	MX50_PAD_SSI_RXF = 31,
+	MX50_PAD_SSI_RXC = 32,
+	MX50_PAD_UART1_TXD = 33,
+	MX50_PAD_UART1_RXD = 34,
+	MX50_PAD_UART1_CTS = 35,
+	MX50_PAD_UART1_RTS = 36,
+	MX50_PAD_UART2_TXD = 37,
+	MX50_PAD_UART2_RXD = 38,
+	MX50_PAD_UART2_CTS = 39,
+	MX50_PAD_UART2_RTS = 40,
+	MX50_PAD_UART3_TXD = 41,
+	MX50_PAD_UART3_RXD = 42,
+	MX50_PAD_UART4_TXD = 43,
+	MX50_PAD_UART4_RXD = 44,
+	MX50_PAD_CSPI_CLK = 45,
+	MX50_PAD_CSPI_MOSI = 46,
+	MX50_PAD_CSPI_MISO = 47,
+	MX50_PAD_CSPI_SS0 = 48,
+	MX50_PAD_ECSPI1_CLK = 49,
+	MX50_PAD_ECSPI1_MOSI = 50,
+	MX50_PAD_ECSPI1_MISO = 51,
+	MX50_PAD_ECSPI1_SS0 = 52,
+	MX50_PAD_ECSPI2_CLK = 53,
+	MX50_PAD_ECSPI2_MOSI = 54,
+	MX50_PAD_ECSPI2_MISO = 55,
+	MX50_PAD_ECSPI2_SS0 = 56,
+	MX50_PAD_SD1_CLK = 57,
+	MX50_PAD_SD1_CMD = 58,
+	MX50_PAD_SD1_D0 = 59,
+	MX50_PAD_SD1_D1 = 60,
+	MX50_PAD_SD1_D2 = 61,
+	MX50_PAD_SD1_D3 = 62,
+	MX50_PAD_SD2_CLK = 63,
+	MX50_PAD_SD2_CMD = 64,
+	MX50_PAD_SD2_D0 = 65,
+	MX50_PAD_SD2_D1 = 66,
+	MX50_PAD_SD2_D2 = 67,
+	MX50_PAD_SD2_D3 = 68,
+	MX50_PAD_SD2_D4 = 69,
+	MX50_PAD_SD2_D5 = 70,
+	MX50_PAD_SD2_D6 = 71,
+	MX50_PAD_SD2_D7 = 72,
+	MX50_PAD_SD2_WP = 73,
+	MX50_PAD_SD2_CD = 74,
+	MX50_PAD_DISP_D0 = 75,
+	MX50_PAD_DISP_D1 = 76,
+	MX50_PAD_DISP_D2 = 77,
+	MX50_PAD_DISP_D3 = 78,
+	MX50_PAD_DISP_D4 = 79,
+	MX50_PAD_DISP_D5 = 80,
+	MX50_PAD_DISP_D6 = 81,
+	MX50_PAD_DISP_D7 = 82,
+	MX50_PAD_DISP_WR = 83,
+	MX50_PAD_DISP_RD = 84,
+	MX50_PAD_DISP_RS = 85,
+	MX50_PAD_DISP_CS = 86,
+	MX50_PAD_DISP_BUSY = 87,
+	MX50_PAD_DISP_RESET = 88,
+	MX50_PAD_SD3_CLK = 89,
+	MX50_PAD_SD3_CMD = 90,
+	MX50_PAD_SD3_D0 = 91,
+	MX50_PAD_SD3_D1 = 92,
+	MX50_PAD_SD3_D2 = 93,
+	MX50_PAD_SD3_D3 = 94,
+	MX50_PAD_SD3_D4 = 95,
+	MX50_PAD_SD3_D5 = 96,
+	MX50_PAD_SD3_D6 = 97,
+	MX50_PAD_SD3_D7 = 98,
+	MX50_PAD_SD3_WP = 99,
+	MX50_PAD_DISP_D8 = 100,
+	MX50_PAD_DISP_D9 = 101,
+	MX50_PAD_DISP_D10 = 102,
+	MX50_PAD_DISP_D11 = 103,
+	MX50_PAD_DISP_D12 = 104,
+	MX50_PAD_DISP_D13 = 105,
+	MX50_PAD_DISP_D14 = 106,
+	MX50_PAD_DISP_D15 = 107,
+	MX50_PAD_EPDC_D0 = 108,
+	MX50_PAD_EPDC_D1 = 109,
+	MX50_PAD_EPDC_D2 = 110,
+	MX50_PAD_EPDC_D3 = 111,
+	MX50_PAD_EPDC_D4 = 112,
+	MX50_PAD_EPDC_D5 = 113,
+	MX50_PAD_EPDC_D6 = 114,
+	MX50_PAD_EPDC_D7 = 115,
+	MX50_PAD_EPDC_D8 = 116,
+	MX50_PAD_EPDC_D9 = 117,
+	MX50_PAD_EPDC_D10 = 118,
+	MX50_PAD_EPDC_D11 = 119,
+	MX50_PAD_EPDC_D12 = 120,
+	MX50_PAD_EPDC_D13 = 121,
+	MX50_PAD_EPDC_D14 = 122,
+	MX50_PAD_EPDC_D15 = 123,
+	MX50_PAD_EPDC_GDCLK = 124,
+	MX50_PAD_EPDC_GDSP = 125,
+	MX50_PAD_EPDC_GDOE = 126,
+	MX50_PAD_EPDC_GDRL = 127,
+	MX50_PAD_EPDC_SDCLK = 128,
+	MX50_PAD_EPDC_SDOEZ = 129,
+	MX50_PAD_EPDC_SDOED = 130,
+	MX50_PAD_EPDC_SDOE = 131,
+	MX50_PAD_EPDC_SDLE = 132,
+	MX50_PAD_EPDC_SDCLKN = 133,
+	MX50_PAD_EPDC_SDSHR = 134,
+	MX50_PAD_EPDC_PWRCOM = 135,
+	MX50_PAD_EPDC_PWRSTAT = 136,
+	MX50_PAD_EPDC_PWRCTRL0 = 137,
+	MX50_PAD_EPDC_PWRCTRL1 = 138,
+	MX50_PAD_EPDC_PWRCTRL2 = 139,
+	MX50_PAD_EPDC_PWRCTRL3 = 140,
+	MX50_PAD_EPDC_VCOM0 = 141,
+	MX50_PAD_EPDC_VCOM1 = 142,
+	MX50_PAD_EPDC_BDR0 = 143,
+	MX50_PAD_EPDC_BDR1 = 144,
+	MX50_PAD_EPDC_SDCE0 = 145,
+	MX50_PAD_EPDC_SDCE1 = 146,
+	MX50_PAD_EPDC_SDCE2 = 147,
+	MX50_PAD_EPDC_SDCE3 = 148,
+	MX50_PAD_EPDC_SDCE4 = 149,
+	MX50_PAD_EPDC_SDCE5 = 150,
+	MX50_PAD_EIM_DA0 = 151,
+	MX50_PAD_EIM_DA1 = 152,
+	MX50_PAD_EIM_DA2 = 153,
+	MX50_PAD_EIM_DA3 = 154,
+	MX50_PAD_EIM_DA4 = 155,
+	MX50_PAD_EIM_DA5 = 156,
+	MX50_PAD_EIM_DA6 = 157,
+	MX50_PAD_EIM_DA7 = 158,
+	MX50_PAD_EIM_DA8 = 159,
+	MX50_PAD_EIM_DA9 = 160,
+	MX50_PAD_EIM_DA10 = 161,
+	MX50_PAD_EIM_DA11 = 162,
+	MX50_PAD_EIM_DA12 = 163,
+	MX50_PAD_EIM_DA13 = 164,
+	MX50_PAD_EIM_DA14 = 165,
+	MX50_PAD_EIM_DA15 = 166,
+	MX50_PAD_EIM_CS2 = 167,
+	MX50_PAD_EIM_CS1 = 168,
+	MX50_PAD_EIM_CS0 = 169,
+	MX50_PAD_EIM_EB0 = 170,
+	MX50_PAD_EIM_EB1 = 171,
+	MX50_PAD_EIM_WAIT = 172,
+	MX50_PAD_EIM_BCLK = 173,
+	MX50_PAD_EIM_RDY = 174,
+	MX50_PAD_EIM_OE = 175,
+	MX50_PAD_EIM_RW = 176,
+	MX50_PAD_EIM_LBA = 177,
+	MX50_PAD_EIM_CRE = 178,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
+	IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
+	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
+	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
+	IMX_PINCTRL_PIN(MX50_PAD_PWM1),
+	IMX_PINCTRL_PIN(MX50_PAD_PWM2),
+	IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
+	IMX_PINCTRL_PIN(MX50_PAD_EPITO),
+	IMX_PINCTRL_PIN(MX50_PAD_WDOG),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
+	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
+	IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
+	IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
+	IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
+	IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
+	IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
+	IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
+	IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
+	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
+	IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
+	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
+	IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
+	IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
+	IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
+	IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
+	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
+	IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
+};
+
+static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
+	.pins = imx50_pinctrl_pads,
+	.npins = ARRAY_SIZE(imx50_pinctrl_pads),
+};
+
+static struct of_device_id imx50_pinctrl_of_match[] = {
+	{ .compatible = "fsl,imx50-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int imx50_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
+}
+
+static struct platform_driver imx50_pinctrl_driver = {
+	.driver = {
+		.name = "imx50-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
+	},
+	.probe = imx50_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+};
+
+static int __init imx50_pinctrl_init(void)
+{
+	return platform_driver_register(&imx50_pinctrl_driver);
+}
+arch_initcall(imx50_pinctrl_init);
+
+static void __exit imx50_pinctrl_exit(void)
+{
+	platform_driver_unregister(&imx50_pinctrl_driver);
+}
+module_exit(imx50_pinctrl_exit);
+MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.4

[PATCH 3/8] ARM: imx: add pinctrl support code for the IMX50 SoC

[Shawn Guo]

On Fri, Oct 18, 2013 at 04:04:15PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Add code to support the specific pin arrangements of the Freescale IMX50 SoC.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>

This patch should be sent to Linus Walleij <linus.walleij@linaro.org>,
who is the pinctrl subsystem maintainer.

And the patch subject prefix should be "pinctrl: imx50: ..."

Shawn

> ---
>  drivers/pinctrl/Kconfig         |   8 +
>  drivers/pinctrl/Makefile        |   1 +
>  drivers/pinctrl/pinctrl-imx50.c | 426 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 435 insertions(+)
>  create mode 100644 drivers/pinctrl/pinctrl-imx50.c
> 
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index b6e864e..530cc8d 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -88,6 +88,14 @@ config PINCTRL_IMX35
>  	help
>  	  Say Y here to enable the imx35 pinctrl driver
>  
> +config PINCTRL_IMX50
> +	bool "IMX50 pinctrl driver"
> +	depends on OF
> +	depends on SOC_IMX50
> +	select PINCTRL_IMX
> +	help
> +	  Say Y here to enable the imx50 pinctrl driver
> +
>  config PINCTRL_IMX51
>  	bool "IMX51 pinctrl driver"
>  	depends on OF
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 496d9bf..cfff09e 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)	+= pinctrl-bcm2835.o
>  obj-$(CONFIG_PINCTRL_BAYTRAIL)	+= pinctrl-baytrail.o
>  obj-$(CONFIG_PINCTRL_IMX)	+= pinctrl-imx.o
>  obj-$(CONFIG_PINCTRL_IMX35)	+= pinctrl-imx35.o
> +obj-$(CONFIG_PINCTRL_IMX50)	+= pinctrl-imx50.o
>  obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
>  obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
>  obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6q.o
> diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c
> new file mode 100644
> index 0000000..b06feed
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-imx50.c
> @@ -0,0 +1,426 @@
> +/*
> + * imx50 pinctrl driver based on imx pinmux core
> + *
> + * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +enum imx50_pads {
> +	MX50_PAD_RESERVE0 = 0,
> +	MX50_PAD_RESERVE1 = 1,
> +	MX50_PAD_RESERVE2 = 2,
> +	MX50_PAD_RESERVE3 = 3,
> +	MX50_PAD_RESERVE4 = 4,
> +	MX50_PAD_RESERVE5 = 5,
> +	MX50_PAD_RESERVE6 = 6,
> +	MX50_PAD_RESERVE7 = 7,
> +	MX50_PAD_KEY_COL0 = 8,
> +	MX50_PAD_KEY_ROW0 = 9,
> +	MX50_PAD_KEY_COL1 = 10,
> +	MX50_PAD_KEY_ROW1 = 11,
> +	MX50_PAD_KEY_COL2 = 12,
> +	MX50_PAD_KEY_ROW2 = 13,
> +	MX50_PAD_KEY_COL3 = 14,
> +	MX50_PAD_KEY_ROW3 = 15,
> +	MX50_PAD_I2C1_SCL = 16,
> +	MX50_PAD_I2C1_SDA = 17,
> +	MX50_PAD_I2C2_SCL = 18,
> +	MX50_PAD_I2C2_SDA = 19,
> +	MX50_PAD_I2C3_SCL = 20,
> +	MX50_PAD_I2C3_SDA = 21,
> +	MX50_PAD_PWM1 = 22,
> +	MX50_PAD_PWM2 = 23,
> +	MX50_PAD_0WIRE = 24,
> +	MX50_PAD_EPITO = 25,
> +	MX50_PAD_WDOG = 26,
> +	MX50_PAD_SSI_TXFS = 27,
> +	MX50_PAD_SSI_TXC = 28,
> +	MX50_PAD_SSI_TXD = 29,
> +	MX50_PAD_SSI_RXD = 30,
> +	MX50_PAD_SSI_RXF = 31,
> +	MX50_PAD_SSI_RXC = 32,
> +	MX50_PAD_UART1_TXD = 33,
> +	MX50_PAD_UART1_RXD = 34,
> +	MX50_PAD_UART1_CTS = 35,
> +	MX50_PAD_UART1_RTS = 36,
> +	MX50_PAD_UART2_TXD = 37,
> +	MX50_PAD_UART2_RXD = 38,
> +	MX50_PAD_UART2_CTS = 39,
> +	MX50_PAD_UART2_RTS = 40,
> +	MX50_PAD_UART3_TXD = 41,
> +	MX50_PAD_UART3_RXD = 42,
> +	MX50_PAD_UART4_TXD = 43,
> +	MX50_PAD_UART4_RXD = 44,
> +	MX50_PAD_CSPI_CLK = 45,
> +	MX50_PAD_CSPI_MOSI = 46,
> +	MX50_PAD_CSPI_MISO = 47,
> +	MX50_PAD_CSPI_SS0 = 48,
> +	MX50_PAD_ECSPI1_CLK = 49,
> +	MX50_PAD_ECSPI1_MOSI = 50,
> +	MX50_PAD_ECSPI1_MISO = 51,
> +	MX50_PAD_ECSPI1_SS0 = 52,
> +	MX50_PAD_ECSPI2_CLK = 53,
> +	MX50_PAD_ECSPI2_MOSI = 54,
> +	MX50_PAD_ECSPI2_MISO = 55,
> +	MX50_PAD_ECSPI2_SS0 = 56,
> +	MX50_PAD_SD1_CLK = 57,
> +	MX50_PAD_SD1_CMD = 58,
> +	MX50_PAD_SD1_D0 = 59,
> +	MX50_PAD_SD1_D1 = 60,
> +	MX50_PAD_SD1_D2 = 61,
> +	MX50_PAD_SD1_D3 = 62,
> +	MX50_PAD_SD2_CLK = 63,
> +	MX50_PAD_SD2_CMD = 64,
> +	MX50_PAD_SD2_D0 = 65,
> +	MX50_PAD_SD2_D1 = 66,
> +	MX50_PAD_SD2_D2 = 67,
> +	MX50_PAD_SD2_D3 = 68,
> +	MX50_PAD_SD2_D4 = 69,
> +	MX50_PAD_SD2_D5 = 70,
> +	MX50_PAD_SD2_D6 = 71,
> +	MX50_PAD_SD2_D7 = 72,
> +	MX50_PAD_SD2_WP = 73,
> +	MX50_PAD_SD2_CD = 74,
> +	MX50_PAD_DISP_D0 = 75,
> +	MX50_PAD_DISP_D1 = 76,
> +	MX50_PAD_DISP_D2 = 77,
> +	MX50_PAD_DISP_D3 = 78,
> +	MX50_PAD_DISP_D4 = 79,
> +	MX50_PAD_DISP_D5 = 80,
> +	MX50_PAD_DISP_D6 = 81,
> +	MX50_PAD_DISP_D7 = 82,
> +	MX50_PAD_DISP_WR = 83,
> +	MX50_PAD_DISP_RD = 84,
> +	MX50_PAD_DISP_RS = 85,
> +	MX50_PAD_DISP_CS = 86,
> +	MX50_PAD_DISP_BUSY = 87,
> +	MX50_PAD_DISP_RESET = 88,
> +	MX50_PAD_SD3_CLK = 89,
> +	MX50_PAD_SD3_CMD = 90,
> +	MX50_PAD_SD3_D0 = 91,
> +	MX50_PAD_SD3_D1 = 92,
> +	MX50_PAD_SD3_D2 = 93,
> +	MX50_PAD_SD3_D3 = 94,
> +	MX50_PAD_SD3_D4 = 95,
> +	MX50_PAD_SD3_D5 = 96,
> +	MX50_PAD_SD3_D6 = 97,
> +	MX50_PAD_SD3_D7 = 98,
> +	MX50_PAD_SD3_WP = 99,
> +	MX50_PAD_DISP_D8 = 100,
> +	MX50_PAD_DISP_D9 = 101,
> +	MX50_PAD_DISP_D10 = 102,
> +	MX50_PAD_DISP_D11 = 103,
> +	MX50_PAD_DISP_D12 = 104,
> +	MX50_PAD_DISP_D13 = 105,
> +	MX50_PAD_DISP_D14 = 106,
> +	MX50_PAD_DISP_D15 = 107,
> +	MX50_PAD_EPDC_D0 = 108,
> +	MX50_PAD_EPDC_D1 = 109,
> +	MX50_PAD_EPDC_D2 = 110,
> +	MX50_PAD_EPDC_D3 = 111,
> +	MX50_PAD_EPDC_D4 = 112,
> +	MX50_PAD_EPDC_D5 = 113,
> +	MX50_PAD_EPDC_D6 = 114,
> +	MX50_PAD_EPDC_D7 = 115,
> +	MX50_PAD_EPDC_D8 = 116,
> +	MX50_PAD_EPDC_D9 = 117,
> +	MX50_PAD_EPDC_D10 = 118,
> +	MX50_PAD_EPDC_D11 = 119,
> +	MX50_PAD_EPDC_D12 = 120,
> +	MX50_PAD_EPDC_D13 = 121,
> +	MX50_PAD_EPDC_D14 = 122,
> +	MX50_PAD_EPDC_D15 = 123,
> +	MX50_PAD_EPDC_GDCLK = 124,
> +	MX50_PAD_EPDC_GDSP = 125,
> +	MX50_PAD_EPDC_GDOE = 126,
> +	MX50_PAD_EPDC_GDRL = 127,
> +	MX50_PAD_EPDC_SDCLK = 128,
> +	MX50_PAD_EPDC_SDOEZ = 129,
> +	MX50_PAD_EPDC_SDOED = 130,
> +	MX50_PAD_EPDC_SDOE = 131,
> +	MX50_PAD_EPDC_SDLE = 132,
> +	MX50_PAD_EPDC_SDCLKN = 133,
> +	MX50_PAD_EPDC_SDSHR = 134,
> +	MX50_PAD_EPDC_PWRCOM = 135,
> +	MX50_PAD_EPDC_PWRSTAT = 136,
> +	MX50_PAD_EPDC_PWRCTRL0 = 137,
> +	MX50_PAD_EPDC_PWRCTRL1 = 138,
> +	MX50_PAD_EPDC_PWRCTRL2 = 139,
> +	MX50_PAD_EPDC_PWRCTRL3 = 140,
> +	MX50_PAD_EPDC_VCOM0 = 141,
> +	MX50_PAD_EPDC_VCOM1 = 142,
> +	MX50_PAD_EPDC_BDR0 = 143,
> +	MX50_PAD_EPDC_BDR1 = 144,
> +	MX50_PAD_EPDC_SDCE0 = 145,
> +	MX50_PAD_EPDC_SDCE1 = 146,
> +	MX50_PAD_EPDC_SDCE2 = 147,
> +	MX50_PAD_EPDC_SDCE3 = 148,
> +	MX50_PAD_EPDC_SDCE4 = 149,
> +	MX50_PAD_EPDC_SDCE5 = 150,
> +	MX50_PAD_EIM_DA0 = 151,
> +	MX50_PAD_EIM_DA1 = 152,
> +	MX50_PAD_EIM_DA2 = 153,
> +	MX50_PAD_EIM_DA3 = 154,
> +	MX50_PAD_EIM_DA4 = 155,
> +	MX50_PAD_EIM_DA5 = 156,
> +	MX50_PAD_EIM_DA6 = 157,
> +	MX50_PAD_EIM_DA7 = 158,
> +	MX50_PAD_EIM_DA8 = 159,
> +	MX50_PAD_EIM_DA9 = 160,
> +	MX50_PAD_EIM_DA10 = 161,
> +	MX50_PAD_EIM_DA11 = 162,
> +	MX50_PAD_EIM_DA12 = 163,
> +	MX50_PAD_EIM_DA13 = 164,
> +	MX50_PAD_EIM_DA14 = 165,
> +	MX50_PAD_EIM_DA15 = 166,
> +	MX50_PAD_EIM_CS2 = 167,
> +	MX50_PAD_EIM_CS1 = 168,
> +	MX50_PAD_EIM_CS0 = 169,
> +	MX50_PAD_EIM_EB0 = 170,
> +	MX50_PAD_EIM_EB1 = 171,
> +	MX50_PAD_EIM_WAIT = 172,
> +	MX50_PAD_EIM_BCLK = 173,
> +	MX50_PAD_EIM_RDY = 174,
> +	MX50_PAD_EIM_OE = 175,
> +	MX50_PAD_EIM_RW = 176,
> +	MX50_PAD_EIM_LBA = 177,
> +	MX50_PAD_EIM_CRE = 178,
> +};
> +
> +/* Pad names for the pinmux subsystem */
> +static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
> +	IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
> +	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
> +	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
> +	IMX_PINCTRL_PIN(MX50_PAD_PWM1),
> +	IMX_PINCTRL_PIN(MX50_PAD_PWM2),
> +	IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPITO),
> +	IMX_PINCTRL_PIN(MX50_PAD_WDOG),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
> +	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
> +	IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
> +	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
> +	IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
> +	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
> +	IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
> +	IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
> +	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
> +	IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
> +};
> +
> +static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
> +	.pins = imx50_pinctrl_pads,
> +	.npins = ARRAY_SIZE(imx50_pinctrl_pads),
> +};
> +
> +static struct of_device_id imx50_pinctrl_of_match[] = {
> +	{ .compatible = "fsl,imx50-iomuxc", },
> +	{ /* sentinel */ }
> +};
> +
> +static int imx50_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
> +}
> +
> +static struct platform_driver imx50_pinctrl_driver = {
> +	.driver = {
> +		.name = "imx50-pinctrl",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
> +	},
> +	.probe = imx50_pinctrl_probe,
> +	.remove = imx_pinctrl_remove,
> +};
> +
> +static int __init imx50_pinctrl_init(void)
> +{
> +	return platform_driver_register(&imx50_pinctrl_driver);
> +}
> +arch_initcall(imx50_pinctrl_init);
> +
> +static void __exit imx50_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&imx50_pinctrl_driver);
> +}
> +module_exit(imx50_pinctrl_exit);
> +MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 1.8.1.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 4/8] ARM: imx: add support code for IMX50 based machines

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add machine support code for the Freescale IMX50 SoC.

It is very similar to the Freescale IMX53, it contains many of the same
periperhal hardware modules, at the same address offsets as the IMX53.
(Notable exceptions are that the IMX50 contains no CAN bus hardware, less
GPIO, no VPU, it does contain an Electrophoretic display controller though).

So this support code just uses the IMX53 definitions as they are today.
We can add the extra IMX50 definitions in the future when required.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/mach-imx/Makefile     |  1 +
 arch/arm/mach-imx/mach-imx50.c | 52 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx50.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5383c58..9d94f47 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
new file mode 100644
index 0000000..4ac1b91
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "common.h"
+#include "mx53.h"
+
+static void __init imx50_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *imx50_dt_board_compat[] __initdata = {
+	"fsl,imx50",
+	NULL
+};
+
+static void __init imx50_timer_init(void)
+{
+	mx50_clocks_init_dt();
+}
+
+DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
+	.map_io		= mx53_map_io,
+	.init_early	= imx53_init_early,
+	.init_irq	= mx53_init_irq,
+	.handle_irq	= imx53_handle_irq,
+	.init_time	= imx50_timer_init,
+	.init_machine	= imx50_dt_init,
+	.init_late	= imx53_init_late,
+	.dt_compat	= imx50_dt_board_compat,
+	.restart	= mxc_restart,
+MACHINE_END
-- 
1.8.1.4

[PATCH 4/8] ARM: imx: add support code for IMX50 based machines

[Rob Herring]

On Fri, Oct 18, 2013 at 1:04 AM,  <gerg@uclinux.org> wrote:
> From: Greg Ungerer <gerg@uclinux.org>
>
> Add machine support code for the Freescale IMX50 SoC.
>
> It is very similar to the Freescale IMX53, it contains many of the same
> periperhal hardware modules, at the same address offsets as the IMX53.
> (Notable exceptions are that the IMX50 contains no CAN bus hardware, less
> GPIO, no VPU, it does contain an Electrophoretic display controller though).
>
> So this support code just uses the IMX53 definitions as they are today.
> We can add the extra IMX50 definitions in the future when required.
>
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/mach-imx/Makefile     |  1 +
>  arch/arm/mach-imx/mach-imx50.c | 52 ++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
>  create mode 100644 arch/arm/mach-imx/mach-imx50.c
>
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 5383c58..9d94f47 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
>  obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
>
>  obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
> +obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
>  obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>
>  obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
> diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
> new file mode 100644
> index 0000000..4ac1b91
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-imx50.c
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +
> +#include "common.h"
> +#include "mx53.h"
> +
> +static void __init imx50_dt_init(void)
> +{
> +       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +static const char *imx50_dt_board_compat[] __initdata = {
> +       "fsl,imx50",
> +       NULL
> +};
> +
> +static void __init imx50_timer_init(void)
> +{
> +       mx50_clocks_init_dt();
> +}
> +
> +DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
> +       .map_io         = mx53_map_io,
> +       .init_early     = imx53_init_early,
> +       .init_irq       = mx53_init_irq,
> +       .handle_irq     = imx53_handle_irq,
> +       .init_time      = imx50_timer_init,
> +       .init_machine   = imx50_dt_init,
> +       .init_late      = imx53_init_late,
> +       .dt_compat      = imx50_dt_board_compat,
> +       .restart        = mxc_restart,
> +MACHINE_END

This seems like a lot of duplication. It seems like mx53 and mx50
could be combined into a single machine_desc. init_time should not be
needed in 3.13.

[PATCH 4/8] ARM: imx: add support code for IMX50 based machines

[Greg Ungerer]

Hi Rob,

On 24/10/13 21:11, Rob Herring wrote:
> On Fri, Oct 18, 2013 at 1:04 AM,  <gerg@uclinux.org> wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> Add machine support code for the Freescale IMX50 SoC.
>>
>> It is very similar to the Freescale IMX53, it contains many of the same
>> periperhal hardware modules, at the same address offsets as the IMX53.
>> (Notable exceptions are that the IMX50 contains no CAN bus hardware, less
>> GPIO, no VPU, it does contain an Electrophoretic display controller though).
>>
>> So this support code just uses the IMX53 definitions as they are today.
>> We can add the extra IMX50 definitions in the future when required.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>>  arch/arm/mach-imx/Makefile     |  1 +
>>  arch/arm/mach-imx/mach-imx50.c | 52 ++++++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 53 insertions(+)
>>  create mode 100644 arch/arm/mach-imx/mach-imx50.c
>>
>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>> index 5383c58..9d94f47 100644
>> --- a/arch/arm/mach-imx/Makefile
>> +++ b/arch/arm/mach-imx/Makefile
>> @@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
>>  obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
>>
>>  obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
>> +obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
>>  obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>>
>>  obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
>> diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
>> new file mode 100644
>> index 0000000..4ac1b91
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mach-imx50.c
>> @@ -0,0 +1,52 @@
>> +/*
>> + * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
>> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> + * Copyright 2011 Linaro Ltd.
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/irq.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +#include <asm/mach/arch.h>
>> +#include <asm/mach/time.h>
>> +
>> +#include "common.h"
>> +#include "mx53.h"
>> +
>> +static void __init imx50_dt_init(void)
>> +{
>> +       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>> +}
>> +
>> +static const char *imx50_dt_board_compat[] __initdata = {
>> +       "fsl,imx50",
>> +       NULL
>> +};
>> +
>> +static void __init imx50_timer_init(void)
>> +{
>> +       mx50_clocks_init_dt();
>> +}
>> +
>> +DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
>> +       .map_io         = mx53_map_io,
>> +       .init_early     = imx53_init_early,
>> +       .init_irq       = mx53_init_irq,
>> +       .handle_irq     = imx53_handle_irq,
>> +       .init_time      = imx50_timer_init,
>> +       .init_machine   = imx50_dt_init,
>> +       .init_late      = imx53_init_late,
>> +       .dt_compat      = imx50_dt_board_compat,
>> +       .restart        = mxc_restart,
>> +MACHINE_END
> 
> This seems like a lot of duplication. It seems like mx53 and mx50
> could be combined into a single machine_desc. init_time should not be
> needed in 3.13.

Are you suggesting that "fsl,imx50" be added to the board compat list
in mach-imx53.c instead?

Regards
Greg

[PATCH 4/8] ARM: imx: add support code for IMX50 based machines

[Rob Herring]

On Mon, Oct 28, 2013 at 1:38 AM, Greg Ungerer <gerg@uclinux.org> wrote:
> Hi Rob,
>
> On 24/10/13 21:11, Rob Herring wrote:
>> On Fri, Oct 18, 2013 at 1:04 AM,  <gerg@uclinux.org> wrote:
>>> From: Greg Ungerer <gerg@uclinux.org>
>>>
>>> Add machine support code for the Freescale IMX50 SoC.


>>> +DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
>>> +       .map_io         = mx53_map_io,
>>> +       .init_early     = imx53_init_early,
>>> +       .init_irq       = mx53_init_irq,
>>> +       .handle_irq     = imx53_handle_irq,
>>> +       .init_time      = imx50_timer_init,
>>> +       .init_machine   = imx50_dt_init,
>>> +       .init_late      = imx53_init_late,
>>> +       .dt_compat      = imx50_dt_board_compat,
>>> +       .restart        = mxc_restart,
>>> +MACHINE_END
>>
>> This seems like a lot of duplication. It seems like mx53 and mx50
>> could be combined into a single machine_desc. init_time should not be
>> needed in 3.13.
>
> Are you suggesting that "fsl,imx50" be added to the board compat list
> in mach-imx53.c instead?

Yes, that would be at least part of it. I'd guess a bit more than that
is needed.

Rob

[PATCH 5/8] ARM: imx: allow configuration of the IMX50 SoC

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Allow the Freescale IMX50 SoC support code to be configured on.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/mach-imx/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 29a8af6..8497b26 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -772,6 +772,15 @@ endchoice
 
 comment "Device tree only"
 
+config	SOC_IMX50
+	bool "i.MX50 support"
+	select HAVE_IMX_SRC
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select SOC_IMX5
+
+	help
+	  This enables support for Freescale i.MX50 processor.
+
 config	SOC_IMX53
 	bool "i.MX53 support"
 	select HAVE_IMX_SRC
-- 
1.8.1.4

[PATCH 5/8] ARM: imx: allow configuration of the IMX50 SoC

[Shawn Guo]

On Fri, Oct 18, 2013 at 04:04:17PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Allow the Freescale IMX50 SoC support code to be configured on.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/mach-imx/Kconfig | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 29a8af6..8497b26 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -772,6 +772,15 @@ endchoice
>  
>  comment "Device tree only"
>  
> +config	SOC_IMX50
> +	bool "i.MX50 support"
> +	select HAVE_IMX_SRC
> +	select IMX_HAVE_PLATFORM_IMX2_WDT

Do you really need to select IMX_HAVE_PLATFORM_IMX2_WDT?

Shawn

> +	select SOC_IMX5
> +
> +	help
> +	  This enables support for Freescale i.MX50 processor.
> +
>  config	SOC_IMX53
>  	bool "i.MX53 support"
>  	select HAVE_IMX_SRC
> -- 
> 1.8.1.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 6/8] ARM: dts: imx: add device tree pin definitions for the IMX50

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add device tree pin function definitions for the Freescale IMX50 SoC.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/boot/dts/imx50-pinfunc.h | 923 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 923 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx50-pinfunc.h

diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h
new file mode 100644
index 0000000..97e6e7f
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-pinfunc.h
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX50_PINFUNC_H
+#define __DTS_IMX50_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX50_PAD_KEY_COL0__KPP_COL_0				0x020 0x2cc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL0__GPIO4_0				0x020 0x2cc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE			0x020 0x2cc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL0__CTI_TRIGIN7				0x020 0x2cc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY			0x020 0x2cc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW0__KPP_ROW_0				0x024 0x2d0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW0__GPIO4_1				0x024 0x2d0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE			0x024 0x2d0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7			0x024 0x2d0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID			0x024 0x2d0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL1__KPP_COL_1				0x028 0x2d4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL1__GPIO4_2				0x028 0x2d4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0			0x028 0x2d4 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6			0x028 0x2d4 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE			0x028 0x2d4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW1__KPP_ROW_1				0x02c 0x2d8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW1__GPIO4_3				0x02c 0x2d8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1			0x02c 0x2d8 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7			0x02c 0x2d8 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR			0x02c 0x2d8 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL2__KPP_COL_1				0x030 0x2dc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL2__GPIO4_4				0x030 0x2dc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2			0x030 0x2dc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6				0x030 0x2dc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK			0x030 0x2dc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW2__KPP_ROW_2				0x034 0x2e0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW2__GPIO4_5				0x034 0x2e0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3			0x034 0x2e0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7				0x034 0x2e0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0			0x034 0x2e0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL3__KPP_COL_2				0x038 0x2e4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL3__GPIO4_6				0x038 0x2e4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0			0x038 0x2e4 0x7b4 0x2 0x0
+#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0			0x038 0x2e4 0x7b8 0x6 0x0
+#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1			0x038 0x2e4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW3__KPP_ROW_3				0x03c 0x2e8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW3__GPIO4_7				0x03c 0x2e8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS			0x03c 0x2e8 0x7b0 0x2 0x0
+#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1			0x03c 0x2e8 0x7bc 0x6 0x0
+#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID			0x03c 0x2e8 0x000 0x7 0x0
+#define MX50_PAD_I2C1_SCL__I2C1_SCL				0x040 0x2ec 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SCL__GPIO6_18				0x040 0x2ec 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX			0x040 0x2ec 0x7cc 0x2 0x0
+#define MX50_PAD_I2C1_SDA__I2C1_SDA				0x044 0x2f0 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SDA__GPIO6_19				0x044 0x2f0 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX			0x044 0x2f0 0x7cc 0x2 0x1
+#define MX50_PAD_I2C2_SCL__I2C2_SCL				0x048 0x2f4 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SCL__GPIO6_20				0x048 0x2f4 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SCL__UART2_CTS				0x048 0x2f4 0x000 0x2 0x0
+#define MX50_PAD_I2C2_SDA__I2C2_SDA				0x04c 0x2f8 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SDA__GPIO6_21				0x04c 0x2f8 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SDA__UART2_RTS				0x04c 0x2f8 0x7c8 0x2 0x1
+#define MX50_PAD_I2C3_SCL__I2C3_SCL				0x050 0x2fc 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SCL__GPIO6_22				0x050 0x2fc 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SCL__FEC_MDC				0x050 0x2fc 0x000 0x2 0x0
+#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY				0x050 0x2fc 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SCL__GPT_CAPIN1				0x050 0x2fc 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0		0x050 0x2fc 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC			0x050 0x2fc 0x7e8 0x7 0x0
+#define MX50_PAD_I2C3_SDA__I2C3_SDA				0x054 0x300 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SDA__GPIO6_23				0x054 0x300 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SDA__FEC_MDIO				0x054 0x300 0x774 0x2 0x0
+#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT			0x054 0x300 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB			0x054 0x300 0x000 0x4 0x0
+#define MX50_PAD_I2C3_SDA__GPT_CAPIN2				0x054 0x300 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1		0x054 0x300 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR			0x054 0x300 0x000 0x7 0x0
+#define MX50_PAD_PWM1__PWM1_PWMO				0x058 0x304 0x000 0x0 0x0
+#define MX50_PAD_PWM1__GPIO6_24					0x058 0x304 0x000 0x1 0x0
+#define MX50_PAD_PWM1__USBOH1_USBOTG_OC				0x058 0x304 0x7e8 0x2 0x1
+#define MX50_PAD_PWM1__GPT_CMPOUT1				0x058 0x304 0x000 0x5 0x0
+#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2		0x058 0x304 0x000 0x6 0x0
+#define MX50_PAD_PWM1__SJC_FAIL					0x058 0x304 0x000 0x7 0x0
+#define MX50_PAD_PWM2__PWM2_PWMO				0x05c 0x308 0x000 0x0 0x0
+#define MX50_PAD_PWM2__GPIO6_25					0x05c 0x308 0x000 0x1 0x0
+#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR			0x05c 0x308 0x000 0x2 0x0
+#define MX50_PAD_PWM2__GPT_CMPOUT2				0x05c 0x308 0x000 0x5 0x0
+#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3		0x05c 0x308 0x000 0x6 0x0
+#define MX50_PAD_PWM2__SRC_ANY_PU_RST				0x05c 0x308 0x000 0x7 0x0
+#define MX50_PAD_OWIRE__OWIRE_LINE				0x060 0x30c 0x000 0x0 0x0
+#define MX50_PAD_OWIRE__GPIO6_26				0x060 0x30c 0x000 0x1 0x0
+#define MX50_PAD_OWIRE__USBOH1_USBH1_OC				0x060 0x30c 0x000 0x2 0x0
+#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK			0x060 0x30c 0x000 0x3 0x0
+#define MX50_PAD_OWIRE__EPDC_PWRIRQ				0x060 0x30c 0x000 0x4 0x0
+#define MX50_PAD_OWIRE__GPT_CMPOUT3				0x060 0x30c 0x000 0x5 0x0
+#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4		0x060 0x30c 0x000 0x6 0x0
+#define MX50_PAD_OWIRE__SJC_JTAG_ACT				0x060 0x30c 0x000 0x7 0x0
+#define MX50_PAD_EPITO__EPIT1_EPITO				0x064 0x310 0x000 0x0 0x0
+#define MX50_PAD_EPITO__GPIO6_27				0x064 0x310 0x000 0x1 0x0
+#define MX50_PAD_EPITO__USBOH1_USBH1_PWR			0x064 0x310 0x000 0x2 0x0
+#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK			0x064 0x310 0x000 0x3 0x0
+#define MX50_PAD_EPITO__DPLLIP1_TOG_EN				0x064 0x310 0x000 0x4 0x0
+#define MX50_PAD_EPITO__GPT_CLK_IN				0x064 0x310 0x000 0x5 0x0
+#define MX50_PAD_EPITO__PMU_IRQ_B				0x064 0x310 0x000 0x6 0x0
+#define MX50_PAD_EPITO__SJC_DE_B				0x064 0x310 0x000 0x7 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_B				0x068 0x314 0x000 0x0 0x0
+#define MX50_PAD_WDOG__GPIO6_28					0x068 0x314 0x000 0x1 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB			0x068 0x314 0x000 0x2 0x0
+#define MX50_PAD_WDOG__CCM_XTAL32K				0x068 0x314 0x000 0x6 0x0
+#define MX50_PAD_WDOG__SJC_DONE					0x068 0x314 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS			0x06c 0x318 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXFS__GPIO6_0				0x06c 0x318 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1			0x06c 0x318 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8			0x06c 0x318 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC			0x070 0x31c 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXC__GPIO6_1				0x070 0x31c 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0			0x070 0x31c 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9			0x070 0x31c 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD			0x074 0x320 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXD__GPIO6_2				0x074 0x320 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXD__CSPI_RDY				0x074 0x320 0x6e8 0x4 0x0
+#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10			0x074 0x320 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD			0x078 0x324 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXD__GPIO6_3				0x078 0x324 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXD__CSPI_SS3				0x078 0x324 0x6f4 0x4 0x0
+#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11			0x078 0x324 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS			0x07c 0x328 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXFS__GPIO6_4				0x07c 0x328 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX			0x07c 0x328 0x7e4 0x2 0x0
+#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6				0x07c 0x328 0x804 0x3 0x0
+#define MX50_PAD_SSI_RXFS__CSPI_SS2				0x07c 0x328 0x6f0 0x4 0x0
+#define MX50_PAD_SSI_RXFS__FEC_COL				0x07c 0x328 0x770 0x5 0x0
+#define MX50_PAD_SSI_RXFS__FEC_MDC				0x07c 0x328 0x000 0x6 0x0
+#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12			0x07c 0x328 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC			0x080 0x32c 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXC__GPIO6_5				0x080 0x32c 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXC__UART5_RXD_MUX				0x080 0x32c 0x7e4 0x2 0x1
+#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7				0x080 0x32c 0x808 0x3 0x0
+#define MX50_PAD_SSI_RXC__CSPI_SS1				0x080 0x32c 0x6ec 0x4 0x0
+#define MX50_PAD_SSI_RXC__FEC_RX_CLK				0x080 0x32c 0x780 0x5 0x0
+#define MX50_PAD_SSI_RXC__FEC_MDIO				0x080 0x32c 0x774 0x6 0x1
+#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13			0x080 0x32c 0x000 0x7 0x0
+#define MX50_PAD_UART1_TXD__UART1_TXD_MUX			0x084 0x330 0x7c4 0x0 0x0
+#define MX50_PAD_UART1_TXD__GPIO6_6				0x084 0x330 0x000 0x1 0x0
+#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14			0x084 0x330 0x000 0x7 0x0
+#define MX50_PAD_UART1_RXD__UART1_RXD_MUX			0x088 0x334 0x7c4 0x0 0x1
+#define MX50_PAD_UART1_RXD__GPIO6_7				0x088 0x334 0x000 0x1 0x0
+#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15			0x088 0x334 0x000 0x7 0x0
+#define MX50_PAD_UART1_CTS__UART1_CTS				0x08c 0x338 0x000 0x0 0x0
+#define MX50_PAD_UART1_CTS__GPIO6_8				0x08c 0x338 0x000 0x1 0x0
+#define MX50_PAD_UART1_CTS__UART5_TXD_MUX			0x08c 0x338 0x7e4 0x2 0x2
+#define MX50_PAD_UART1_CTS__ESDHC4_DAT4				0x08c 0x338 0x760 0x4 0x0
+#define MX50_PAD_UART1_CTS__ESDHC4_CMD				0x08c 0x338 0x74c 0x5 0x0
+#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8			0x08c 0x338 0x000 0x7 0x0
+#define MX50_PAD_UART1_RTS__UART1_RTS				0x090 0x33c 0x7c0 0x0 0x3
+#define MX50_PAD_UART1_RTS__GPIO6_9				0x090 0x33c 0x000 0x1 0x0
+#define MX50_PAD_UART1_RTS__UART5_RXD_MUX			0x090 0x33c 0x7e4 0x2 0x3
+#define MX50_PAD_UART1_RTS__ESDHC4_DAT5				0x090 0x33c 0x764 0x4 0x0
+#define MX50_PAD_UART1_RTS__ESDHC4_CLK				0x090 0x33c 0x748 0x5 0x0
+#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9			0x090 0x33c 0x000 0x7 0x0
+#define MX50_PAD_UART2_TXD__UART2_TXD_MUX			0x094 0x340 0x7cc 0x0 0x2
+#define MX50_PAD_UART2_TXD__GPIO6_10				0x094 0x340 0x000 0x1 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT6				0x094 0x340 0x768 0x4 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT4				0x094 0x340 0x760 0x5 0x1
+#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10			0x094 0x340 0x000 0x7 0x0
+#define MX50_PAD_UART2_RXD__UART2_RXD_MUX			0x098 0x344 0x7cc 0x0 0x3
+#define MX50_PAD_UART2_RXD__GPIO6_11				0x098 0x344 0x000 0x1 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT7				0x098 0x344 0x76c 0x4 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT5				0x098 0x344 0x764 0x5 0x1
+#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11			0x098 0x344 0x000 0x7 0x0
+#define MX50_PAD_UART2_CTS__UART2_CTS				0x09c 0x348 0x000 0x0 0x0
+#define MX50_PAD_UART2_CTS__GPIO6_12				0x09c 0x348 0x000 0x1 0x0
+#define MX50_PAD_UART2_CTS__ESDHC4_CMD				0x09c 0x348 0x74c 0x4 0x1
+#define MX50_PAD_UART2_CTS__ESDHC4_DAT6				0x09c 0x348 0x768 0x5 0x1
+#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12			0x09c 0x348 0x000 0x7 0x0
+#define MX50_PAD_UART2_RTS__UART2_RTS				0x0a0 0x34c 0x7c8 0x0 0x2
+#define MX50_PAD_UART2_RTS__GPIO6_13				0x0a0 0x34c 0x000 0x1 0x0
+#define MX50_PAD_UART2_RTS__ESDHC4_CLK				0x0a0 0x34c 0x748 0x4 0x1
+#define MX50_PAD_UART2_RTS__ESDHC4_DAT7				0x0a0 0x34c 0x76c 0x5 0x1
+#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13			0x0a0 0x34c 0x000 0x7 0x0
+#define MX50_PAD_UART3_TXD__UART3_TXD_MUX			0x0a4 0x350 0x7d4 0x0 0x0
+#define MX50_PAD_UART3_TXD__GPIO6_14				0x0a4 0x350 0x000 0x1 0x0
+#define MX50_PAD_UART3_TXD__ESDHC1_DAT4				0x0a4 0x350 0x000 0x3 0x0
+#define MX50_PAD_UART3_TXD__ESDHC4_DAT0				0x0a4 0x350 0x000 0x4 0x0
+#define MX50_PAD_UART3_TXD__ESDHC2_WP				0x0a4 0x350 0x744 0x5 0x0
+#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12			0x0a4 0x350 0x81c 0x6 0x0
+#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14			0x0a4 0x350 0x000 0x7 0x0
+#define MX50_PAD_UART3_RXD__UART3_RXD_MUX			0x0a8 0x354 0x7d4 0x0 0x1
+#define MX50_PAD_UART3_RXD__GPIO6_15				0x0a8 0x354 0x000 0x1 0x0
+#define MX50_PAD_UART3_RXD__ESDHC1_DAT5				0x0a8 0x354 0x000 0x3 0x0
+#define MX50_PAD_UART3_RXD__ESDHC4_DAT1				0x0a8 0x354 0x754 0x4 0x0
+#define MX50_PAD_UART3_RXD__ESDHC2_CD				0x0a8 0x354 0x740 0x5 0x0
+#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13			0x0a8 0x354 0x820 0x6 0x0
+#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15			0x0a8 0x354 0x000 0x7 0x0
+#define MX50_PAD_UART4_TXD__UART4_TXD_MUX			0x0ac 0x358 0x7dc 0x0 0x0
+#define MX50_PAD_UART4_TXD__GPIO6_16				0x0ac 0x358 0x000 0x1 0x0
+#define MX50_PAD_UART4_TXD__UART3_CTS				0x0ac 0x358 0x7d0 0x2 0x0
+#define MX50_PAD_UART4_TXD__ESDHC1_DAT6				0x0ac 0x358 0x000 0x3 0x0
+#define MX50_PAD_UART4_TXD__ESDHC4_DAT2				0x0ac 0x358 0x758 0x4 0x0
+#define MX50_PAD_UART4_TXD__ESDHC2_LCTL				0x0ac 0x358 0x000 0x5 0x0
+#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14			0x0ac 0x358 0x824 0x6 0x0
+#define MX50_PAD_UART4_RXD__UART4_RXD_MUX			0x0b0 0x35c 0x7dc 0x0 0x1
+#define MX50_PAD_UART4_RXD__GPIO6_17				0x0b0 0x35c 0x000 0x1 0x0
+#define MX50_PAD_UART4_RXD__UART3_RTS				0x0b0 0x35c 0x7d0 0x2 0x1
+#define MX50_PAD_UART4_RXD__ESDHC1_DAT7				0x0b0 0x35c 0x000 0x3 0x0
+#define MX50_PAD_UART4_RXD__ESDHC4_DAT3				0x0b0 0x35c 0x75c 0x4 0x0
+#define MX50_PAD_UART4_RXD__ESDHC1_LCTL				0x0b0 0x35c 0x000 0x5 0x0
+#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15			0x0b0 0x35c 0x828 0x6 0x0
+#define MX50_PAD_CSPI_SCLK__CSPI_SCLK				0x0b4 0x360 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SCLK__GPIO4_8				0x0b4 0x360 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MOSI__CSPI_MOSI				0x0b8 0x364 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MOSI__GPIO4_9				0x0b8 0x364 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MISO__CSPI_MISO				0x0bc 0x368 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MISO__GPIO4_10				0x0bc 0x368 0x000 0x1 0x0
+#define MX50_PAD_CSPI_SS0__CSPI_SS0				0x0c0 0x36c 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SS0__GPIO4_11				0x0c0 0x36c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK			0x0c4 0x370 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SCLK__GPIO4_12				0x0c4 0x370 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY				0x0c4 0x370 0x6e8 0x2 0x1
+#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY			0x0c4 0x370 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SCLK__UART3_RTS				0x0c4 0x370 0x7d0 0x4 0x2
+#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6			0x0c4 0x370 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8			0x0c4 0x370 0x80c 0x7 0x0
+#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI			0x0c8 0x374 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MOSI__GPIO4_13				0x0c8 0x374 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1				0x0c8 0x374 0x6ec 0x2 0x1
+#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1			0x0c8 0x374 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS				0x0c8 0x374 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7			0x0c8 0x374 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9			0x0c8 0x374 0x810 0x7 0x0
+#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO			0x0cc 0x378 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MISO__GPIO4_14				0x0cc 0x378 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MISO__CSPI_SS2				0x0cc 0x378 0x6f0 0x2 0x1
+#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2			0x0cc 0x378 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MISO__UART4_RTS				0x0cc 0x378 0x7d8 0x4 0x0
+#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8			0x0cc 0x378 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10			0x0cc 0x378 0x814 0x7 0x0
+#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0				0x0d0 0x37c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SS0__GPIO4_15				0x0d0 0x37c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SS0__CSPI_SS3				0x0d0 0x37c 0x6f4 0x2 0x1
+#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3				0x0d0 0x37c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS				0x0d0 0x37c 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9			0x0d0 0x37c 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11			0x0d0 0x37c 0x818 0x7 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK			0x0d4 0x380 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SCLK__GPIO4_16				0x0d4 0x380 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN			0x0d4 0x380 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY			0x0d4 0x380 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SCLK__UART5_RTS				0x0d4 0x380 0x7e0 0x4 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK			0x0d4 0x380 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4			0x0d4 0x380 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8			0x0d4 0x380 0x80c 0x7 0x1
+#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI			0x0d8 0x384 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MOSI__GPIO4_17				0x0d8 0x384 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E			0x0d8 0x384 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1			0x0d8 0x384 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS				0x0d8 0x384 0x7e0 0x4 0x1
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE			0x0d8 0x384 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5			0x0d8 0x384 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9			0x0d8 0x384 0x810 0x7 0x1
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO			0x0dc 0x388 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MISO__GPIO4_18				0x0dc 0x388 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS				0x0dc 0x388 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2			0x0dc 0x388 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX			0x0dc 0x388 0x7e4 0x4 0x4
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC			0x0dc 0x388 0x73c 0x5 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6			0x0dc 0x388 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10			0x0dc 0x388 0x814 0x7 0x1
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0				0x0e0 0x38c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SS0__GPIO4_19				0x0e0 0x38c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS				0x0e0 0x38c 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3				0x0e0 0x38c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX			0x0e0 0x38c 0x7e4 0x4 0x5
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC			0x0e0 0x38c 0x6f8 0x5 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7			0x0e0 0x38c 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11			0x0e0 0x38c 0x818 0x7 0x1
+#define MX50_PAD_SD1_CLK__ESDHC1_CLK				0x0e4 0x390 0x000 0x0 0x0
+#define MX50_PAD_SD1_CLK__GPIO5_0				0x0e4 0x390 0x000 0x1 0x0
+#define MX50_PAD_SD1_CLK__CCM_CLKO				0x0e4 0x390 0x000 0x7 0x0
+#define MX50_PAD_SD1_CMD__ESDHC1_CMD				0x0e8 0x394 0x000 0x0 0x0
+#define MX50_PAD_SD1_CMD__GPIO5_1				0x0e8 0x394 0x000 0x1 0x0
+#define MX50_PAD_SD1_CMD__CCM_CLKO2				0x0e8 0x394 0x000 0x7 0x0
+#define MX50_PAD_SD1_D0__ESDHC1_DAT0				0x0ec 0x398 0x000 0x0 0x0
+#define MX50_PAD_SD1_D0__GPIO5_2				0x0ec 0x398 0x000 0x1 0x0
+#define MX50_PAD_SD1_D0__CCM_PLL1_BYP				0x0ec 0x398 0x6dc 0x7 0x0
+#define MX50_PAD_SD1_D1__ESDHC1_DAT1				0x0f0 0x39c 0x000 0x0 0x0
+#define MX50_PAD_SD1_D1__GPIO5_3				0x0f0 0x39c 0x000 0x1 0x0
+#define MX50_PAD_SD1_D1__CCM_PLL2_BYP				0x0f0 0x39c 0x000 0x7 0x0
+#define MX50_PAD_SD1_D2__ESDHC1_DAT2				0x0f4 0x3a0 0x000 0x0 0x0
+#define MX50_PAD_SD1_D2__GPIO5_4				0x0f4 0x3a0 0x000 0x1 0x0
+#define MX50_PAD_SD1_D2__CCM_PLL3_BYP				0x0f4 0x3a0 0x6e4 0x7 0x0
+#define MX50_PAD_SD1_D3__ESDHC1_DAT3				0x0f8 0x3a4 0x000 0x0 0x0
+#define MX50_PAD_SD1_D3__GPIO5_5				0x0f8 0x3a4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__ESDHC2_CLK				0x0fc 0x3a8 0x000 0x0 0x0
+#define MX50_PAD_SD2_CLK__GPIO5_6				0x0fc 0x3a8 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__MSHC_SCLK				0x0fc 0x3a8 0x000 0x2 0x0
+#define MX50_PAD_SD2_CMD__ESDHC2_CMD				0x100 0x3ac 0x000 0x0 0x0
+#define MX50_PAD_SD2_CMD__GPIO5_7				0x100 0x3ac 0x000 0x1 0x0
+#define MX50_PAD_SD2_CMD__MSHC_BS				0x100 0x3ac 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__ESDHC2_DAT0				0x104 0x3b0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D0__GPIO5_8				0x104 0x3b0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D0__MSHC_DATA_0				0x104 0x3b0 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__KPP_COL_4				0x104 0x3b0 0x790 0x3 0x0
+#define MX50_PAD_SD2_D1__ESDHC2_DAT1				0x108 0x3b4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D1__GPIO5_9				0x108 0x3b4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D1__MSHC_DATA_1				0x108 0x3b4 0x000 0x2 0x0
+#define MX50_PAD_SD2_D1__KPP_ROW_4				0x108 0x3b4 0x7a0 0x3 0x0
+#define MX50_PAD_SD2_D2__ESDHC2_DAT2				0x10c 0x3b8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D2__GPIO5_10				0x10c 0x3b8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D2__MSHC_DATA_2				0x10c 0x3b8 0x000 0x2 0x0
+#define MX50_PAD_SD2_D2__KPP_COL_5				0x10c 0x3b8 0x794 0x3 0x0
+#define MX50_PAD_SD2_D3__ESDHC2_DAT3				0x110 0x3bc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D3__GPIO5_11				0x110 0x3bc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D3__MSHC_DATA_3				0x110 0x3bc 0x000 0x2 0x0
+#define MX50_PAD_SD2_D3__KPP_ROW_5				0x110 0x3bc 0x7a4 0x3 0x0
+#define MX50_PAD_SD2_D4__ESDHC2_DAT4				0x114 0x3c0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D4__GPIO5_12				0x114 0x3c0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS			0x114 0x3c0 0x6d0 0x2 0x0
+#define MX50_PAD_SD2_D4__KPP_COL_6				0x114 0x3c0 0x798 0x3 0x0
+#define MX50_PAD_SD2_D4__EIM_WEIM_D_0				0x114 0x3c0 0x7ec 0x4 0x0
+#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0				0x114 0x3c0 0x000 0x7 0x0
+#define MX50_PAD_SD2_D5__ESDHC2_DAT5				0x118 0x3c4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D5__GPIO5_13				0x118 0x3c4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC			0x118 0x3c4 0x6cc 0x2 0x0
+#define MX50_PAD_SD2_D5__KPP_ROW_6				0x118 0x3c4 0x7a8 0x3 0x0
+#define MX50_PAD_SD2_D5__EIM_WEIM_D_1				0x118 0x3c4 0x7f0 0x4 0x0
+#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1				0x118 0x3c4 0x000 0x7 0x0
+#define MX50_PAD_SD2_D6__ESDHC2_DAT6				0x11c 0x3c8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D6__GPIO5_14				0x11c 0x3c8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD			0x11c 0x3c8 0x6c4 0x2 0x0
+#define MX50_PAD_SD2_D6__KPP_COL_7				0x11c 0x3c8 0x79c 0x3 0x0
+#define MX50_PAD_SD2_D6__EIM_WEIM_D_2				0x11c 0x3c8 0x7f4 0x4 0x0
+#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2				0x11c 0x3c8 0x000 0x7 0x0
+#define MX50_PAD_SD2_D7__ESDHC2_DAT7				0x120 0x3cc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D7__GPIO5_15				0x120 0x3cc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS			0x120 0x3cc 0x6d8 0x2 0x0
+#define MX50_PAD_SD2_D7__KPP_ROW_7				0x120 0x3cc 0x7ac 0x3 0x0
+#define MX50_PAD_SD2_D7__EIM_WEIM_D_3				0x120 0x3cc 0x7f8 0x4 0x0
+#define MX50_PAD_SD2_D7__CCM_STOP				0x120 0x3cc 0x000 0x7 0x0
+#define MX50_PAD_SD2_WP__ESDHC2_WP				0x124 0x3d0 0x744 0x0 0x1
+#define MX50_PAD_SD2_WP__GPIO5_16				0x124 0x3d0 0x000 0x1 0x0
+#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD			0x124 0x3d0 0x6c8 0x2 0x0
+#define MX50_PAD_SD2_WP__EIM_WEIM_D_4				0x124 0x3d0 0x7fc 0x4 0x0
+#define MX50_PAD_SD2_WP__CCM_WAIT				0x124 0x3d0 0x000 0x7 0x0
+#define MX50_PAD_SD2_CD__ESDHC2_CD				0x128 0x3d4 0x740 0x0 0x1
+#define MX50_PAD_SD2_CD__GPIO5_17				0x128 0x3d4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC			0x128 0x3d4 0x6d4 0x2 0x0
+#define MX50_PAD_SD2_CD__EIM_WEIM_D_5				0x128 0x3d4 0x800 0x4 0x0
+#define MX50_PAD_SD2_CD__CCM_REF_EN_B				0x128 0x3d4 0x000 0x7 0x0
+#define MX50_PAD_DISP_D0__ELCDIF_DAT_0				0x12c 0x40c 0x6fc 0x0 0x0
+#define MX50_PAD_DISP_D0__GPIO2_0				0x12c 0x40c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D0__FEC_TX_CLK				0x12c 0x40c 0x78c 0x2 0x0
+#define MX50_PAD_DISP_D0__EIM_WEIM_A_16				0x12c 0x40c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0			0x12c 0x40c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0			0x12c 0x40c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D1__ELCDIF_DAT_1				0x130 0x410 0x700 0x0 0x0
+#define MX50_PAD_DISP_D1__GPIO2_1				0x130 0x410 0x000 0x1 0x0
+#define MX50_PAD_DISP_D1__FEC_RX_ERR				0x130 0x410 0x788 0x2 0x0
+#define MX50_PAD_DISP_D1__EIM_WEIM_A_17				0x130 0x410 0x000 0x3 0x0
+#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1			0x130 0x410 0x000 0x6 0x0
+#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1			0x130 0x410 0x000 0x7 0x0
+#define MX50_PAD_DISP_D2__ELCDIF_DAT_2				0x134 0x414 0x704 0x0 0x0
+#define MX50_PAD_DISP_D2__GPIO2_2				0x134 0x414 0x000 0x1 0x0
+#define MX50_PAD_DISP_D2__FEC_RX_DV				0x134 0x414 0x784 0x2 0x0
+#define MX50_PAD_DISP_D2__EIM_WEIM_A_18				0x134 0x414 0x000 0x3 0x0
+#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2			0x134 0x414 0x000 0x6 0x0
+#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2			0x134 0x414 0x000 0x7 0x0
+#define MX50_PAD_DISP_D3__ELCDIF_DAT_3				0x138 0x418 0x708 0x0 0x0
+#define MX50_PAD_DISP_D3__GPIO2_3				0x138 0x418 0x000 0x1 0x0
+#define MX50_PAD_DISP_D3__FEC_RDATA_1				0x138 0x418 0x77c 0x2 0x0
+#define MX50_PAD_DISP_D3__EIM_WEIM_A_19				0x138 0x418 0x000 0x3 0x0
+#define MX50_PAD_DISP_D3__FEC_COL				0x138 0x418 0x770 0x4 0x1
+#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3			0x138 0x418 0x000 0x6 0x0
+#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3			0x138 0x418 0x000 0x7 0x0
+#define MX50_PAD_DISP_D4__ELCDIF_DAT_4				0x13c 0x41c 0x70c 0x0 0x0
+#define MX50_PAD_DISP_D4__GPIO2_4				0x13c 0x41c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D4__FEC_RDATA_0				0x13c 0x41c 0x778 0x2 0x0
+#define MX50_PAD_DISP_D4__EIM_WEIM_A_20				0x13c 0x41c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4			0x13c 0x41c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4			0x13c 0x41c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D5__ELCDIF_DAT_5				0x140 0x420 0x710 0x0 0x0
+#define MX50_PAD_DISP_D5__GPIO2_5				0x140 0x420 0x000 0x1 0x0
+#define MX50_PAD_DISP_D5__FEC_TX_EN				0x140 0x420 0x000 0x2 0x0
+#define MX50_PAD_DISP_D5__EIM_WEIM_A_21				0x140 0x420 0x000 0x3 0x0
+#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5			0x140 0x420 0x000 0x6 0x0
+#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5			0x140 0x420 0x000 0x7 0x0
+#define MX50_PAD_DISP_D6__ELCDIF_DAT_6				0x144 0x424 0x714 0x0 0x0
+#define MX50_PAD_DISP_D6__GPIO2_6				0x144 0x424 0x000 0x1 0x0
+#define MX50_PAD_DISP_D6__FEC_TDATA_1				0x144 0x424 0x000 0x2 0x0
+#define MX50_PAD_DISP_D6__EIM_WEIM_A_22				0x144 0x424 0x000 0x3 0x0
+#define MX50_PAD_DISP_D6__FEC_RX_CLK				0x144 0x424 0x780 0x4 0x1
+#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6			0x144 0x424 0x000 0x6 0x0
+#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6			0x144 0x424 0x000 0x7 0x0
+#define MX50_PAD_DISP_D7__ELCDIF_DAT_7				0x148 0x428 0x718 0x0 0x0
+#define MX50_PAD_DISP_D7__GPIO2_7				0x148 0x428 0x000 0x1 0x0
+#define MX50_PAD_DISP_D7__FEC_TDATA_0				0x148 0x428 0x000 0x2 0x0
+#define MX50_PAD_DISP_D7__EIM_WEIM_A_23				0x148 0x428 0x000 0x3 0x0
+#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7			0x148 0x428 0x000 0x6 0x0
+#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7			0x148 0x428 0x000 0x7 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN				0x14c 0x42c 0x000 0x0 0x0
+#define MX50_PAD_DISP_WR__GPIO2_16				0x14c 0x42c 0x000 0x1 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK				0x14c 0x42c 0x000 0x2 0x0
+#define MX50_PAD_DISP_WR__EIM_WEIM_A_24				0x14c 0x42c 0x000 0x3 0x0
+#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8			0x14c 0x42c 0x000 0x6 0x0
+#define MX50_PAD_DISP_WR__USBPHY1_AVALID			0x14c 0x42c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_RD_E				0x150 0x430 0x000 0x0 0x0
+#define MX50_PAD_DISP_RD__GPIO2_19				0x150 0x430 0x000 0x1 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_ENABLE				0x150 0x430 0x000 0x2 0x0
+#define MX50_PAD_DISP_RD__EIM_WEIM_A_25				0x150 0x430 0x000 0x3 0x0
+#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9			0x150 0x430 0x000 0x6 0x0
+#define MX50_PAD_DISP_RD__USBPHY1_BVALID			0x150 0x430 0x000 0x7 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_RS				0x154 0x434 0x000 0x0 0x0
+#define MX50_PAD_DISP_RS__GPIO2_17				0x154 0x434 0x000 0x1 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_VSYNC				0x154 0x434 0x73c 0x2 0x1
+#define MX50_PAD_DISP_RS__EIM_WEIM_A_26				0x154 0x434 0x000 0x3 0x0
+#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10			0x154 0x434 0x000 0x6 0x0
+#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION			0x154 0x434 0x000 0x7 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_CS				0x158 0x438 0x000 0x0 0x0
+#define MX50_PAD_DISP_CS__GPIO2_21				0x158 0x438 0x000 0x1 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_HSYNC				0x158 0x438 0x6f8 0x2 0x1
+#define MX50_PAD_DISP_CS__EIM_WEIM_A_27				0x158 0x438 0x000 0x3 0x0
+#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3				0x158 0x438 0x000 0x4 0x0
+#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11			0x158 0x438 0x000 0x6 0x0
+#define MX50_PAD_DISP_CS__USBPHY1_IDDIG				0x158 0x438 0x000 0x7 0x0
+#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY				0x15c 0x43c 0x6f8 0x0 0x2
+#define MX50_PAD_DISP_BUSY__GPIO2_18				0x15c 0x43c 0x000 0x1 0x0
+#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3			0x15c 0x43c 0x000 0x4 0x0
+#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12			0x15c 0x43c 0x000 0x6 0x0
+#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT		0x15c 0x43c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RESET__ELCDIF_RESET			0x160 0x440 0x000 0x0 0x0
+#define MX50_PAD_DISP_RESET__GPIO2_20				0x160 0x440 0x000 0x1 0x0
+#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3			0x160 0x440 0x000 0x4 0x0
+#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13			0x160 0x440 0x000 0x6 0x0
+#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK			0x160 0x440 0x000 0x7 0x0
+#define MX50_PAD_SD3_CMD__ESDHC3_CMD				0x164 0x444 0x000 0x0 0x0
+#define MX50_PAD_SD3_CMD__GPIO5_18				0x164 0x444 0x000 0x1 0x0
+#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN				0x164 0x444 0x000 0x2 0x0
+#define MX50_PAD_SD3_CMD__SSP_CMD				0x164 0x444 0x000 0x3 0x0
+#define MX50_PAD_SD3_CLK__ESDHC3_CLK				0x168 0x448 0x000 0x0 0x0
+#define MX50_PAD_SD3_CLK__GPIO5_19				0x168 0x448 0x000 0x1 0x0
+#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN				0x168 0x448 0x000 0x2 0x0
+#define MX50_PAD_SD3_CLK__SSP_CLK				0x168 0x448 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__ESDHC3_DAT0				0x16c 0x44c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D0__GPIO5_20				0x16c 0x44c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D0__EIM_NANDF_D_4				0x16c 0x44c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D0__SSP_D0					0x16c 0x44c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__CCM_PLL1_BYP				0x16c 0x44c 0x6dc 0x7 0x1
+#define MX50_PAD_SD3_D1__ESDHC3_DAT1				0x170 0x450 0x000 0x0 0x0
+#define MX50_PAD_SD3_D1__GPIO5_21				0x170 0x450 0x000 0x1 0x0
+#define MX50_PAD_SD3_D1__EIM_NANDF_D_5				0x170 0x450 0x000 0x2 0x0
+#define MX50_PAD_SD3_D1__SSP_D1					0x170 0x450 0x000 0x3 0x0
+#define MX50_PAD_SD3_D1__CCM_PLL2_BYP				0x170 0x450 0x000 0x7 0x0
+#define MX50_PAD_SD3_D2__ESDHC3_DAT2				0x174 0x454 0x000 0x0 0x0
+#define MX50_PAD_SD3_D2__GPIO5_22				0x174 0x454 0x000 0x1 0x0
+#define MX50_PAD_SD3_D2__EIM_NANDF_D_6				0x174 0x454 0x000 0x2 0x0
+#define MX50_PAD_SD3_D2__SSP_D2					0x174 0x454 0x000 0x3 0x0
+#define MX50_PAD_SD3_D2__CCM_PLL3_BYP				0x174 0x454 0x6e4 0x7 0x1
+#define MX50_PAD_SD3_D3__ESDHC3_DAT3				0x178 0x458 0x000 0x0 0x0
+#define MX50_PAD_SD3_D3__GPIO5_23				0x178 0x458 0x000 0x1 0x0
+#define MX50_PAD_SD3_D3__EIM_NANDF_D_7				0x178 0x458 0x000 0x2 0x0
+#define MX50_PAD_SD3_D3__SSP_D3					0x178 0x458 0x000 0x3 0x0
+#define MX50_PAD_SD3_D4__ESDHC3_DAT4				0x17c 0x45c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D4__GPIO5_24				0x17c 0x45c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D4__EIM_NANDF_D_0				0x17c 0x45c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D4__SSP_D4					0x17c 0x45c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D5__ESDHC3_DAT5				0x180 0x460 0x000 0x0 0x0
+#define MX50_PAD_SD3_D5__GPIO5_25				0x180 0x460 0x000 0x1 0x0
+#define MX50_PAD_SD3_D5__EIM_NANDF_D_1				0x180 0x460 0x000 0x2 0x0
+#define MX50_PAD_SD3_D5__SSP_D5					0x180 0x460 0x000 0x3 0x0
+#define MX50_PAD_SD3_D6__ESDHC3_DAT6				0x184 0x464 0x000 0x0 0x0
+#define MX50_PAD_SD3_D6__GPIO5_26				0x184 0x464 0x000 0x1 0x0
+#define MX50_PAD_SD3_D6__EIM_NANDF_D_2				0x184 0x464 0x000 0x2 0x0
+#define MX50_PAD_SD3_D6__SSP_D6					0x184 0x464 0x000 0x3 0x0
+#define MX50_PAD_SD3_D7__ESDHC3_DAT7				0x188 0x468 0x000 0x0 0x0
+#define MX50_PAD_SD3_D7__GPIO5_27				0x188 0x468 0x000 0x1 0x0
+#define MX50_PAD_SD3_D7__EIM_NANDF_D_3				0x188 0x468 0x000 0x2 0x0
+#define MX50_PAD_SD3_D7__SSP_D7					0x188 0x468 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC3_WP				0x18c 0x46C 0x000 0x0 0x0
+#define MX50_PAD_SD3_WP__GPIO5_28				0x18c 0x46C 0x000 0x1 0x0
+#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN			0x18c 0x46C 0x000 0x2 0x0
+#define MX50_PAD_SD3_WP__SSP_CD					0x18c 0x46C 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC4_LCTL				0x18c 0x46C 0x000 0x4 0x0
+#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3				0x18c 0x46C 0x000 0x5 0x0
+#define MX50_PAD_DISP_D8__ELCDIF_DAT_8				0x190 0x470 0x71c 0x0 0x0
+#define MX50_PAD_DISP_D8__GPIO2_8				0x190 0x470 0x000 0x1 0x0
+#define MX50_PAD_DISP_D8__EIM_NANDF_CLE				0x190 0x470 0x000 0x2 0x0
+#define MX50_PAD_DISP_D8__ESDHC1_LCTL				0x190 0x470 0x000 0x3 0x0
+#define MX50_PAD_DISP_D8__ESDHC4_CMD				0x190 0x470 0x74c 0x4 0x2
+#define MX50_PAD_DISP_D8__KPP_COL_4				0x190 0x470 0x790 0x5 0x1
+#define MX50_PAD_DISP_D8__FEC_TX_CLK				0x190 0x470 0x78c 0x6 0x1
+#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0			0x190 0x470 0x000 0x7 0x0
+#define MX50_PAD_DISP_D9__ELCDIF_DAT_9				0x194 0x474 0x720 0x0 0x0
+#define MX50_PAD_DISP_D9__GPIO2_9				0x194 0x474 0x000 0x1 0x0
+#define MX50_PAD_DISP_D9__EIM_NANDF_ALE				0x194 0x474 0x000 0x2 0x0
+#define MX50_PAD_DISP_D9__ESDHC2_LCTL				0x194 0x474 0x000 0x3 0x0
+#define MX50_PAD_DISP_D9__ESDHC4_CLK				0x194 0x474 0x748 0x4 0x2
+#define MX50_PAD_DISP_D9__KPP_ROW_4				0x194 0x474 0x7a0 0x5 0x1
+#define MX50_PAD_DISP_D9__FEC_RX_ER				0x194 0x474 0x788 0x6 0x1
+#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1			0x194 0x474 0x000 0x7 0x0
+#define MX50_PAD_DISP_D10__ELCDIF_DAT_10			0x198 0x478 0x724 0x0 0x0
+#define MX50_PAD_DISP_D10__GPIO2_10				0x198 0x478 0x000 0x1 0x0
+#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0			0x198 0x478 0x000 0x2 0x0
+#define MX50_PAD_DISP_D10__ESDHC3_LCTL				0x198 0x478 0x000 0x3 0x0
+#define MX50_PAD_DISP_D10__ESDHC4_DAT0				0x198 0x478 0x000 0x4 0x0
+#define MX50_PAD_DISP_D10__KPP_COL_5				0x198 0x478 0x794 0x5 0x1
+#define MX50_PAD_DISP_D10__FEC_RX_DV				0x198 0x478 0x784 0x6 0x1
+#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2			0x198 0x478 0x000 0x7 0x0
+#define MX50_PAD_DISP_D11__ELCDIF_DAT_11			0x19c 0x47c 0x728 0x0 0x0
+#define MX50_PAD_DISP_D11__GPIO2_11				0x19c 0x47c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1			0x19c 0x47c 0x000 0x2 0x0
+#define MX50_PAD_DISP_D11__ESDHC4_DAT1				0x19c 0x47c 0x754 0x4 0x1
+#define MX50_PAD_DISP_D11__KPP_ROW_5				0x19c 0x47c 0x7a4 0x5 0x1
+#define MX50_PAD_DISP_D11__FEC_RDATA_1				0x19c 0x47c 0x77c 0x6 0x1
+#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3			0x19c 0x47c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D12__ELCDIF_DAT_12			0x1a0 0x480 0x72c 0x0 0x0
+#define MX50_PAD_DISP_D12__GPIO2_12				0x1a0 0x480 0x000 0x1 0x0
+#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2			0x1a0 0x480 0x000 0x2 0x0
+#define MX50_PAD_DISP_D12__ESDHC1_CD				0x1a0 0x480 0x000 0x3 0x0
+#define MX50_PAD_DISP_D12__ESDHC4_DAT2				0x1a0 0x480 0x758 0x4 0x1
+#define MX50_PAD_DISP_D12__KPP_COL_6				0x1a0 0x480 0x798 0x5 0x1
+#define MX50_PAD_DISP_D12__FEC_RDATA_0				0x1a0 0x480 0x778 0x6 0x1
+#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4			0x1a0 0x480 0x000 0x7 0x0
+#define MX50_PAD_DISP_D13__ELCDIF_DAT_13			0x1a4 0x484 0x730 0x0 0x0
+#define MX50_PAD_DISP_D13__GPIO2_13				0x1a4 0x484 0x000 0x1 0x0
+#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3			0x1a4 0x484 0x000 0x2 0x0
+#define MX50_PAD_DISP_D13__ESDHC3_CD				0x1a4 0x484 0x000 0x3 0x0
+#define MX50_PAD_DISP_D13__ESDHC4_DAT3				0x1a4 0x484 0x75c 0x4 0x1
+#define MX50_PAD_DISP_D13__KPP_ROW_6				0x1a4 0x484 0x7a8 0x5 0x1
+#define MX50_PAD_DISP_D13__FEC_TX_EN				0x1a4 0x484 0x000 0x6 0x0
+#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5			0x1a4 0x484 0x000 0x7 0x0
+#define MX50_PAD_DISP_D14__ELCDIF_DAT_14			0x1a8 0x488 0x734 0x0 0x0
+#define MX50_PAD_DISP_D14__GPIO2_14				0x1a8 0x488 0x000 0x1 0x0
+#define MX50_PAD_DISP_D14__EIM_NANDF_READY0			0x1a8 0x488 0x7b4 0x2 0x1
+#define MX50_PAD_DISP_D14__ESDHC1_WP				0x1a8 0x488 0x000 0x3 0x0
+#define MX50_PAD_DISP_D14__ESDHC4_WP				0x1a8 0x488 0x000 0x4 0x0
+#define MX50_PAD_DISP_D14__KPP_COL_7				0x1a8 0x488 0x79c 0x5 0x1
+#define MX50_PAD_DISP_D14__FEC_TDATA_1				0x1a8 0x488 0x000 0x6 0x0
+#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6			0x1a8 0x488 0x000 0x7 0x0
+#define MX50_PAD_DISP_D15__ELCDIF_DAT_15			0x1ac 0x48c 0x738 0x0 0x0
+#define MX50_PAD_DISP_D15__GPIO2_15				0x1ac 0x48c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D15__EIM_NANDF_DQS			0x1ac 0x48c 0x7b0 0x2 0x1
+#define MX50_PAD_DISP_D15__ESDHC3_RST				0x1ac 0x48c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D15__ESDHC4_CD				0x1ac 0x48c 0x000 0x4 0x0
+#define MX50_PAD_DISP_D15__KPP_ROW_7				0x1ac 0x48c 0x7ac 0x5 0x1
+#define MX50_PAD_DISP_D15__FEC_TDATA_0				0x1ac 0x48c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7			0x1ac 0x48c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D0__EPDC_SDDO_0				0x1b0 0x54c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D0__GPIO3_0				0x1b0 0x54c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0				0x1b0 0x54c 0x7ec 0x2 0x1
+#define MX50_PAD_EPDC_D0__ELCDIF_RS				0x1b0 0x54c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK				0x1b0 0x54c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0		0x1b0 0x54c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0			0x1b0 0x54c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D1__EPDC_SDDO_1				0x1b4 0x550 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D1__GPIO3_1				0x1b4 0x550 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1				0x1b4 0x550 0x7f0 0x2 0x1
+#define MX50_PAD_EPDC_D1__ELCDIF_CS				0x1b4 0x550 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE				0x1b4 0x550 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1		0x1b4 0x550 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1			0x1b4 0x550 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D2__EPDC_SDDO_2				0x1b8 0x554 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D2__GPIO3_2				0x1b8 0x554 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2				0x1b8 0x554 0x7f4 0x2 0x1
+#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN				0x1b8 0x554 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC				0x1b8 0x554 0x73c 0x4 0x2
+#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2		0x1b8 0x554 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2			0x1b8 0x554 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D3__EPDC_SDDO_3				0x1bc 0x558 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D3__GPIO3_3				0x1bc 0x558 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3				0x1bc 0x558 0x7f8 0x2 0x1
+#define MX50_PAD_EPDC_D3__ELCDIF_RD_E				0x1bc 0x558 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC				0x1bc 0x558 0x6f8 0x4 0x3
+#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3		0x1bc 0x558 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3			0x1bc 0x558 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D4__EPDC_SDDO_4				0x1c0 0x55c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D4__GPIO3_4				0x1c0 0x55c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4				0x1c0 0x55c 0x7fc 0x2 0x1
+#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4		0x1c0 0x55c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4			0x1c0 0x55c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D5__EPDC_SDDO_5				0x1c4 0x560 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D5__GPIO3_5				0x1c4 0x560 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5				0x1c4 0x560 0x800 0x2 0x1
+#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5		0x1c4 0x560 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5			0x1c4 0x560 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D6__EPDC_SDDO_6				0x1c8 0x564 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D6__GPIO3_6				0x1c8 0x564 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6				0x1c8 0x564 0x804 0x2 0x1
+#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6		0x1c8 0x564 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6			0x1c8 0x564 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D7__EPDC_SDDO_7				0x1cc 0x568 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D7__GPIO3_7				0x1cc 0x568 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7				0x1cc 0x568 0x808 0x2 0x1
+#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7		0x1cc 0x568 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7			0x1cc 0x568 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D8__EPDC_SDDO_8				0x1d0 0x56c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D8__GPIO3_8				0x1d0 0x56c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8				0x1d0 0x56c 0x80c 0x2 0x2
+#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24				0x1d0 0x56c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS		0x1d0 0x56c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0			0x1d0 0x56c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D9__EPDC_SDDO_9				0x1d4 0x570 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D9__GPIO3_9				0x1d4 0x570 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9				0x1d4 0x570 0x810 0x2 0x2
+#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25				0x1d4 0x570 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL		0x1d4 0x570 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1			0x1d4 0x570 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D10__EPDC_SDDO_10				0x1d8 0x574 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D10__GPIO3_10				0x1d8 0x574 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10			0x1d8 0x574 0x814 0x2 0x2
+#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26			0x1d8 0x574 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0		0x1d8 0x574 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2			0x1d8 0x574 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D11__EPDC_SDDO_11				0x1dc 0x578 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D11__GPIO3_11				0x1dc 0x578 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11			0x1dc 0x578 0x818 0x2 0x2
+#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27			0x1dc 0x578 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1		0x1dc 0x578 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3			0x1dc 0x578 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D12__EPDC_SDDO_12				0x1e0 0x57c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D12__GPIO3_12				0x1e0 0x57c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12			0x1e0 0x57c 0x81c 0x2 0x1
+#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28			0x1e0 0x57c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2		0x1e0 0x57c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4			0x1e0 0x57c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D13__EPDC_SDDO_13				0x1e4 0x580 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D13__GPIO3_13				0x1e4 0x580 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13			0x1e4 0x580 0x820 0x2 0x1
+#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29			0x1e4 0x580 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3		0x1e4 0x580 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5			0x1e4 0x580 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D14__EPDC_SDDO_14				0x1e8 0x584 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D14__GPIO3_14				0x1e8 0x584 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14			0x1e8 0x584 0x824 0x2 0x1
+#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30			0x1e8 0x584 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD			0x1e8 0x584 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4		0x1e8 0x584 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6			0x1e8 0x584 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D15__EPDC_SDDO_15				0x1ec 0x588 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D15__GPIO3_15				0x1ec 0x588 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15			0x1ec 0x588 0x828 0x2 0x1
+#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31			0x1ec 0x588 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC			0x1ec 0x588 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5		0x1ec 0x588 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7			0x1ec 0x588 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK				0x1f0 0x58c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDCLK__GPIO3_16				0x1f0 0x58c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16			0x1f0 0x58c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16			0x1f0 0x58c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS			0x1f0 0x58c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0		0x1f0 0x58c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK			0x1f0 0x58c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDSP__EPCD_GDSP				0x1f4 0x590 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDSP__GPIO3_17				0x1f4 0x590 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17			0x1f4 0x590 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17			0x1f4 0x590 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD			0x1f4 0x590 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1		0x1f4 0x590 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID			0x1f4 0x590 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDOE__EPCD_GDOE				0x1f8 0x594 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDOE__GPIO3_18				0x1f8 0x594 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18			0x1f8 0x594 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18			0x1f8 0x594 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC			0x1f8 0x594 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2		0x1f8 0x594 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION			0x1f8 0x594 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDRL__EPCD_GDRL				0x1fc 0x598 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDRL__GPIO3_19				0x1fc 0x598 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19			0x1f8 0x598 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19			0x1fc 0x598 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS			0x1fc 0x598 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3		0x1fc 0x598 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG			0x1fc 0x598 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK				0x200 0x59c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLK__GPIO3_20				0x200 0x59c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20			0x200 0x59c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20			0x200 0x59c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD			0x200 0x59c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0		0x200 0x59c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT		0x200 0x59c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ				0x204 0x5a0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOEZ__GPIO3_21				0x204 0x5a0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21			0x204 0x5a0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21			0x204 0x5a0 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC			0x204 0x5a0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1		0x204 0x5a0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY			0x204 0x5a0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOED__EPCD_SDOED				0x208 0x5a4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOED__GPIO3_22				0x208 0x5a4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22			0x208 0x5a4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22			0x208 0x5a4 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS			0x208 0x5a4 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2		0x208 0x5a4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID			0x208 0x5a4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOE__EPCD_SDOE				0x20c 0x5a8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOE__GPIO3_23				0x20c 0x5a8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23			0x20c 0x5a8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23			0x20c 0x5a8 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD			0x20c 0x5a8 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3		0x20c 0x5a8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE			0x20c 0x5a8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDLE__EPCD_SDLE				0x210 0x5ac 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDLE__GPIO3_24				0x210 0x5ac 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24			0x210 0x5ac 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8			0x210 0x5ac 0x71c 0x3 0x1
+#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC			0x210 0x5ac 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4		0x210 0x5ac 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR			0x210 0x5ac 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN			0x214 0x5b0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLKN__GPIO3_25				0x214 0x5b0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25			0x214 0x5b0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9			0x214 0x5b0 0x720 0x3 0x1
+#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS			0x214 0x5b0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR		0x214 0x5b0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK			0x214 0x5b0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR				0x218 0x5b4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDSHR__GPIO3_26				0x218 0x5b4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26			0x218 0x5b4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10			0x218 0x5b4 0x724 0x3 0x1
+#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD			0x218 0x5b4 0x6c8 0x4 0x1
+#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB			0x218 0x5b4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0		0x218 0x5b4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM			0x21c 0x5b8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCOM__GPIO3_27				0x21c 0x5b8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27			0x21c 0x5b8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11			0x21c 0x5b8 0x728 0x3 0x1
+#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC			0x21c 0x5b8 0x6d4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN		0x21c 0x5b8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1		0x21c 0x5b8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT			0x220 0x5bc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28				0x220 0x5bc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28			0x220 0x5bc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12			0x220 0x5bc 0x72c 0x3 0x1
+#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS			0x220 0x5bc 0x6d8 0x4 0x1
+#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE			0x220 0x5bc 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID		0x220 0x5bc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0			0x224 0x5c0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29			0x224 0x5c0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29			0x224 0x5c0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13			0x224 0x5c0 0x730 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD			0x224 0x5c0 0x6c4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE	0x224 0x5c0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID			0x224 0x5c0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1			0x228 0x5c4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30			0x228 0x5c4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30			0x228 0x5c4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14			0x228 0x5c4 0x734 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC			0x228 0x5c4 0x6cc 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD		0x228 0x5c4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST			0x228 0x5c4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2			0x22c 0x5c8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31			0x22c 0x5c8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31			0x22c 0x5c8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15			0x22c 0x5c8 0x738 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS		0x22c 0x5c8 0x6d0 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0		0x22c 0x5c8 0x7b8 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST			0x22c 0x5c8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3			0x230 0x5cc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20			0x230 0x5cc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2			0x230 0x5cc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1		0x230 0x5cc 0x7bc 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK			0x230 0x5cc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0			0x234 0x5d0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM0__GPIO4_21				0x234 0x5d0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3			0x234 0x5d0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK			0x234 0x5d0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1			0x238 0x5d4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM1__GPIO4_22				0x238 0x5d4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3			0x238 0x5d4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0				0x23c 0x5d8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR0__GPIO4_23				0x23c 0x5d8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7			0x23c 0x5d8 0x718 0x3 0x1
+#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1				0x240 0x5dc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR1__GPIO4_24				0x240 0x5dc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6			0x240 0x5dc 0x714 0x3 0x1
+#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0			0x244 0x5e0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE0__GPIO4_25				0x244 0x5e0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5			0x244 0x5e0 0x710 0x3 0x1
+#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1			0x248 0x5e4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE1__GPIO4_26				0x248 0x5e4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4			0x248 0x5e4 0x70c 0x3 0x0
+#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2			0x24c 0x5e8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE2__GPIO4_27				0x24c 0x5e8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3			0x24c 0x5e8 0x708 0x3 0x1
+#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3			0x250 0x5ec 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE3__GPIO4_28				0x250 0x5ec 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2			0x250 0x5ec 0x704 0x3 0x1
+#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4			0x254 0x5f0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE4__GPIO4_29				0x254 0x5f0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1			0x254 0x5f0 0x700 0x3 0x1
+#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5			0x258 0x5f4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE5__GPIO4_30				0x258 0x5f4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0			0x258 0x5f4 0x6fc 0x3 0x1
+#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0				0x25c 0x5f8 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA0__GPIO1_0				0x25c 0x5f8 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA0__KPP_COL_4				0x25c 0x5f8 0x790 0x3 0x2
+#define MX50_PAD_EIM_DA0__TPIU_TRACE_0				0x25c 0x5f8 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0				0x25c 0x5f8 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1				0x260 0x5fc 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA1__GPIO1_1				0x260 0x5fc 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA1__KPP_ROW_4				0x260 0x5fc 0x7a0 0x3 0x2
+#define MX50_PAD_EIM_DA1__TPIU_TRACE_1				0x260 0x5fc 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1				0x260 0x5fc 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2				0x264 0x600 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA2__GPIO1_2				0x264 0x600 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA2__KPP_COL_5				0x264 0x600 0x794 0x3 0x2
+#define MX50_PAD_EIM_DA2__TPIU_TRACE_2				0x264 0x600 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2				0x264 0x600 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3				0x268 0x604 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA3__GPIO1_3				0x268 0x604 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA3__KPP_ROW_5				0x268 0x604 0x7a4 0x3 0x2
+#define MX50_PAD_EIM_DA3__TPIU_TRACE_3				0x268 0x604 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3				0x268 0x604 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4				0x26c 0x608 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA4__GPIO1_4				0x26c 0x608 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA4__KPP_COL_6				0x26c 0x608 0x798 0x3 0x2
+#define MX50_PAD_EIM_DA4__TPIU_TRACE_4				0x26c 0x608 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4				0x26c 0x608 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5				0x270 0x60c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA5__GPIO1_5				0x270 0x60c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA5__KPP_ROW_6				0x270 0x60c 0x7a8 0x3 0x2
+#define MX50_PAD_EIM_DA5__TPIU_TRACE_5				0x270 0x60c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5				0x270 0x60c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6				0x274 0x610 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA6__GPIO1_6				0x274 0x610 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA6__KPP_COL_7				0x274 0x610 0x79c 0x3 0x2
+#define MX50_PAD_EIM_DA6__TPIU_TRACE_6				0x274 0x610 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6				0x274 0x610 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7				0x278 0x614 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA7__GPIO1_7				0x278 0x614 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA7__KPP_ROW_7				0x278 0x614 0x7ac 0x3 0x2
+#define MX50_PAD_EIM_DA7__TPIU_TRACE_7				0x278 0x614 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7				0x278 0x614 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8				0x27c 0x618 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA8__GPIO1_8				0x27c 0x618 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE				0x27c 0x618 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA8__TPIU_TRACE_8				0x27c 0x618 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0				0x27c 0x618 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9				0x280 0x61c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA9__GPIO1_9				0x280 0x61c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE				0x280 0x61c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA9__TPIU_TRACE_9				0x280 0x61c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1				0x280 0x61c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10			0x284 0x620 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA10__GPIO1_10				0x284 0x620 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0			0x284 0x620 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA10__TPIU_TRACE_10			0x284 0x620 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2			0x284 0x620 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11			0x288 0x624 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA11__GPIO1_11				0x288 0x624 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1			0x288 0x624 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA11__TPIU_TRACE_11			0x288 0x624 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3			0x288 0x624 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12			0x28c 0x628 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA12__GPIO1_12				0x28c 0x628 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2			0x28c 0x628 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA12__EPDC_SDCE_6				0x28c 0x628 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA12__TPIU_TRACE_12			0x28c 0x628 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4			0x28c 0x628 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13			0x290 0x62c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA13__GPIO1_13				0x290 0x62c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3			0x290 0x62c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA13__EPDC_SDCE_7				0x290 0x62c 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA13__TPIU_TRACE_13			0x290 0x62c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5			0x290 0x62c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14			0x294 0x630 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA14__GPIO1_14				0x294 0x630 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0			0x294 0x630 0x7b4 0x2 0x2
+#define MX50_PAD_EIM_DA14__EPDC_SDCE_8				0x294 0x630 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA14__TPIU_TRACE_14			0x294 0x630 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6			0x294 0x630 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15			0x298 0x634 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA15__GPIO1_15				0x298 0x634 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS			0x298 0x634 0x7b0 0x2 0x2
+#define MX50_PAD_EIM_DA15__EPDC_SDCE_9				0x298 0x634 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA15__TPIU_TRACE_15			0x298 0x634 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7			0x298 0x634 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2				0x29c 0x638 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS2__GPIO1_16				0x29c 0x638 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27				0x29c 0x638 0x000 0x2 0x0
+#define MX50_PAD_EIM_CS2__TPIU_TRCLK				0x29c 0x638 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0				0x29c 0x638 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1				0x2a0 0x63c 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS1__GPIO1_17				0x2a0 0x63c 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS1__TPIU_TRCTL				0x2a0 0x63c 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1				0x2a0 0x63c 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0				0x2a4 0x640 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS0__GPIO1_18				0x2a4 0x640 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2				0x2a4 0x640 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0				0x2a8 0x644 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB0__GPIO1_19				0x2a8 0x644 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3				0x2a8 0x644 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1				0x2ac 0x648 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB1__GPIO1_20				0x2ac 0x648 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4				0x2ac 0x648 0x000 0x7 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT			0x2b0 0x64c 0x000 0x0 0x0
+#define MX50_PAD_EIM_WAIT__GPIO1_21				0x2b0 0x64c 0x000 0x1 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B			0x2b0 0x64c 0x000 0x2 0x0
+#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5			0x2b0 0x64c 0x000 0x7 0x0
+#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK			0x2b4 0x650 0x000 0x0 0x0
+#define MX50_PAD_EIM_BCLK__GPIO1_22				0x2b4 0x650 0x000 0x1 0x0
+#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6			0x2b4 0x650 0x000 0x7 0x0
+#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY				0x2b8 0x654 0x000 0x0 0x0
+#define MX50_PAD_EIM_RDY__GPIO1_23				0x2b8 0x654 0x000 0x1 0x0
+#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7				0x2b8 0x654 0x000 0x7 0x0
+#define MX50_PAD_EIM_OE__EIM_WEIM_OE				0x2bc 0x658 0x000 0x0 0x0
+#define MX50_PAD_EIM_OE__GPIO1_24				0x2bc 0x658 0x000 0x1 0x0
+#define MX50_PAD_EIM_OE__INT_BOOT				0x2bc 0x658 0x000 0x7 0x0
+#define MX50_PAD_EIM_RW__EIM_WEIM_RW				0x2c0 0x65c 0x000 0x0 0x0
+#define MX50_PAD_EIM_RW__GPIO1_25				0x2c0 0x65c 0x000 0x1 0x0
+#define MX50_PAD_EIM_RW__SYSTEM_RST				0x2c0 0x65c 0x000 0x7 0x0
+#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA				0x2c4 0x660 0x000 0x0 0x0
+#define MX50_PAD_EIM_LBA__GPIO1_26				0x2c4 0x660 0x000 0x1 0x0
+#define MX50_PAD_EIM_LBA__TESTER_ACK				0x2c4 0x660 0x000 0x7 0x0
+#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE				0x2c8 0x664 0x000 0x0 0x0
+#define MX50_PAD_EIM_CRE__GPIO1_27				0x2c8 0x664 0x000 0x1 0x0
+
+#endif /* __DTS_IMX50_PINFUNC_H */
-- 
1.8.1.4

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Create device tree bindings for the Freescale IMX50 SoC. This was based on
the IMX53 bindings with changes made as necessary.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/boot/dts/imx50.dtsi | 659 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 659 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx50.dtsi

diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
new file mode 100644
index 0000000..c4de7ac
--- /dev/null
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -0,0 +1,659 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx50-pinfunc.h"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+	};
+
+	tzic: tz-interrupt-controller at 0fffc000 {
+		compatible = "fsl,imx50-tzic", "fsl,tzic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x0fffc000 0x4000>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ckil {
+			compatible = "fsl,imx-ckil", "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		ckih1 {
+			compatible = "fsl,imx-ckih1", "fixed-clock";
+			clock-frequency = <22579200>;
+		};
+
+		ckih2 {
+			compatible = "fsl,imx-ckih2", "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		osc {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&tzic>;
+		ranges;
+
+		aips at 50000000 { /* AIPS1 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x50000000 0x10000000>;
+			ranges;
+
+			spba at 50000000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x50000000 0x40000>;
+				ranges;
+
+				esdhc1: esdhc at 50004000 {
+					compatible = "fsl,imx50-esdhc";
+					reg = <0x50004000 0x4000>;
+					interrupts = <1>;
+					clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+
+				esdhc2: esdhc at 50008000 {
+					compatible = "fsl,imx50-esdhc";
+					reg = <0x50008000 0x4000>;
+					interrupts = <2>;
+					clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+
+				uart3: serial at 5000c000 {
+					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+					reg = <0x5000c000 0x4000>;
+					interrupts = <33>;
+					clocks = <&clks 32>, <&clks 33>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi1: ecspi at 50010000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+					reg = <0x50010000 0x4000>;
+					interrupts = <36>;
+					clocks = <&clks 51>, <&clks 52>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ssi2: ssi at 50014000 {
+					compatible = "fsl,imx50-ssi", "fsl,imx21-ssi";
+					reg = <0x50014000 0x4000>;
+					interrupts = <30>;
+					clocks = <&clks 49>;
+					fsl,fifo-depth = <15>;
+					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+					status = "disabled";
+				};
+
+				esdhc3: esdhc at 50020000 {
+					compatible = "fsl,imx50-esdhc";
+					reg = <0x50020000 0x4000>;
+					interrupts = <3>;
+					clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+
+				esdhc4: esdhc at 50024000 {
+					compatible = "fsl,imx50-esdhc";
+					reg = <0x50024000 0x4000>;
+					interrupts = <4>;
+					clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+					clock-names = "ipg", "ahb", "per";
+					bus-width = <4>;
+					status = "disabled";
+				};
+			};
+
+			usbotg: usb at 53f80000 {
+				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+				reg = <0x53f80000 0x0200>;
+				interrupts = <18>;
+				clocks = <&clks 124>;
+				status = "disabled";
+			};
+
+			usbh1: usb at 53f80200 {
+				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+				reg = <0x53f80200 0x0200>;
+				interrupts = <14>;
+				clocks = <&clks 125>;
+				status = "disabled";
+			};
+
+			usbh2: usb at 53f80400 {
+				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+				reg = <0x53f80400 0x0200>;
+				interrupts = <16>;
+				clocks = <&clks 108>;
+				status = "disabled";
+			};
+
+			usbh3: usb at 53f80600 {
+				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+				reg = <0x53f80600 0x0200>;
+				interrupts = <17>;
+				clocks = <&clks 108>;
+				status = "disabled";
+			};
+
+			gpio1: gpio at 53f84000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53f84000 0x4000>;
+				interrupts = <50 51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio at 53f88000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53f88000 0x4000>;
+				interrupts = <52 53>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio at 53f8c000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53f8c000 0x4000>;
+				interrupts = <54 55>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio at 53f90000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53f90000 0x4000>;
+				interrupts = <56 57>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			wdog1: wdog at 53f98000 {
+				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
+				reg = <0x53f98000 0x4000>;
+				interrupts = <58>;
+				clocks = <&clks 0>;
+			};
+
+			gpt: timer at 53fa0000 {
+				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+				clocks = <&clks 36>, <&clks 41>;
+				clock-names = "ipg", "per";
+			};
+
+			iomuxc: iomuxc at 53fa8000 {
+				compatible = "fsl,imx50-iomuxc";
+				reg = <0x53fa8000 0x4000>;
+
+				fec {
+					pinctrl_fec_1: fecgrp-1 {
+						fsl,pins = <
+							MX50_PAD_SSI_RXFS__FEC_MDC	0x80
+							MX50_PAD_SSI_RXC__FEC_MDIO	0x80
+							MX50_PAD_DISP_D0__FEC_TX_CLK	0x80
+							MX50_PAD_DISP_D1__FEC_RX_ERR	0x80
+							MX50_PAD_DISP_D2__FEC_RX_DV	0x80
+							MX50_PAD_DISP_D3__FEC_RDATA_1	0x80
+							MX50_PAD_DISP_D4__FEC_RDATA_0	0x80
+							MX50_PAD_DISP_D5__FEC_TX_EN	0x80
+							MX50_PAD_DISP_D6__FEC_TDATA_1	0x80
+							MX50_PAD_DISP_D7__FEC_TDATA_0	0x80
+						>;
+					};
+
+					pinctrl_fec_2: fecgrp-2 {
+						fsl,pins = <
+							MX50_PAD_I2C3_SCL__FEC_MDC	0x80
+							MX50_PAD_I2C3_SDA__FEC_MDIO	0x80
+							MX50_PAD_DISP_D0__FEC_TX_CLK	0x80
+							MX50_PAD_DISP_D10__FEC_RX_DV	0x80
+							MX50_PAD_DISP_D11__FEC_RDATA_1	0x80
+							MX50_PAD_DISP_D12__FEC_RDATA_0	0x80
+							MX50_PAD_DISP_D13__FEC_TX_EN	0x80
+							MX50_PAD_DISP_D14__FEC_TDATA_1	0x80
+							MX50_PAD_DISP_D15__FEC_TDATA_0	0x80
+						>;
+					};
+
+				};
+
+				cspi {
+					pinctrl_cspi_1: cspigrp-1 {
+						fsl,pins = <
+							MX50_PAD_CSPI_SCLK__CSPI_SCLK	0
+							MX50_PAD_CSPI_MISO__CSPI_MISO	0
+							MX50_PAD_CSPI_MOSI__CSPI_MOSI	0
+							MX50_PAD_CSPI_SS0__GPIO4_11	0xc4
+							MX50_PAD_ECSPI1_MOSI__CSPI_SS1	0xf4
+						>;
+					};
+				};
+
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0
+							MX50_PAD_ECSPI1_SS0__ECSPI1_SS0   0
+							MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0
+							MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0
+						>;
+					};
+				};
+
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp-1 {
+						fsl,pins = <
+							MX50_PAD_SD1_D0__ESDHC1_DAT0    0
+							MX50_PAD_SD1_D1__ESDHC1_DAT1    0
+							MX50_PAD_SD1_D2__ESDHC1_DAT2    0
+							MX50_PAD_SD1_D3__ESDHC1_DAT3    0
+							MX50_PAD_SD1_CMD__ESDHC1_CMD	0
+							MX50_PAD_SD1_CLK__ESDHC1_CLK	0
+						>;
+					};
+
+					pinctrl_esdhc1_2: esdhc1grp-2 {
+						fsl,pins = <
+							MX50_PAD_SD1_D0__ESDHC1_DAT0	0
+							MX50_PAD_SD1_D1__ESDHC1_DAT1	0
+							MX50_PAD_SD1_D2__ESDHC1_DAT2	0
+							MX50_PAD_SD1_D3__ESDHC1_DAT3	0
+							MX50_PAD_UART3_TXD__ESDHC1_DAT4	0
+							MX50_PAD_UART3_RXD__ESDHC1_DAT5	0
+							MX50_PAD_UART4_TXD__ESDHC1_DAT6	0
+							MX50_PAD_UART4_RXD__ESDHC1_DAT7	0
+							MX50_PAD_SD1_CMD__ESDHC1_CMD	0
+							MX50_PAD_SD1_CLK__ESDHC1_CLK	0
+						>;
+					};
+				};
+
+				esdhc2 {
+					pinctrl_esdhc2_1: esdhc2grp-1 {
+						fsl,pins = <
+							MX50_PAD_SD2_CMD__ESDHC2_CMD	0
+							MX50_PAD_SD2_CLK__ESDHC2_CLK	0
+							MX50_PAD_SD2_D0__ESDHC2_DAT0	0
+							MX50_PAD_SD2_D1__ESDHC2_DAT1	0
+							MX50_PAD_SD2_D2__ESDHC2_DAT2	0
+							MX50_PAD_SD2_D3__ESDHC2_DAT3	0
+							MX50_PAD_SD2_D4__ESDHC2_DAT4	0
+							MX50_PAD_SD2_D5__ESDHC2_DAT5	0
+							MX50_PAD_SD2_D6__ESDHC2_DAT6	0
+							MX50_PAD_SD2_D7__ESDHC2_DAT7	0
+						>;
+					};
+				};
+
+				esdhc3 {
+					pinctrl_esdhc3_1: esdhc3grp-1 {
+						fsl,pins = <
+							MX50_PAD_SD3_D0__ESDHC3_DAT0	0
+							MX50_PAD_SD3_D1__ESDHC3_DAT1	0
+							MX50_PAD_SD3_D2__ESDHC3_DAT2	0
+							MX50_PAD_SD3_D3__ESDHC3_DAT3	0
+							MX50_PAD_SD3_D4__ESDHC3_DAT4	0
+							MX50_PAD_SD3_D5__ESDHC3_DAT5	0
+							MX50_PAD_SD3_D6__ESDHC3_DAT6	0
+							MX50_PAD_SD3_D7__ESDHC3_DAT7	0
+							MX50_PAD_SD3_CMD__ESDHC3_CMD	0
+							MX50_PAD_SD3_CLK__ESDHC3_CLK	0
+						>;
+					};
+				};
+
+				i2c1 {
+					pinctrl_i2c1_1: i2c1grp-1 {
+						fsl,pins = <
+							MX50_PAD_I2C1_SDA__I2C1_SDA	0
+							MX50_PAD_I2C1_SCL__I2C1_SCL	0
+						>;
+					};
+				};
+
+				i2c2 {
+					pinctrl_i2c2_1: i2c2grp-1 {
+						fsl,pins = <
+							MX50_PAD_I2C2_SDA__I2C2_SDA	0
+							MX50_PAD_I2C2_SCL__I2C2_SCL	0
+						>;
+					};
+				};
+
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <
+							MX50_PAD_I2C3_SDA__I2C3_SDA	0
+							MX50_PAD_I2C3_SCL__I2C3_SCL	0
+						>;
+					};
+				};
+
+				owire {
+					pinctrl_owire_1: owiregrp-1 {
+						fsl,pins = <
+							MX50_PAD_OWIRE__OWIRE_LINE	0
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							MX50_PAD_UART1_TXD__UART1_TXD_MUX 0
+							MX50_PAD_UART1_RXD__UART1_RXD_MUX 0
+							MX50_PAD_UART1_RTS__UART1_RTS     0
+							MX50_PAD_UART1_CTS__UART1_CTS     0
+						>;
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2_1: uart2grp-1 {
+						fsl,pins = <
+							MX50_PAD_UART2_TXD__UART2_TXD_MUX 0
+							MX50_PAD_UART2_RXD__UART2_RXD_MUX 0
+							MX50_PAD_UART2_RTS__UART2_RTS     0
+							MX50_PAD_UART2_CTS__UART2_CTS     0
+						>;
+					};
+
+					pinctrl_uart2_2: uart2grp-2 {
+						fsl,pins = <
+							MX50_PAD_I2C1_SCL__UART2_TXD_MUX  0
+							MX50_PAD_I2C1_SDA__UART2_RXD_MUX  0
+							MX50_PAD_I2C2_SDA__UART2_RTS      0
+							MX50_PAD_I2C2_SCL__UART2_CTS      0
+						>;
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3_1: uart3grp-1 {
+						fsl,pins = <
+							MX50_PAD_UART3_TXD__UART3_TXD_MUX 0
+							MX50_PAD_UART3_RXD__UART3_RXD_MUX 0
+							MX50_PAD_ECSPI1_SCLK__UART3_RTS	  0
+							MX50_PAD_ECSPI1_MOSI__UART3_CTS	  0
+						>;
+					};
+				};
+
+				uart4 {
+					pinctrl_uart4_1: uart4grp-1 {
+						fsl,pins = <
+							MX50_PAD_UART4_TXD__UART4_TXD_MUX 0
+							MX50_PAD_UART4_RXD__UART4_RXD_MUX 0
+							MX50_PAD_ECSPI1_MISO__UART4_RTS   0
+							MX50_PAD_ECSPI1_SS0__UART4_CTS    0
+						>;
+					};
+				};
+
+				uart5 {
+					pinctrl_uart5_1: uart5grp-1 {
+						fsl,pins = <
+							MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0
+							MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX  0
+							MX50_PAD_ECSPI2_SCLK__UART5_RTS     0
+							MX50_PAD_ECSPI2_MOSI__UART5_CTS     0
+						>;
+					};
+				};
+
+			};
+
+			gpr: iomuxc-gpr at 53fa8000 {
+				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
+				reg = <0x53fa8000 0xc>;
+			};
+
+			pwm1: pwm at 53fb4000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+				reg = <0x53fb4000 0x4000>;
+				clocks = <&clks 37>, <&clks 38>;
+				clock-names = "ipg", "per";
+				interrupts = <61>;
+			};
+
+			pwm2: pwm at 53fb8000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+				reg = <0x53fb8000 0x4000>;
+				clocks = <&clks 39>, <&clks 40>;
+				clock-names = "ipg", "per";
+				interrupts = <94>;
+			};
+
+			uart1: serial at 53fbc000 {
+				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+				reg = <0x53fbc000 0x4000>;
+				interrupts = <31>;
+				clocks = <&clks 28>, <&clks 29>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart2: serial at 53fc0000 {
+				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+				reg = <0x53fc0000 0x4000>;
+				interrupts = <32>;
+				clocks = <&clks 30>, <&clks 31>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			src: src at 53fd0000 {
+				compatible = "fsl,imx50-src", "fsl,imx51-src";
+				reg = <0x53fd0000 0x4000>;
+				#reset-cells = <1>;
+			};
+
+			clks: ccm at 53fd4000{
+				compatible = "fsl,imx50-ccm";
+				reg = <0x53fd4000 0x4000>;
+				interrupts = <0 71 0x04 0 72 0x04>;
+				#clock-cells = <1>;
+			};
+
+			gpio5: gpio at 53fdc000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <103 104>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio at 53fe0000 {
+				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+				reg = <0x53fe0000 0x4000>;
+				interrupts = <105 106>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			i2c3: i2c at 53fec000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+				reg = <0x53fec000 0x4000>;
+				interrupts = <64>;
+				clocks = <&clks 88>;
+				status = "disabled";
+			};
+
+			uart4: serial at 53ff0000 {
+				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+				reg = <0x53ff0000 0x4000>;
+				interrupts = <13>;
+				clocks = <&clks 65>, <&clks 66>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+		};
+
+		aips at 60000000 {	/* AIPS2 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x60000000 0x10000000>;
+			ranges;
+
+			uart5: serial at 63f90000 {
+				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+				reg = <0x63f90000 0x4000>;
+				interrupts = <86>;
+				clocks = <&clks 67>, <&clks 68>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			owire: owire at 63fa4000 {
+				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
+				reg = <0x63fa4000 0x4000>;
+				clocks = <&clks 159>;
+				status = "disabled";
+			};
+
+			ecspi2: ecspi at 63fac000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+				reg = <0x63fac000 0x4000>;
+				interrupts = <37>;
+				clocks = <&clks 53>, <&clks 54>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			sdma: sdma at 63fb0000 {
+				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
+				reg = <0x63fb0000 0x4000>;
+				interrupts = <6>;
+				clocks = <&clks 56>, <&clks 56>;
+				clock-names = "ipg", "ahb";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
+			};
+
+			cspi: cspi at 63fc0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
+				reg = <0x63fc0000 0x4000>;
+				interrupts = <38>;
+				clocks = <&clks 55>, <&clks 55>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			i2c2: i2c at 63fc4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc4000 0x4000>;
+				interrupts = <63>;
+				clocks = <&clks 35>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 63fc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc8000 0x4000>;
+				interrupts = <62>;
+				clocks = <&clks 34>;
+				status = "disabled";
+			};
+
+			ssi1: ssi at 63fcc000 {
+				compatible = "fsl,imx50-ssi", "fsl,imx21-ssi";
+				reg = <0x63fcc000 0x4000>;
+				interrupts = <29>;
+				clocks = <&clks 48>;
+				fsl,fifo-depth = <15>;
+				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
+				status = "disabled";
+			};
+
+			audmux: audmux at 63fd0000 {
+				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
+				reg = <0x63fd0000 0x4000>;
+				status = "disabled";
+			};
+
+			fec: ethernet at 63fec000 {
+				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+				reg = <0x63fec000 0x4000>;
+				interrupts = <87>;
+				clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+				clock-names = "ipg", "ahb", "ptp";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.8.1.4

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Sascha Hauer]

On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Create device tree bindings for the Freescale IMX50 SoC. This was based on
> the IMX53 bindings with changes made as necessary.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
> +
> +			iomuxc: iomuxc at 53fa8000 {
> +				compatible = "fsl,imx50-iomuxc";
> +				reg = <0x53fa8000 0x4000>;
> +
> +				fec {
> +					pinctrl_fec_1: fecgrp-1 {
> +						fsl,pins = <
> +							MX50_PAD_SSI_RXFS__FEC_MDC	0x80
> +							MX50_PAD_SSI_RXC__FEC_MDIO	0x80
> +							MX50_PAD_DISP_D0__FEC_TX_CLK	0x80
> +							MX50_PAD_DISP_D1__FEC_RX_ERR	0x80
> +							MX50_PAD_DISP_D2__FEC_RX_DV	0x80
> +							MX50_PAD_DISP_D3__FEC_RDATA_1	0x80
> +							MX50_PAD_DISP_D4__FEC_RDATA_0	0x80
> +							MX50_PAD_DISP_D5__FEC_TX_EN	0x80
> +							MX50_PAD_DISP_D6__FEC_TDATA_1	0x80
> +							MX50_PAD_DISP_D7__FEC_TDATA_0	0x80
> +						>;
> +					};
> +

Shawn recently removed the pinctrl groups here and referenced to this
node by doing

&iomuxc {
	fec {
		...
	};
};

> +				cspi {
> +					pinctrl_cspi_1: cspigrp-1 {
> +						fsl,pins = <
> +							MX50_PAD_CSPI_SCLK__CSPI_SCLK	0

0 is definitely wrong here. We have 0x80000000 for "Don't touch
padctrl", but otherwise this should contain some real padctrl settings.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Matt Sealey]

On Tue, Oct 22, 2013 at 7:35 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> Create device tree bindings for the Freescale IMX50 SoC. This was based on
>> the IMX53 bindings with changes made as necessary.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>> +
>> +                     iomuxc: iomuxc at 53fa8000 {
>> +                             compatible = "fsl,imx50-iomuxc";
>> +                             reg = <0x53fa8000 0x4000>;
>> +
>> +                             fec {
>> +                                     pinctrl_fec_1: fecgrp-1 {
>> +                                             fsl,pins = <
>> +                                                     MX50_PAD_SSI_RXFS__FEC_MDC      0x80
>> +                                                     MX50_PAD_SSI_RXC__FEC_MDIO      0x80
>> +                                                     MX50_PAD_DISP_D0__FEC_TX_CLK    0x80
>> +                                                     MX50_PAD_DISP_D1__FEC_RX_ERR    0x80
>> +                                                     MX50_PAD_DISP_D2__FEC_RX_DV     0x80
>> +                                                     MX50_PAD_DISP_D3__FEC_RDATA_1   0x80
>> +                                                     MX50_PAD_DISP_D4__FEC_RDATA_0   0x80
>> +                                                     MX50_PAD_DISP_D5__FEC_TX_EN     0x80
>> +                                                     MX50_PAD_DISP_D6__FEC_TDATA_1   0x80
>> +                                                     MX50_PAD_DISP_D7__FEC_TDATA_0   0x80
>> +                                             >;
>> +                                     };
>> +
>
> Shawn recently removed the pinctrl groups here and referenced to this
> node by doing
>
> &iomuxc {
>         fec {
>                 ...
>         };
> };
>
>> +                             cspi {
>> +                                     pinctrl_cspi_1: cspigrp-1 {
>> +                                             fsl,pins = <
>> +                                                     MX50_PAD_CSPI_SCLK__CSPI_SCLK   0
>
> 0 is definitely wrong here. We have 0x80000000 for "Don't touch
> padctrl", but otherwise this should contain some real padctrl settings.

A more pressing question is in what world did the bootloader not
already set these pins up and if they are already set up, why are they
loitering in the device tree?

-- 
Matt Sealey <neko@bakuhatsu.net>

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Sascha Hauer]

On Tue, Oct 22, 2013 at 03:08:43PM -0500, Matt Sealey wrote:
> On Tue, Oct 22, 2013 at 7:35 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
> >> From: Greg Ungerer <gerg@uclinux.org>
> >>
> >> Create device tree bindings for the Freescale IMX50 SoC. This was based on
> >> the IMX53 bindings with changes made as necessary.
> >>
> >> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> >> ---
> >> +
> >> +                     iomuxc: iomuxc at 53fa8000 {
> >> +                             compatible = "fsl,imx50-iomuxc";
> >> +                             reg = <0x53fa8000 0x4000>;
> >> +
> >> +                             fec {
> >> +                                     pinctrl_fec_1: fecgrp-1 {
> >> +                                             fsl,pins = <
> >> +                                                     MX50_PAD_SSI_RXFS__FEC_MDC      0x80
> >> +                                                     MX50_PAD_SSI_RXC__FEC_MDIO      0x80
> >> +                                                     MX50_PAD_DISP_D0__FEC_TX_CLK    0x80
> >> +                                                     MX50_PAD_DISP_D1__FEC_RX_ERR    0x80
> >> +                                                     MX50_PAD_DISP_D2__FEC_RX_DV     0x80
> >> +                                                     MX50_PAD_DISP_D3__FEC_RDATA_1   0x80
> >> +                                                     MX50_PAD_DISP_D4__FEC_RDATA_0   0x80
> >> +                                                     MX50_PAD_DISP_D5__FEC_TX_EN     0x80
> >> +                                                     MX50_PAD_DISP_D6__FEC_TDATA_1   0x80
> >> +                                                     MX50_PAD_DISP_D7__FEC_TDATA_0   0x80
> >> +                                             >;
> >> +                                     };
> >> +
> >
> > Shawn recently removed the pinctrl groups here and referenced to this
> > node by doing
> >
> > &iomuxc {
> >         fec {
> >                 ...
> >         };
> > };
> >
> >> +                             cspi {
> >> +                                     pinctrl_cspi_1: cspigrp-1 {
> >> +                                             fsl,pins = <
> >> +                                                     MX50_PAD_CSPI_SCLK__CSPI_SCLK   0
> >
> > 0 is definitely wrong here. We have 0x80000000 for "Don't touch
> > padctrl", but otherwise this should contain some real padctrl settings.
> 
> A more pressing question is in what world did the bootloader not
> already set these pins up and if they are already set up, why are they
> loitering in the device tree?

Having NO_PAD_CTRL in the devicetree doesn't make sense, you're right.
Either a pin has to be configured by the bootloader completely or not at
all. Having the mux configured by the kernel and the drive strength by
the bootloader is broken by design. All pins should have a complete
padctrl setup and NO_PAD_CTRL should be dropped.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Benoît Thébaudeau]

Dear Sascha Hauer,

On Tuesday, October 22, 2013 11:57:47 PM, Sascha Hauer wrote:
> On Tue, Oct 22, 2013 at 03:08:43PM -0500, Matt Sealey wrote:
> > On Tue, Oct 22, 2013 at 7:35 AM, Sascha Hauer <s.hauer@pengutronix.de>
> > wrote:
> > > On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
> > >> From: Greg Ungerer <gerg@uclinux.org>
> > >>
> > >> Create device tree bindings for the Freescale IMX50 SoC. This was based
> > >> on
> > >> the IMX53 bindings with changes made as necessary.
> > >>
> > >> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> > >> ---
> > >> +
> > >> +                     iomuxc: iomuxc at 53fa8000 {
> > >> +                             compatible = "fsl,imx50-iomuxc";
> > >> +                             reg = <0x53fa8000 0x4000>;
> > >> +
> > >> +                             fec {
> > >> +                                     pinctrl_fec_1: fecgrp-1 {
> > >> +                                             fsl,pins = <
> > >> +
> > >> MX50_PAD_SSI_RXFS__FEC_MDC
> > >> 0x80
> > >> +
> > >> MX50_PAD_SSI_RXC__FEC_MDIO
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D0__FEC_TX_CLK
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D1__FEC_RX_ERR
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D2__FEC_RX_DV
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D3__FEC_RDATA_1
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D4__FEC_RDATA_0
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D5__FEC_TX_EN
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D6__FEC_TDATA_1
> > >> 0x80
> > >> +
> > >> MX50_PAD_DISP_D7__FEC_TDATA_0
> > >> 0x80
> > >> +                                             >;
> > >> +                                     };
> > >> +
> > >
> > > Shawn recently removed the pinctrl groups here and referenced to this
> > > node by doing
> > >
> > > &iomuxc {
> > >         fec {
> > >                 ...
> > >         };
> > > };
> > >
> > >> +                             cspi {
> > >> +                                     pinctrl_cspi_1: cspigrp-1 {
> > >> +                                             fsl,pins = <
> > >> +
> > >> MX50_PAD_CSPI_SCLK__CSPI_SCLK
> > >> 0
> > >
> > > 0 is definitely wrong here. We have 0x80000000 for "Don't touch
> > > padctrl", but otherwise this should contain some real padctrl settings.
> > 
> > A more pressing question is in what world did the bootloader not
> > already set these pins up and if they are already set up, why are they
> > loitering in the device tree?
> 
> Having NO_PAD_CTRL in the devicetree doesn't make sense, you're right.
> Either a pin has to be configured by the bootloader completely or not at
> all. Having the mux configured by the kernel and the drive strength by
> the bootloader is broken by design. All pins should have a complete
> padctrl setup and NO_PAD_CTRL should be dropped.

Some pins may be configured completely by the kernel, and not at all by the
bootloader. In that case, the device tree may wish to keep the SoC reset pad
configuration. NO_PAD_CTRL is useful in that case, although one might argue that
the reset values should not be trusted for various reasons.

But there is another case. One SoC pin may be connected to several external
devices, e.g. through an external analog mux. In that case, the bootloader may
configure the SoC mux and pad for one usage, while the kernel may afterwards
change only the mux configuration of this pin for the other usage.

So NO_PAD_CTRL is not strictly required for pinctrl, but it can be handy.

Best regards,
Beno?t

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Matt Sealey]

On Tue, Oct 22, 2013 at 5:42 PM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Dear Sascha Hauer,
>
> On Tuesday, October 22, 2013 11:57:47 PM, Sascha Hauer wrote:
>> > >
>> > > 0 is definitely wrong here. We have 0x80000000 for "Don't touch
>> > > padctrl", but otherwise this should contain some real padctrl settings.
>> >
>> > A more pressing question is in what world did the bootloader not
>> > already set these pins up and if they are already set up, why are they
>> > loitering in the device tree?
>>
>> Having NO_PAD_CTRL in the devicetree doesn't make sense, you're right.
>> Either a pin has to be configured by the bootloader completely or not at
>> all. Having the mux configured by the kernel and the drive strength by
>> the bootloader is broken by design. All pins should have a complete
>> padctrl setup and NO_PAD_CTRL should be dropped.
>
> Some pins may be configured completely by the kernel, and not at all by the
> bootloader. In that case, the device tree may wish to keep the SoC reset pad
> configuration. NO_PAD_CTRL is useful in that case, although one might argue that
> the reset values should not be trusted for various reasons.

No, that's totally illogical. The magic bit to "leave my pad controls
alone" makes no sense since you're re-configuring mux mode and input
select (even if they're the same as the bootloader, you're doing it
twice).

There are two reasons this gets done, both of which are very very odd..

1) The definition of the pinmux tuple of 3 register/value pairs is
ordered such that the pad control can be set independently of the
preprocessor definition for the pad (which supplies the first 5 values
in the 6 value pin definition). This is weird since one of the values
doesn't belong to the register the value pair is intended for, and
saying "do not

2) The reason we have to define the three registers even if we "don't
change values" is so users (or userspace) can fiddle with the GPIOs
through some never-used non-existent (since it doesn't expose these
values) sysfs pinmuxing API.

In this case, you don't "set the pad control to 'do not touch'" but
supply the exact values from the manual or empirically derived from
inspection at SoC power on. There is ZERO use for a 'do not touch'
bit. In the case where it turns out the bootloader is wrong, you'll
have to supply a value here anyway. So supply the default.

In reality what would happen is the binding gets a kick in the pants
so it makes more sense, and we define that the bootloader MUST set up
all static pin multiplexing configuration at the earliest opportunity
and save Linux the hassle. pinctrl is for microcontrollers and
robotics boards - Arduino or BeagleBone Black where you have expansion
connectors which could have multiple useful configurations, or be
changed on a hotpluggable attachment.

Even if your bootloader doesn't use the pins, it should at least set
them up for later, for electrical reasons. If the default direction
for a gpio mux is output, who knows what it is for a custom peripheral
mux, and if your peripheral has an output on that pin.. then you're
driving outputs from both sides, which is nonsensical. If the default
direction is input, and your peripheral is an input, you can set up
conditions where essentially the value floats (or at least is
unpredictable) at the peripheral side.

Your hardware guy will usually slap you for leaving it in the wrong
state for the time it takes to load Linux from SD card or SPI NOR, and
decompress, and get to several seconds into the boot process before
configuring pin muxing, or even to past the init daemon, so it can do
a module or firmware load first.

> But there is another case. One SoC pin may be connected to several external
> devices, e.g. through an external analog mux. In that case, the bootloader may
> configure the SoC mux and pad for one usage, while the kernel may afterwards
> change only the mux configuration of this pin for the other usage.

This is the ONLY use case it makes any sense in a static
configuration, but at this point, why not just supply the required
value, even if it's the chip default? If the configuration for "kernel
time" is fixed, the bootloader should quiesce the device and configure
it for the kernel to match the device tree. There are a bunch of
configurations on i.MX51 where the DT is redefining the default pinmux
for the SoC... pointlessly..

> So NO_PAD_CTRL is not strictly required for pinctrl, but it can be handy.

Given that 0x0 (or 0x80000000) takes up exactly the same amount of
space and time to research and put in the tree as the ACTUAL required
pad settings from the manual or empirically supplied, supplying the
pad settings makes more sense (and is far, far more descriptive).
There is a case here for cross-checking ALL DT hardware configuration
details against the actual configuration of the hardware, and
supplying a weird pinctrl definition (for instance, setting a RAZ bit
as 1, or a RAO bit to 0) could be caught this way (there are *lots* of
pin definitions out there in the world for i.MX at least which are
doing this, some of them in the Boot ROM DCD table...)

-- 
Matt Sealey <neko@bakuhatsu.net>

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Benoît Thébaudeau]

Hi Matt,

On Wednesday, October 23, 2013 1:06:44 AM, Matt Sealey wrote:
> On Tue, Oct 22, 2013 at 5:42 PM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> > Dear Sascha Hauer,
> >
> > On Tuesday, October 22, 2013 11:57:47 PM, Sascha Hauer wrote:
> >> > >
> >> > > 0 is definitely wrong here. We have 0x80000000 for "Don't touch
> >> > > padctrl", but otherwise this should contain some real padctrl
> >> > > settings.
> >> >
> >> > A more pressing question is in what world did the bootloader not
> >> > already set these pins up and if they are already set up, why are they
> >> > loitering in the device tree?
> >>
> >> Having NO_PAD_CTRL in the devicetree doesn't make sense, you're right.
> >> Either a pin has to be configured by the bootloader completely or not at
> >> all. Having the mux configured by the kernel and the drive strength by
> >> the bootloader is broken by design. All pins should have a complete
> >> padctrl setup and NO_PAD_CTRL should be dropped.
> >
> > Some pins may be configured completely by the kernel, and not at all by the
> > bootloader. In that case, the device tree may wish to keep the SoC reset
> > pad
> > configuration. NO_PAD_CTRL is useful in that case, although one might argue
> > that
> > the reset values should not be trusted for various reasons.
> 
> No, that's totally illogical. The magic bit to "leave my pad controls
> alone" makes no sense since you're re-configuring mux mode and input
> select (even if they're the same as the bootloader, you're doing it
> twice).
> 
> There are two reasons this gets done, both of which are very very odd..
> 
> 1) The definition of the pinmux tuple of 3 register/value pairs is
> ordered such that the pad control can be set independently of the
> preprocessor definition for the pad (which supplies the first 5 values
> in the 6 value pin definition). This is weird since one of the values
> doesn't belong to the register the value pair is intended for, and
> saying "do not
> 
> 2) The reason we have to define the three registers even if we "don't
> change values" is so users (or userspace) can fiddle with the GPIOs
> through some never-used non-existent (since it doesn't expose these
> values) sysfs pinmuxing API.
> 
> In this case, you don't "set the pad control to 'do not touch'" but
> supply the exact values from the manual or empirically derived from
> inspection at SoC power on. There is ZERO use for a 'do not touch'
> bit. In the case where it turns out the bootloader is wrong, you'll
> have to supply a value here anyway. So supply the default.

That makes sense, but it has the disadvantage of being more error prone than
keeping reset values if they're fine, because errors in pad settings may lead to
bugs less obvious than bugs in mux settings. On the other hand, forcing the
developers to check all pad settings has the advantage of not using reset values
that may be wrong for some applications. All in all, removing NO_PAD_CTRL seems
better here.

> In reality what would happen is the binding gets a kick in the pants
> so it makes more sense, and we define that the bootloader MUST set up
> all static pin multiplexing configuration at the earliest opportunity
> and save Linux the hassle. pinctrl is for microcontrollers and
> robotics boards - Arduino or BeagleBone Black where you have expansion
> connectors which could have multiple useful configurations, or be
> changed on a hotpluggable attachment.
> 
> Even if your bootloader doesn't use the pins, it should at least set
> them up for later, for electrical reasons. If the default direction
> for a gpio mux is output, who knows what it is for a custom peripheral
> mux, and if your peripheral has an output on that pin.. then you're
> driving outputs from both sides, which is nonsensical. If the default
> direction is input, and your peripheral is an input, you can set up
> conditions where essentially the value floats (or at least is
> unpredictable) at the peripheral side.
> 
> Your hardware guy will usually slap you for leaving it in the wrong
> state for the time it takes to load Linux from SD card or SPI NOR, and
> decompress, and get to several seconds into the boot process before
> configuring pin muxing, or even to past the init daemon, so it can do
> a module or firmware load first.

I agree, except that a properly designed board should not connect pins set as
outputs upon reset to the outputs of external devices, since this leaves
potential electrical level conflicts from reset at least until the software
cleans the mess. However, you're right that such things happen and should be
handled as you say.

But if some SoC pins are used as inputs, set up as inputs by the SoC reset but
with the wrong mux value, and unused by the bootloader, there is no reason to
set up these pins in the bootloader rather than in the DT. Same for output pins
connected to a bus disabled by default and unused in the bootloader. Actually,
the bootloader really has to set up pins because it uses them, or for electrical
reasons, or to disable some unused feature, but the two latter are most of the
time an exception among all connected pins.

> > But there is another case. One SoC pin may be connected to several external
> > devices, e.g. through an external analog mux. In that case, the bootloader
> > may
> > configure the SoC mux and pad for one usage, while the kernel may
> > afterwards
> > change only the mux configuration of this pin for the other usage.
> 
> This is the ONLY use case it makes any sense in a static
> configuration, but at this point, why not just supply the required
> value, even if it's the chip default? If the configuration for "kernel
> time" is fixed, the bootloader should quiesce the device and configure
> it for the kernel to match the device tree. There are a bunch of
> configurations on i.MX51 where the DT is redefining the default pinmux
> for the SoC... pointlessly..

This is a possibility.

> > So NO_PAD_CTRL is not strictly required for pinctrl, but it can be handy.
> 
> Given that 0x0 (or 0x80000000) takes up exactly the same amount of
> space and time to research and put in the tree as the ACTUAL required
> pad settings from the manual or empirically supplied, supplying the
> pad settings makes more sense (and is far, far more descriptive).
> There is a case here for cross-checking ALL DT hardware configuration
> details against the actual configuration of the hardware, and
> supplying a weird pinctrl definition (for instance, setting a RAZ bit
> as 1, or a RAO bit to 0) could be caught this way (there are *lots* of
> pin definitions out there in the world for i.MX at least which are
> doing this, some of them in the Boot ROM DCD table...)

Agreed. It may be better to drop NO_PAD_CTRL from DT, but I still find debatable
whether to compel to move all pin configurations to the bootloader for static
configurations, since the less the kernel has to rely on the bootloader, the
more reliable and self-sufficient it is (with DT).

Note that in the patch above, 0 may be intended to be the actual pad setting,
and not to mean by mistake NO_PAD_CTRL.

Best regards,
Beno?t

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Greg Ungerer]

Hi Benoit, Matt, Sascha,

On 23/10/13 10:17, Beno?t Th?baudeau wrote:
> Hi Matt,
> 
> On Wednesday, October 23, 2013 1:06:44 AM, Matt Sealey wrote:
>> On Tue, Oct 22, 2013 at 5:42 PM, Beno?t Th?baudeau
>> <benoit.thebaudeau@advansee.com> wrote:
>>> Dear Sascha Hauer,
>>>
>>> On Tuesday, October 22, 2013 11:57:47 PM, Sascha Hauer wrote:
>>>>>>
>>>>>> 0 is definitely wrong here. We have 0x80000000 for "Don't touch
>>>>>> padctrl", but otherwise this should contain some real padctrl
>>>>>> settings.
>>>>>
>>>>> A more pressing question is in what world did the bootloader not
>>>>> already set these pins up and if they are already set up, why are they
>>>>> loitering in the device tree?
>>>>
>>>> Having NO_PAD_CTRL in the devicetree doesn't make sense, you're right.
>>>> Either a pin has to be configured by the bootloader completely or not at
>>>> all. Having the mux configured by the kernel and the drive strength by
>>>> the bootloader is broken by design. All pins should have a complete
>>>> padctrl setup and NO_PAD_CTRL should be dropped.
>>>
>>> Some pins may be configured completely by the kernel, and not at all by the
>>> bootloader. In that case, the device tree may wish to keep the SoC reset
>>> pad
>>> configuration. NO_PAD_CTRL is useful in that case, although one might argue
>>> that
>>> the reset values should not be trusted for various reasons.
>>
>> No, that's totally illogical. The magic bit to "leave my pad controls
>> alone" makes no sense since you're re-configuring mux mode and input
>> select (even if they're the same as the bootloader, you're doing it
>> twice).
>>
>> There are two reasons this gets done, both of which are very very odd..
>>
>> 1) The definition of the pinmux tuple of 3 register/value pairs is
>> ordered such that the pad control can be set independently of the
>> preprocessor definition for the pad (which supplies the first 5 values
>> in the 6 value pin definition). This is weird since one of the values
>> doesn't belong to the register the value pair is intended for, and
>> saying "do not
>>
>> 2) The reason we have to define the three registers even if we "don't
>> change values" is so users (or userspace) can fiddle with the GPIOs
>> through some never-used non-existent (since it doesn't expose these
>> values) sysfs pinmuxing API.
>>
>> In this case, you don't "set the pad control to 'do not touch'" but
>> supply the exact values from the manual or empirically derived from
>> inspection at SoC power on. There is ZERO use for a 'do not touch'
>> bit. In the case where it turns out the bootloader is wrong, you'll
>> have to supply a value here anyway. So supply the default.
> 
> That makes sense, but it has the disadvantage of being more error prone than
> keeping reset values if they're fine, because errors in pad settings may lead to
> bugs less obvious than bugs in mux settings. On the other hand, forcing the
> developers to check all pad settings has the advantage of not using reset values
> that may be wrong for some applications. All in all, removing NO_PAD_CTRL seems
> better here.
> 
>> In reality what would happen is the binding gets a kick in the pants
>> so it makes more sense, and we define that the bootloader MUST set up
>> all static pin multiplexing configuration at the earliest opportunity
>> and save Linux the hassle. pinctrl is for microcontrollers and
>> robotics boards - Arduino or BeagleBone Black where you have expansion
>> connectors which could have multiple useful configurations, or be
>> changed on a hotpluggable attachment.
>>
>> Even if your bootloader doesn't use the pins, it should at least set
>> them up for later, for electrical reasons. If the default direction
>> for a gpio mux is output, who knows what it is for a custom peripheral
>> mux, and if your peripheral has an output on that pin.. then you're
>> driving outputs from both sides, which is nonsensical. If the default
>> direction is input, and your peripheral is an input, you can set up
>> conditions where essentially the value floats (or at least is
>> unpredictable) at the peripheral side.
>>
>> Your hardware guy will usually slap you for leaving it in the wrong
>> state for the time it takes to load Linux from SD card or SPI NOR, and
>> decompress, and get to several seconds into the boot process before
>> configuring pin muxing, or even to past the init daemon, so it can do
>> a module or firmware load first.
> 
> I agree, except that a properly designed board should not connect pins set as
> outputs upon reset to the outputs of external devices, since this leaves
> potential electrical level conflicts from reset at least until the software
> cleans the mess. However, you're right that such things happen and should be
> handled as you say.
> 
> But if some SoC pins are used as inputs, set up as inputs by the SoC reset but
> with the wrong mux value, and unused by the bootloader, there is no reason to
> set up these pins in the bootloader rather than in the DT. Same for output pins
> connected to a bus disabled by default and unused in the bootloader. Actually,
> the bootloader really has to set up pins because it uses them, or for electrical
> reasons, or to disable some unused feature, but the two latter are most of the
> time an exception among all connected pins.
> 
>>> But there is another case. One SoC pin may be connected to several external
>>> devices, e.g. through an external analog mux. In that case, the bootloader
>>> may
>>> configure the SoC mux and pad for one usage, while the kernel may
>>> afterwards
>>> change only the mux configuration of this pin for the other usage.
>>
>> This is the ONLY use case it makes any sense in a static
>> configuration, but at this point, why not just supply the required
>> value, even if it's the chip default? If the configuration for "kernel
>> time" is fixed, the bootloader should quiesce the device and configure
>> it for the kernel to match the device tree. There are a bunch of
>> configurations on i.MX51 where the DT is redefining the default pinmux
>> for the SoC... pointlessly..
> 
> This is a possibility.
> 
>>> So NO_PAD_CTRL is not strictly required for pinctrl, but it can be handy.
>>
>> Given that 0x0 (or 0x80000000) takes up exactly the same amount of
>> space and time to research and put in the tree as the ACTUAL required
>> pad settings from the manual or empirically supplied, supplying the
>> pad settings makes more sense (and is far, far more descriptive).
>> There is a case here for cross-checking ALL DT hardware configuration
>> details against the actual configuration of the hardware, and
>> supplying a weird pinctrl definition (for instance, setting a RAZ bit
>> as 1, or a RAO bit to 0) could be caught this way (there are *lots* of
>> pin definitions out there in the world for i.MX at least which are
>> doing this, some of them in the Boot ROM DCD table...)
> 
> Agreed. It may be better to drop NO_PAD_CTRL from DT, but I still find debatable
> whether to compel to move all pin configurations to the bootloader for static
> configurations, since the less the kernel has to rely on the bootloader, the
> more reliable and self-sufficient it is (with DT).
> 
> Note that in the patch above, 0 may be intended to be the actual pad setting,
> and not to mean by mistake NO_PAD_CTRL.

And 0 was the intended pad control setting here. I wasn't even aware of
NO_PAD_CTRL.

Regards
Greg

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Matt Sealey]

On Tue, Oct 22, 2013 at 7:17 PM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Hi Matt,

Hello Beno?t,

> On Wednesday, October 23, 2013 1:06:44 AM, Matt Sealey wrote:
>
>> No, that's totally illogical. The magic bit to "leave my pad controls
>> alone" makes no sense since you're re-configuring mux mode and input
>> select (even if they're the same as the bootloader, you're doing it
>> twice).
>>
>> There are two reasons this gets done, both of which are very very odd..
>>
>> 1) The definition of the pinmux tuple of 3 register/value pairs is
>> ordered such that the pad control can be set independently of the
>> preprocessor definition for the pad (which supplies the first 5 values
>> in the 6 value pin definition). This is weird since one of the values
>> doesn't belong to the register the value pair is intended for, and
>> saying "do not
>>
>> 2) The reason we have to define the three registers even if we "don't
>> change values" is so users (or userspace) can fiddle with the GPIOs
>> through some never-used non-existent (since it doesn't expose these
>> values) sysfs pinmuxing API.
>>
>> In this case, you don't "set the pad control to 'do not touch'" but
>> supply the exact values from the manual or empirically derived from
>> inspection at SoC power on. There is ZERO use for a 'do not touch'
>> bit. In the case where it turns out the bootloader is wrong, you'll
>> have to supply a value here anyway. So supply the default.
>
> That makes sense, but it has the disadvantage of being more error prone than
> keeping reset values if they're fine, because errors in pad settings may lead to
> bugs less obvious than bugs in mux settings.

That is true, but programmer error is programmer error.. you can
introduce it on either side.

The major use right now for "I want my pads not to be touched" is to
get past the restriction that pinctrl MUST be specified (and people
don't like adding empty, dummy entries) and to make trees more
readable (but kilobytes bigger), and the use cases where it seems
expected to redefine pad settings that are either chip defaults on POR
(hence the special pad control bit) or that the bootloader can
absolutely be guaranteed to have done, for some reason.

If you MUST specify a pinmux, specify the whole damn thing - mux,
input and pad. Not a half-way mux, input, "pad register but please
ignore me."

Having fewer ways of defining it means having fewer things to expect
when debugging.

> developers to check all pad settings has the advantage of not using reset values
> that may be wrong for some applications. All in all, removing NO_PAD_CTRL seems
> better here.

Thanks.

>> Your hardware guy will usually slap you for leaving it in the wrong
>> state for the time it takes to load Linux from SD card or SPI NOR, and
>> decompress, and get to several seconds into the boot process before
>> configuring pin muxing, or even to past the init daemon, so it can do
>> a module or firmware load first.
>
> I agree, except that a properly designed board should not connect pins set as
> outputs upon reset to the outputs of external devices, since this leaves
> potential electrical level conflicts from reset at least until the software
> cleans the mess.

True, but you cannot just say "well all my IOs on my chip default to
GPIO inputs so I cannot connect any peripheral inputs to any of them
until I have configured them". Sometimes you are at the mercy of your
SoC designer and peripheral designer, and the pad layout of your chip.

> However, you're right that such things happen and should be
> handled as you say.
>
> But if some SoC pins are used as inputs, set up as inputs by the SoC reset but
> with the wrong mux value, and unused by the bootloader, there is no reason to
> set up these pins in the bootloader rather than in the DT.

There's all the reason in the world; this SHOULD be the preferred,
default practice.

> connected to a bus disabled by default and unused in the bootloader. Actually,
> the bootloader really has to set up pins because it uses them, or for electrical
> reasons, or to disable some unused feature, but the two latter are most of the
> time an exception among all connected pins.

To give the Efika MX as an example, the bootloader needs to set up
maybe 60-70 out of a possible 80-90 pins (DDR in the DCD or BootROM
plugin, PATA, SD card (twice on some configs), LEDs, board id inputs,
pmic interrupt, spi + chipselects, uart, usb, i2c, clock outs, reset
toggles for all of the above peripherals to effectively make sure
everything is quiesced for the OS).

The things not really set up - video and audio. But a bootloader could
support video, so you could expect this will need to be set up
eventually. It may even play a sound at a future point.

When you are left with basically adding 10 or 15 more pins, and you
already implemented 70.. this is not really a difficult task. On i.MX
at least, you have the opportunity to do a lot of this inside the boot
ROM stage, and considering you want to give user interactivity,
multiple boot sources, and be sure the system is running and powered
okay before you get to the OS, you're stuck doing it.

You could do the bare minimum internally but externally - when it goes
upstream in U-Boot or something - it should all be there. Any pin
definitions in DT would be firmware bug workarounds or dynamically
configured items which can ONLY be determined at runtime (DDR mode or
voltage level selects on SDHC for example) and that are safe to
change. It is not true on i.MX, but on some SoC in the world, changing
pad mux is NOT going to be glitchless and encouraging huge amounts of
reconfiguration at OS boot time is possibly the worst thing ever.

> Agreed. It may be better to drop NO_PAD_CTRL from DT, but I still find debatable
> whether to compel to move all pin configurations to the bootloader for static
> configurations, since the less the kernel has to rely on the bootloader, the
> more reliable and self-sufficient it is (with DT).

There's a status quo of not doing it, and putting the definitions in
Linux, but I am just saying it should be encouraged to do this in the
bootloader and save the device tree space (and hassle) and reserve the
tree definitions for when you REALLY have no other choice in doing so.

I would prefer bootloaders were written with as much care as the DT should be ;)

I can't enforce it, but it can be made to be something developers
might get a 'gold star' and a smile, if they do so.

> Note that in the patch above, 0 may be intended to be the actual pad setting,
> and not to mean by mistake NO_PAD_CTRL.

It could be, but 0 for a pad setting doesn't make a lot of sense for
the vast majority of pins.. in this case, it kind of does.

In this case, I'd prefer 0x00000000 rather than just a 0. The DTC is
going to expand it to a 32-bit cell anyway.. but it'd go a long way to
knowing the intent.. (this is kind of why I don't like the idea of
specifying the pad settings and preprocessor macros, it hides
implementation details which give information to reviewers about what
they're looking at..)

--
Matt Sealey <neko@bakuhatsu.net>

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Greg Ungerer]

Hi Sascha,

n 22/10/13 22:35, Sascha Hauer wrote:
> On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> Create device tree bindings for the Freescale IMX50 SoC. This was based on
>> the IMX53 bindings with changes made as necessary.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>> +
>> +			iomuxc: iomuxc at 53fa8000 {
>> +				compatible = "fsl,imx50-iomuxc";
>> +				reg = <0x53fa8000 0x4000>;
>> +
>> +				fec {
>> +					pinctrl_fec_1: fecgrp-1 {
>> +						fsl,pins = <
>> +							MX50_PAD_SSI_RXFS__FEC_MDC	0x80
>> +							MX50_PAD_SSI_RXC__FEC_MDIO	0x80
>> +							MX50_PAD_DISP_D0__FEC_TX_CLK	0x80
>> +							MX50_PAD_DISP_D1__FEC_RX_ERR	0x80
>> +							MX50_PAD_DISP_D2__FEC_RX_DV	0x80
>> +							MX50_PAD_DISP_D3__FEC_RDATA_1	0x80
>> +							MX50_PAD_DISP_D4__FEC_RDATA_0	0x80
>> +							MX50_PAD_DISP_D5__FEC_TX_EN	0x80
>> +							MX50_PAD_DISP_D6__FEC_TDATA_1	0x80
>> +							MX50_PAD_DISP_D7__FEC_TDATA_0	0x80
>> +						>;
>> +					};
>> +
> 
> Shawn recently removed the pinctrl groups here and referenced to this
> node by doing
> 
> &iomuxc {
> 	fec {
> 		...
> 	};
> };

Ok, I'll move them in the same way then.


>> +				cspi {
>> +					pinctrl_cspi_1: cspigrp-1 {
>> +						fsl,pins = <
>> +							MX50_PAD_CSPI_SCLK__CSPI_SCLK	0
> 
> 0 is definitely wrong here. We have 0x80000000 for "Don't touch
> padctrl", but otherwise this should contain some real padctrl settings.

0 was the intended value here. Although I am happy to hear arguments that 
it is not the correct value.

0 in this case translates to:

   . Low driver strength
   . Open drain disabled
   . Pull/Keep disabled

If the norm is to leave what the boot loader set then I will change them
to 0x80000000. Is the net out of the discussion that followed to do this?

Thanks for looking over the patches.

Regards
Greg

[PATCH 7/8] ARM: dts: imx: add IMX50 SoC device tree bindings

[Shawn Guo]

On Fri, Oct 18, 2013 at 04:04:19PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Create device tree bindings for the Freescale IMX50 SoC. This was based on

I think it's a device tree source rather than bindings.

> the IMX53 bindings with changes made as necessary.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/boot/dts/imx50.dtsi | 659 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 659 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx50.dtsi
> 
> diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
> new file mode 100644
> index 0000000..c4de7ac
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx50.dtsi
> @@ -0,0 +1,659 @@
> +/*
> + * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include "skeleton.dtsi"
> +#include "imx50-pinfunc.h"
> +
> +/ {
> +	aliases {
> +		serial0 = &uart1;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +		serial3 = &uart4;
> +		serial4 = &uart5;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
> +		gpio5 = &gpio6;

Please sort these aliases alphabetically.

Shawn

> +	};

[PATCH 8/8] ARM: dts: imx: add device tree support for Freescale imx50evk board

[gerg at uclinux.org]

From: Greg Ungerer <gerg@uclinux.org>

Add device tree support for the Freescale IMX50EVk board based around the
IMX50 SoC. Supports UART, SPI flash, FEC ethernet and USB on this board.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/arm/boot/dts/Makefile      |  1 +
 arch/arm/boot/dts/imx50-evk.dts | 89 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 90 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx50-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..4dd442c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -122,6 +122,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx27-phytec-phycard-s-som.dtb \
 	imx27-phytec-phycard-s-rdk.dtb \
 	imx31-bug.dtb \
+	imx50-evk.dtb \
 	imx51-apf51.dtb \
 	imx51-apf51dev.dtb \
 	imx51-babbage.dtb \
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
new file mode 100644
index 0000000..74b260d
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx50.dtsi"
+
+/ {
+	model = "Freescale i.MX50 Evaluation Kit";
+	compatible = "fsl,imx50-evk", "fsl,imx50";
+
+	memory {
+		reg = <0x70000000 0x80000000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&cspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_cspi_1>;
+	fsl,spi-num-chipselects = <2>;
+	cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
+	status = "okay";
+
+	flash: m25p32 at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "m25p32", "m25p80";
+		spi-max-frequency = <25000000>;
+		reg = <1>;
+
+		partition at 0 {
+			label = "bootloader";
+			reg = <0x0 0x100000>;
+			read-only;
+		};
+
+		partition at 100000 {
+			label = "kernel";
+			reg = <0x100000 0x300000>;
+		};
+	};
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbh1 {
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbh2 {
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbh3 {
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec_1>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio4 12 0>;
+	status = "okay";
+};
-- 
1.8.1.4

[PATCH 8/8] ARM: dts: imx: add device tree support for Freescale imx50evk board

[Shawn Guo]

On Fri, Oct 18, 2013 at 04:04:20PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> Add device tree support for the Freescale IMX50EVk board based around the
> IMX50 SoC. Supports UART, SPI flash, FEC ethernet and USB on this board.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/boot/dts/Makefile      |  1 +
>  arch/arm/boot/dts/imx50-evk.dts | 89 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 90 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx50-evk.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e95af3f..4dd442c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -122,6 +122,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx27-phytec-phycard-s-som.dtb \
>  	imx27-phytec-phycard-s-rdk.dtb \
>  	imx31-bug.dtb \
> +	imx50-evk.dtb \
>  	imx51-apf51.dtb \
>  	imx51-apf51dev.dtb \
>  	imx51-babbage.dtb \
> diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
> new file mode 100644
> index 0000000..74b260d
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx50-evk.dts
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include "imx50.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX50 Evaluation Kit";
> +	compatible = "fsl,imx50-evk", "fsl,imx50";
> +
> +	memory {
> +		reg = <0x70000000 0x80000000>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +};

There is nothing meaningful in there, so it can be dropped for now.

> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1_1>;
> +	status = "okay";
> +};
> +
> +&cspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_cspi_1>;
> +	fsl,spi-num-chipselects = <2>;
> +	cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
> +	status = "okay";
> +
> +	flash: m25p32 at 1 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "m25p32", "m25p80";
> +		spi-max-frequency = <25000000>;
> +		reg = <1>;
> +
> +		partition at 0 {
> +			label = "bootloader";
> +			reg = <0x0 0x100000>;
> +			read-only;
> +		};
> +
> +		partition at 100000 {
> +			label = "kernel";
> +			reg = <0x100000 0x300000>;
> +		};
> +	};
> +};
> +
> +&usbotg {
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&usbh2 {
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&usbh3 {
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec_1>;
> +	phy-mode = "rmii";
> +	phy-reset-gpios = <&gpio4 12 0>;
> +	status = "okay";
> +};

Please sort these nodes alphabetically in label name.

Shawn

> -- 
> 1.8.1.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/8] ARM: imx: add IMX50 SoC support

[Jason Cooper]

Greg,

On Fri, Oct 18, 2013 at 04:04:12PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> This set of patches is the code and device tree support for the Freescale
> IMX50 SoC. This part is similar to the IMX53 SoC family, and I have resued
> as much of its support as possible. These patches are against 3.12-rc5.
> 
> With these changes you can load and run on the Freescale IMX50-EVK board.

Thanks for doing this!  I was tinkering with adding this in order to
bring up a vanilla kernel on the SanDisk Connect Wireless Media Drive.
I'm at Edinburgh this week, so I won't be able to test until next week.

thx,

Jason.

[PATCH 0/8] ARM: imx: add IMX50 SoC support

[Greg Ungerer]

Hi Jason,

On 23/10/13 19:14, Jason Cooper wrote:
> On Fri, Oct 18, 2013 at 04:04:12PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> This set of patches is the code and device tree support for the Freescale
>> IMX50 SoC. This part is similar to the IMX53 SoC family, and I have resued
>> as much of its support as possible. These patches are against 3.12-rc5.
>>
>> With these changes you can load and run on the Freescale IMX50-EVK board.
>
> Thanks for doing this!  I was tinkering with adding this in order to
> bring up a vanilla kernel on the SanDisk Connect Wireless Media Drive.
> I'm at Edinburgh this week, so I won't be able to test until next week.

More testing would be great.

Thanks
Greg

[PATCH 0/8] ARM: imx: add IMX50 SoC support

[Shawn Guo]

Hi Greg,

On Fri, Oct 18, 2013 at 04:04:12PM +1000, gerg at uclinux.org wrote:
> From: Greg Ungerer <gerg@uclinux.org>
> 
> This set of patches is the code and device tree support for the Freescale
> IMX50 SoC. This part is similar to the IMX53 SoC family, and I have resued
> as much of its support as possible. These patches are against 3.12-rc5.

Nice patches.  Can you please base it on branch below with your next
posting, so that I can apply them more easily?

  git://git.linaro.org/people/shawnguo/linux-2.6.git for-next

Shawn

> With these changes you can load and run on the Freescale IMX50-EVK board.
> 
> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
> ---
>  arch/arm/Kconfig.debug              |    9 
>  arch/arm/boot/dts/Makefile          |    1 
>  arch/arm/boot/dts/imx50-evk.dts     |   89 +++
>  arch/arm/boot/dts/imx50-pinfunc.h   |  923 ++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/imx50.dtsi        |  659 +++++++++++++++++++++++++
>  arch/arm/include/debug/imx-uart.h   |   10 
>  arch/arm/mach-imx/Kconfig           |    9 
>  arch/arm/mach-imx/Makefile          |    1 
>  arch/arm/mach-imx/clk-imx51-imx53.c |   79 +++
>  arch/arm/mach-imx/common.h          |    3 
>  arch/arm/mach-imx/mach-imx50.c      |   52 ++
>  drivers/pinctrl/Kconfig             |    8 
>  drivers/pinctrl/Makefile            |    1 
>  drivers/pinctrl/pinctrl-imx50.c     |  426 ++++++++++++++++
>  14 files changed, 2270 insertions(+)
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/8] ARM: imx: add IMX50 SoC support

[Greg Ungerer]

Hi Shawn

On 25/10/13 01:00, Shawn Guo wrote:
> Hi Greg,
>
> On Fri, Oct 18, 2013 at 04:04:12PM +1000, gerg at uclinux.org wrote:
>> From: Greg Ungerer <gerg@uclinux.org>
>>
>> This set of patches is the code and device tree support for the Freescale
>> IMX50 SoC. This part is similar to the IMX53 SoC family, and I have resued
>> as much of its support as possible. These patches are against 3.12-rc5.
>
> Nice patches.  Can you please base it on branch below with your next
> posting, so that I can apply them more easily?
>
>    git://git.linaro.org/people/shawnguo/linux-2.6.git for-next

Sure thing. I'll roll in all your suggestions, and send out a v2 in
the next few days. Thanks for the review.

Regards
Greg



> Shawn
>
>> With these changes you can load and run on the Freescale IMX50-EVK board.
>>
>> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
>> ---
>>   arch/arm/Kconfig.debug              |    9
>>   arch/arm/boot/dts/Makefile          |    1
>>   arch/arm/boot/dts/imx50-evk.dts     |   89 +++
>>   arch/arm/boot/dts/imx50-pinfunc.h   |  923 ++++++++++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/imx50.dtsi        |  659 +++++++++++++++++++++++++
>>   arch/arm/include/debug/imx-uart.h   |   10
>>   arch/arm/mach-imx/Kconfig           |    9
>>   arch/arm/mach-imx/Makefile          |    1
>>   arch/arm/mach-imx/clk-imx51-imx53.c |   79 +++
>>   arch/arm/mach-imx/common.h          |    3
>>   arch/arm/mach-imx/mach-imx50.c      |   52 ++
>>   drivers/pinctrl/Kconfig             |    8
>>   drivers/pinctrl/Makefile            |    1
>>   drivers/pinctrl/pinctrl-imx50.c     |  426 ++++++++++++++++
>>   14 files changed, 2270 insertions(+)
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>