* [PATCH 02/20] clocksource: sun4i: Change CPU mask to cpu_possible_mask
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 03/20] clocksource: sun4i: Increase a bit the clock event and sources rating Daniel Lezcano
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
The interrupt for the timer is a shared processor interrupt, so any CPU
found in the system can handle it. Switch to our cpumask to
cpu_possible_mask instead of cpumask_of(0).
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/clocksource/sun4i_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index a7f492e..6a76b4e 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -187,7 +187,7 @@ static void __init sun4i_timer_init(struct device_node *node)
val = readl(timer_base + TIMER_IRQ_EN_REG);
writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
- sun4i_clockevent.cpumask = cpumask_of(0);
+ sun4i_clockevent.cpumask = cpu_possible_mask;
sun4i_clockevent.irq = irq;
clockevents_config_and_register(&sun4i_clockevent, rate,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 03/20] clocksource: sun4i: Increase a bit the clock event and sources rating
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
2013-12-30 10:19 ` [PATCH 02/20] clocksource: sun4i: Change CPU mask to cpu_possible_mask Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 04/20] clocksource: Add Allwinner SoCs HS timers driver Daniel Lezcano
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
We want to keep this driver as the default provider of the clock events
and source, yet some other driver might fit in the "desired" category of
ratings. Hence, we need to increase a bit the rating so that we can have
more flexibility in the ratings we choose.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/sun4i_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index 6a76b4e..d7a1a1a 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
static struct clock_event_device sun4i_clockevent = {
.name = "sun4i_tick",
- .rating = 300,
+ .rating = 350,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = sun4i_clkevt_mode,
.set_next_event = sun4i_clkevt_next_event,
@@ -172,7 +172,7 @@ static void __init sun4i_timer_init(struct device_node *node)
setup_sched_clock(sun4i_timer_sched_read, 32, rate);
clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
- rate, 300, 32, clocksource_mmio_readl_down);
+ rate, 350, 32, clocksource_mmio_readl_down);
ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 04/20] clocksource: Add Allwinner SoCs HS timers driver
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
2013-12-30 10:19 ` [PATCH 02/20] clocksource: sun4i: Change CPU mask to cpu_possible_mask Daniel Lezcano
2013-12-30 10:19 ` [PATCH 03/20] clocksource: sun4i: Increase a bit the clock event and sources rating Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 05/20] ARM: sun5i: a10s: Add support for the High Speed Timers Daniel Lezcano
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.
The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.
[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
alphabetically"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 22 +++
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/clocksource/Kconfig | 4 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-sun5i.c | 192 ++++++++++++++++++++
5 files changed, 220 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 drivers/clocksource/timer-sun5i.c
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
new file mode 100644
index 0000000..7c26154
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
@@ -0,0 +1,22 @@
+Allwinner SoCs High Speed Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sun5i-a13-hstimer" or
+ "allwinner,sun7i-a20-hstimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
+ one)
+- clocks: phandle to the source clock (usually the AHB clock)
+
+Example:
+
+timer at 01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index c9e72c8..bce0d42 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -12,3 +12,4 @@ config ARCH_SUNXI
select PINCTRL_SUNXI
select SPARSE_IRQ
select SUN4I_TIMER
+ select SUN5I_HSTIMER
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index bdb953e..884eeff 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -37,6 +37,10 @@ config SUN4I_TIMER
select CLKSRC_MMIO
bool
+config SUN5I_HSTIMER
+ select CLKSRC_MMIO
+ bool
+
config VT8500_TIMER
bool
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 33621ef..358358d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
+obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
new file mode 100644
index 0000000..bddc522
--- /dev/null
+++ b/drivers/clocksource/timer-sun5i.c
@@ -0,0 +1,192 @@
+/*
+ * Allwinner SoCs hstimer driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define TIMER_IRQ_EN_REG 0x00
+#define TIMER_IRQ_EN(val) BIT(val)
+#define TIMER_IRQ_ST_REG 0x04
+#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
+#define TIMER_CTL_ENABLE BIT(0)
+#define TIMER_CTL_RELOAD BIT(1)
+#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
+#define TIMER_CTL_ONESHOT BIT(7)
+#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
+#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
+#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
+#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
+
+#define TIMER_SYNC_TICKS 3
+
+static void __iomem *timer_base;
+static u32 ticks_per_jiffy;
+
+/*
+ * When we disable a timer, we need to wait at least for 2 cycles of
+ * the timer source clock. We will use for that the clocksource timer
+ * that is already setup and runs@the same frequency than the other
+ * timers, and we never will be disabled.
+ */
+static void sun5i_clkevt_sync(void)
+{
+ u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
+
+ while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
+ cpu_relax();
+}
+
+static void sun5i_clkevt_time_stop(u8 timer)
+{
+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
+ writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
+
+ sun5i_clkevt_sync();
+}
+
+static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
+{
+ writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
+}
+
+static void sun5i_clkevt_time_start(u8 timer, bool periodic)
+{
+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
+
+ if (periodic)
+ val &= ~TIMER_CTL_ONESHOT;
+ else
+ val |= TIMER_CTL_ONESHOT;
+
+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+ timer_base + TIMER_CTL_REG(timer));
+}
+
+static void sun5i_clkevt_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ sun5i_clkevt_time_stop(0);
+ sun5i_clkevt_time_setup(0, ticks_per_jiffy);
+ sun5i_clkevt_time_start(0, true);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ sun5i_clkevt_time_stop(0);
+ sun5i_clkevt_time_start(0, false);
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ default:
+ sun5i_clkevt_time_stop(0);
+ break;
+ }
+}
+
+static int sun5i_clkevt_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+{
+ sun5i_clkevt_time_stop(0);
+ sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
+ sun5i_clkevt_time_start(0, false);
+
+ return 0;
+}
+
+static struct clock_event_device sun5i_clockevent = {
+ .name = "sun5i_tick",
+ .rating = 340,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = sun5i_clkevt_mode,
+ .set_next_event = sun5i_clkevt_next_event,
+};
+
+
+static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sun5i_timer_irq = {
+ .name = "sun5i_timer0",
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = sun5i_timer_interrupt,
+ .dev_id = &sun5i_clockevent,
+};
+
+static u32 sun5i_timer_sched_read(void)
+{
+ return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
+}
+
+static void __init sun5i_timer_init(struct device_node *node)
+{
+ unsigned long rate;
+ struct clk *clk;
+ int ret, irq;
+ u32 val;
+
+ timer_base = of_iomap(node, 0);
+ if (!timer_base)
+ panic("Can't map registers");
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (irq <= 0)
+ panic("Can't parse IRQ");
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+ clk_prepare_enable(clk);
+ rate = clk_get_rate(clk);
+
+ writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
+ writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+ timer_base + TIMER_CTL_REG(1));
+
+ setup_sched_clock(sun5i_timer_sched_read, 32, rate);
+ clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
+ rate, 340, 32, clocksource_mmio_readl_down);
+
+ ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
+
+ ret = setup_irq(irq, &sun5i_timer_irq);
+ if (ret)
+ pr_warn("failed to setup irq %d\n", irq);
+
+ /* Enable timer0 interrupt */
+ val = readl(timer_base + TIMER_IRQ_EN_REG);
+ writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
+
+ sun5i_clockevent.cpumask = cpu_possible_mask;
+ sun5i_clockevent.irq = irq;
+
+ clockevents_config_and_register(&sun5i_clockevent, rate,
+ TIMER_SYNC_TICKS, 0xffffffff);
+}
+CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
+ sun5i_timer_init);
+CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
+ sun5i_timer_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 05/20] ARM: sun5i: a10s: Add support for the High Speed Timers
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (2 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 04/20] clocksource: Add Allwinner SoCs HS timers driver Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 06/20] ARM: sun5i: a13: " Daniel Lezcano
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A10s has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 5247674..e674c94 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -332,5 +332,12 @@
clock-frequency = <100000>;
status = "disabled";
};
+
+ timer at 01c60000 {
+ compatible = "allwinner,sun5i-a13-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <82>, <83>;
+ clocks = <&ahb_gates 28>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 06/20] ARM: sun5i: a13: Add support for the High Speed Timers
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (3 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 05/20] ARM: sun5i: a10s: Add support for the High Speed Timers Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 07/20] ARM: sun7i: a20: " Daniel Lezcano
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A13 has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a..1ccd75d 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -273,5 +273,12 @@
clock-frequency = <100000>;
status = "disabled";
};
+
+ timer at 01c60000 {
+ compatible = "allwinner,sun5i-a13-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <82>, <83>;
+ clocks = <&ahb_gates 28>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 07/20] ARM: sun7i: a20: Add support for the High Speed Timers
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (4 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 06/20] ARM: sun5i: a13: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 08/20] clocksource: arm_global_timer: Switch to sched_clock_register() Daniel Lezcano
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.
Now that we have a driver to support it, we can enable them in the
device tree.
[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e46cfed..ee6cec7 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -395,6 +395,16 @@
status = "disabled";
};
+ hstimer at 01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 81 1>,
+ <0 82 1>,
+ <0 83 1>,
+ <0 84 1>;
+ clocks = <&ahb_gates 28>;
+ };
+
gic: interrupt-controller at 01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 08/20] clocksource: arm_global_timer: Switch to sched_clock_register()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (5 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 07/20] ARM: sun7i: a20: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 09/20] clocksource: cadence_ttc_timer: " Daniel Lezcano
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface. While we're here increase the number of bits that
sched_clock can handle to 64 to make full use of the counter.
Cc: Stuart Menefy <stuart.menefy@st.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/arm_global_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c
index c639b1a..0fc31d0 100644
--- a/drivers/clocksource/arm_global_timer.c
+++ b/drivers/clocksource/arm_global_timer.c
@@ -202,7 +202,7 @@ static struct clocksource gt_clocksource = {
};
#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-static u32 notrace gt_sched_clock_read(void)
+static u64 notrace gt_sched_clock_read(void)
{
return gt_counter_read();
}
@@ -217,7 +217,7 @@ static void __init gt_clocksource_init(void)
writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
- setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
+ sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
#endif
clocksource_register_hz(>_clocksource, gt_clk_rate);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 09/20] clocksource: cadence_ttc_timer: Switch to sched_clock_register()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (6 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 08/20] clocksource: arm_global_timer: Switch to sched_clock_register() Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 10/20] clocksource: sun4i: " Daniel Lezcano
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/cadence_ttc_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index b2bb3a4b..b865b4e 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -158,7 +158,7 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
TTC_COUNT_VAL_OFFSET);
}
-static u32 notrace ttc_sched_clock_read(void)
+static u64 notrace ttc_sched_clock_read(void)
{
return __raw_readl(ttc_sched_clock_val_reg);
}
@@ -306,7 +306,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
}
ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
- setup_sched_clock(ttc_sched_clock_read, 16,
+ sched_clock_register(ttc_sched_clock_read, 16,
clk_get_rate(ttccs->ttc.clk) / PRESCALE);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 10/20] clocksource: sun4i: Switch to sched_clock_register()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (7 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 09/20] clocksource: cadence_ttc_timer: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 11/20] clocksource: orion: " Daniel Lezcano
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface. While we're here, mark the sched_clock function as
notrace to prevent ftrace recursion crashes.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/sun4i_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index d7a1a1a..1911874 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -138,7 +138,7 @@ static struct irqaction sun4i_timer_irq = {
.dev_id = &sun4i_clockevent,
};
-static u32 sun4i_timer_sched_read(void)
+static u64 notrace sun4i_timer_sched_read(void)
{
return ~readl(timer_base + TIMER_CNTVAL_REG(1));
}
@@ -170,7 +170,7 @@ static void __init sun4i_timer_init(struct device_node *node)
TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
timer_base + TIMER_CTL_REG(1));
- setup_sched_clock(sun4i_timer_sched_read, 32, rate);
+ sched_clock_register(sun4i_timer_sched_read, 32, rate);
clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
rate, 350, 32, clocksource_mmio_readl_down);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 11/20] clocksource: orion: Switch to sched_clock_register()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (8 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 10/20] clocksource: sun4i: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 12/20] clocksource: clksrc-of: Warn if no clock sources are found Daniel Lezcano
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Boyd <sboyd@codeaurora.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/time-orion.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/time-orion.c
index 9c7f018..2006622 100644
--- a/drivers/clocksource/time-orion.c
+++ b/drivers/clocksource/time-orion.c
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(orion_timer_ctrl_clrset);
/*
* Free-running clocksource handling.
*/
-static u32 notrace orion_read_sched_clock(void)
+static u64 notrace orion_read_sched_clock(void)
{
return ~readl(timer_base + TIMER0_VAL);
}
@@ -135,7 +135,7 @@ static void __init orion_timer_init(struct device_node *np)
clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
clk_get_rate(clk), 300, 32,
clocksource_mmio_readl_down);
- setup_sched_clock(orion_read_sched_clock, 32, clk_get_rate(clk));
+ sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk));
/* setup timer1 as clockevent timer */
if (setup_irq(irq, &orion_clkevt_irq))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 12/20] clocksource: clksrc-of: Warn if no clock sources are found
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (9 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 11/20] clocksource: orion: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 13/20] clocksource: armada-370-xp: Enable timer divider only when needed Daniel Lezcano
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
Many platforms rely on clocksource_of_init() being implicitly
called for registering clock sources and will get zero warnings
if no working clock source is available. Let's print a critical
error message if no clock source is found.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/clksrc-of.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c
index 35639cf4..a30b42c 100644
--- a/drivers/clocksource/clksrc-of.c
+++ b/drivers/clocksource/clksrc-of.c
@@ -28,6 +28,7 @@ void __init clocksource_of_init(void)
struct device_node *np;
const struct of_device_id *match;
clocksource_of_init_fn init_func;
+ unsigned clocksources = 0;
for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
if (!of_device_is_available(np))
@@ -36,5 +37,8 @@ void __init clocksource_of_init(void)
init_func = match->data;
init_func(np);
of_node_put(np);
+ clocksources++;
}
+ if (!clocksources)
+ pr_crit("%s: no matching clocksources found\n", __func__);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 13/20] clocksource: armada-370-xp: Enable timer divider only when needed
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (10 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 12/20] clocksource: clksrc-of: Warn if no clock sources are found Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 14/20] clocksource: sh_tmu: Remove unnecessary platform_set_drvdata() Daniel Lezcano
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
The current code sets the timer divider bits always. However, when
the 25 MHz timer is enabled, this is not needed and has no effect.
As this causes some confusion, rework the code so the divider is
set only when needed, i.e. when the 25 MHz timer is not in use.
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/time-armada-370-xp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index d8e47e5..0450f6b 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -76,6 +76,7 @@
static void __iomem *timer_base, *local_base;
static unsigned int timer_clk;
static bool timer25Mhz = true;
+static u32 enable_mask;
/*
* Number of timer ticks per jiffy.
@@ -121,8 +122,7 @@ armada_370_xp_clkevt_next_event(unsigned long delta,
/*
* Enable the timer.
*/
- local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
- TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+ local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
return 0;
}
@@ -141,9 +141,7 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode,
/*
* Enable timer.
*/
- local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
- TIMER0_EN |
- TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+ local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
} else {
/*
* Disable timer.
@@ -240,10 +238,13 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
WARN_ON(!timer_base);
local_base = of_iomap(np, 1);
- if (timer25Mhz)
+ if (timer25Mhz) {
set = TIMER0_25MHZ;
- else
+ enable_mask = TIMER0_EN;
+ } else {
clr = TIMER0_25MHZ;
+ enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
+ }
timer_ctrl_clrset(clr, set);
local_timer_ctrl_clrset(clr, set);
@@ -267,8 +268,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
- timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
- TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+ timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
"armada_370_xp_clocksource",
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 14/20] clocksource: sh_tmu: Remove unnecessary platform_set_drvdata()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (11 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 13/20] clocksource: armada-370-xp: Enable timer divider only when needed Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 15/20] clocksource: sh_mtu2: " Daniel Lezcano
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingoo Han <jg1.han@samsung.com>
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/sh_tmu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 78b8dae..54ab475 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -509,7 +509,6 @@ static int sh_tmu_probe(struct platform_device *pdev)
ret = sh_tmu_setup(p, pdev);
if (ret) {
kfree(p);
- platform_set_drvdata(pdev, NULL);
pm_runtime_idle(&pdev->dev);
return ret;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 15/20] clocksource: sh_mtu2: Remove unnecessary platform_set_drvdata()
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (12 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 14/20] clocksource: sh_tmu: Remove unnecessary platform_set_drvdata() Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 16/20] clocksource: misc drivers: Remove deprecated IRQF_DISABLED Daniel Lezcano
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Jingoo Han <jg1.han@samsung.com>
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/sh_mtu2.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 4aac9ee..f02648e 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -346,7 +346,6 @@ static int sh_mtu2_probe(struct platform_device *pdev)
ret = sh_mtu2_setup(p, pdev);
if (ret) {
kfree(p);
- platform_set_drvdata(pdev, NULL);
pm_runtime_idle(&pdev->dev);
return ret;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 16/20] clocksource: misc drivers: Remove deprecated IRQF_DISABLED
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (13 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 15/20] clocksource: sh_mtu2: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 17/20] clocksource: tegra: " Daniel Lezcano
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Michael Opdenacker <michael.opdenacker@free-electrons.com>
This patch removes the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/cadence_ttc_timer.c | 3 +--
drivers/clocksource/cs5535-clockevt.c | 2 +-
drivers/clocksource/dw_apb_timer.c | 3 +--
drivers/clocksource/nomadik-mtu.c | 2 +-
drivers/clocksource/samsung_pwm_timer.c | 2 +-
drivers/clocksource/sh_cmt.c | 3 +--
drivers/clocksource/sh_mtu2.c | 3 +--
drivers/clocksource/sh_tmu.c | 3 +--
8 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index b865b4e..8c7382b 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -388,8 +388,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
err = request_irq(irq, ttc_clock_event_interrupt,
- IRQF_DISABLED | IRQF_TIMER,
- ttcce->ce.name, ttcce);
+ IRQF_TIMER, ttcce->ce.name, ttcce);
if (WARN_ON(err)) {
kfree(ttcce);
return;
diff --git a/drivers/clocksource/cs5535-clockevt.c b/drivers/clocksource/cs5535-clockevt.c
index ea21048..db21052 100644
--- a/drivers/clocksource/cs5535-clockevt.c
+++ b/drivers/clocksource/cs5535-clockevt.c
@@ -131,7 +131,7 @@ static irqreturn_t mfgpt_tick(int irq, void *dev_id)
static struct irqaction mfgptirq = {
.handler = mfgpt_tick,
- .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
+ .flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
.name = DRV_NAME,
};
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index e54ca10..f3656a6 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -243,8 +243,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
dw_ced->irqaction.dev_id = &dw_ced->ced;
dw_ced->irqaction.irq = irq;
dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
- IRQF_NOBALANCING |
- IRQF_DISABLED;
+ IRQF_NOBALANCING;
dw_ced->eoi = apbt_eoi;
err = setup_irq(irq, &dw_ced->irqaction);
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index ed7b73b..152a3f3 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -187,7 +187,7 @@ static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
static struct irqaction nmdk_timer_irq = {
.name = "Nomadik Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER,
+ .flags = IRQF_TIMER,
.handler = nmdk_timer_interrupt,
.dev_id = &nmdk_clkevt,
};
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 85082e8..5645cfc 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -264,7 +264,7 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
static struct irqaction samsung_clock_event_irq = {
.name = "samsung_time_irq",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = samsung_clock_event_isr,
.dev_id = &time_event_device,
};
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 0965e98..c618633 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -726,8 +726,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
p->irqaction.name = dev_name(&p->pdev->dev);
p->irqaction.handler = sh_cmt_interrupt;
p->irqaction.dev_id = p;
- p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
- IRQF_IRQPOLL | IRQF_NOBALANCING;
+ p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
/* get hold of clock */
p->clk = clk_get(&p->pdev->dev, "cmt_fck");
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index f02648e..b6a56b1 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -302,8 +302,7 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
p->irqaction.handler = sh_mtu2_interrupt;
p->irqaction.dev_id = p;
p->irqaction.irq = irq;
- p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
- IRQF_IRQPOLL | IRQF_NOBALANCING;
+ p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
/* get hold of clock */
p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 54ab475..fc752f7 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -462,8 +462,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
p->irqaction.handler = sh_tmu_interrupt;
p->irqaction.dev_id = p;
p->irqaction.irq = irq;
- p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
- IRQF_IRQPOLL | IRQF_NOBALANCING;
+ p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
/* get hold of clock */
p->clk = clk_get(&p->pdev->dev, "tmu_fck");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 17/20] clocksource: tegra: Remove deprecated IRQF_DISABLED
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (14 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 16/20] clocksource: misc drivers: Remove deprecated IRQF_DISABLED Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 18/20] clocksource: vt8500: " Daniel Lezcano
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Michael Opdenacker <michael.opdenacker@free-electrons.com>
This patch removes the use of the IRQF_DISABLED flag.
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/tegra20_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 6428492..d1869f0 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -149,7 +149,7 @@ static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
static struct irqaction tegra_timer_irq = {
.name = "timer0",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
+ .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
.handler = tegra_timer_interrupt,
.dev_id = &tegra_clockevent,
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 18/20] clocksource: vt8500: Remove deprecated IRQF_DISABLED
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (15 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 17/20] clocksource: tegra: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 19/20] clocksource: bcm_kona_timer: Remove unused bcm_timer_ids Daniel Lezcano
2013-12-30 10:19 ` [PATCH 20/20] clocksource: sh_cmt: Add clk_prepare/unprepare support Daniel Lezcano
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Michael Opdenacker <michael.opdenacker@free-electrons.com>
This patch removes the use of the IRQF_DISABLED flag.
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/vt8500_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index ad3c0e8..1098ed3 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -124,7 +124,7 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
static struct irqaction irq = {
.name = "vt8500_timer",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = vt8500_timer_interrupt,
.dev_id = &clockevent,
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 19/20] clocksource: bcm_kona_timer: Remove unused bcm_timer_ids
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (16 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 18/20] clocksource: vt8500: " Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
2013-12-30 10:19 ` [PATCH 20/20] clocksource: sh_cmt: Add clk_prepare/unprepare support Daniel Lezcano
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Axel Lin <axel.lin@ingics.com>
bcm_timer_ids is no longer used after converting to CLOCKSOURCE_OF_DECLARE.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/bcm_kona_timer.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/clocksource/bcm_kona_timer.c b/drivers/clocksource/bcm_kona_timer.c
index 0d7d8c3..5176e76 100644
--- a/drivers/clocksource/bcm_kona_timer.c
+++ b/drivers/clocksource/bcm_kona_timer.c
@@ -98,12 +98,6 @@ kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw)
return;
}
-static const struct of_device_id bcm_timer_ids[] __initconst = {
- {.compatible = "brcm,kona-timer"},
- {.compatible = "bcm,kona-timer"}, /* deprecated name */
- {},
-};
-
static void __init kona_timers_init(struct device_node *node)
{
u32 freq;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 20/20] clocksource: sh_cmt: Add clk_prepare/unprepare support
2013-12-30 10:19 ` [PATCH 01/20] clockevent: sun4i: Fill the irq field in the clockevent structure Daniel Lezcano
` (17 preceding siblings ...)
2013-12-30 10:19 ` [PATCH 19/20] clocksource: bcm_kona_timer: Remove unused bcm_timer_ids Daniel Lezcano
@ 2013-12-30 10:19 ` Daniel Lezcano
18 siblings, 0 replies; 23+ messages in thread
From: Daniel Lezcano @ 2013-12-30 10:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/sh_cmt.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 0965e98..940341a 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -634,12 +634,18 @@ static int sh_cmt_clock_event_next(unsigned long delta,
static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
{
- pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev);
+ struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+ pm_genpd_syscore_poweroff(&p->pdev->dev);
+ clk_unprepare(p->clk);
}
static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
{
- pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev);
+ struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+ clk_prepare(p->clk);
+ pm_genpd_syscore_poweron(&p->pdev->dev);
}
static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
@@ -737,6 +743,10 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
goto err2;
}
+ ret = clk_prepare(p->clk);
+ if (ret < 0)
+ goto err3;
+
if (res2 && (resource_size(res2) == 4)) {
/* assume both CMSTR and CMCSR to be 32-bit */
p->read_control = sh_cmt_read32;
@@ -773,19 +783,21 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
cfg->clocksource_rating);
if (ret) {
dev_err(&p->pdev->dev, "registration failed\n");
- goto err3;
+ goto err4;
}
p->cs_enabled = false;
ret = setup_irq(irq, &p->irqaction);
if (ret) {
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
- goto err3;
+ goto err4;
}
platform_set_drvdata(pdev, p);
return 0;
+err4:
+ clk_unprepare(p->clk);
err3:
clk_put(p->clk);
err2:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread