* about last level cache on big little cpu
@ 2014-02-03 14:51 Alex Shi
2014-02-03 15:03 ` Morten Rasmussen
2014-02-03 15:56 ` Sudeep Holla
0 siblings, 2 replies; 3+ messages in thread
From: Alex Shi @ 2014-02-03 14:51 UTC (permalink / raw)
To: linux-arm-kernel
Does all the big.LITTLE cpu share the same llc? or it depends on
different vendor's products?
--
Thanks
Alex
^ permalink raw reply [flat|nested] 3+ messages in thread
* about last level cache on big little cpu
2014-02-03 14:51 about last level cache on big little cpu Alex Shi
@ 2014-02-03 15:03 ` Morten Rasmussen
2014-02-03 15:56 ` Sudeep Holla
1 sibling, 0 replies; 3+ messages in thread
From: Morten Rasmussen @ 2014-02-03 15:03 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 03, 2014 at 02:51:08PM +0000, Alex Shi wrote:
> Does all the big.LITTLE cpu share the same llc? or it depends on
> different vendor's products?
No. I don't know of any big.LITTLE implementation that does have a
shared last level cache. TC2 has per cluster L2 caches as last level
caches, so no cache is shared between the big and little clusters.
Morten
^ permalink raw reply [flat|nested] 3+ messages in thread
* about last level cache on big little cpu
2014-02-03 14:51 about last level cache on big little cpu Alex Shi
2014-02-03 15:03 ` Morten Rasmussen
@ 2014-02-03 15:56 ` Sudeep Holla
1 sibling, 0 replies; 3+ messages in thread
From: Sudeep Holla @ 2014-02-03 15:56 UTC (permalink / raw)
To: linux-arm-kernel
On 03/02/14 14:51, Alex Shi wrote:
> Does all the big.LITTLE cpu share the same llc? or it depends on
> different vendor's products?
>
It depends on implementation. e.g. on Cortex-A7 L2 is optional.
So there can be big.LITTLE system with CA15(with L2) and CA7(without L2).
In general depends are the choice of the processors in bL and if L2
is mandatory or optional on those processors.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-02-03 14:51 about last level cache on big little cpu Alex Shi
2014-02-03 15:03 ` Morten Rasmussen
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