From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CE39C4167D for ; Mon, 6 Nov 2023 11:02:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IQ0W2lGmA3v5M8upYOPkbo1Uyq9ik/6GM0pPqltXdvc=; b=2P81Md6VNf3ogv 5UHF8Tfhp5cEF28IwOyUTuN7elO0PJ8sXk4+C9R2TyY6mKXdYJg3votXDDfmtq+vsgmp2L9w4NY/r LIIHr8zyJ3VJNGNjCkq6jCbsjWxT74ywsgsr2coQUZBgORzDOvyTi1R3oAFFjvh3X9xjbK4eJjVva PLphEuEHK4tUOd3AT6xhjxac9M3wRCPj9+DQdP/TYwzZf7wsLgXcSapM3+l/5M+gfN0cOENgFtL8d hfAxUlaVjdli2pY+6DFYSNMTHcET88Ljd8SNp66nyrNxOmS92komd6A5b7wXIwJ0tuIMgSi3zXsGd Ud1Qcli4HNgUN2bz7tNA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qzxN9-00GJ1e-0p; Mon, 06 Nov 2023 11:02:23 +0000 Received: from eu-smtp-delivery-151.mimecast.com ([185.58.85.151]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qzxN6-00GIzr-0k for linux-arm-kernel@lists.infradead.org; Mon, 06 Nov 2023 11:02:21 +0000 Received: from AcuMS.aculab.com (156.67.243.121 [156.67.243.121]) by relay.mimecast.com with ESMTP with both STARTTLS and AUTH (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id uk-mta-44-NNK0qxekP9KmzfnMHlHj9Q-1; Mon, 06 Nov 2023 11:02:13 +0000 X-MC-Unique: NNK0qxekP9KmzfnMHlHj9Q-1 Received: from AcuMS.Aculab.com (10.202.163.4) by AcuMS.aculab.com (10.202.163.4) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 6 Nov 2023 11:02:12 +0000 Received: from AcuMS.Aculab.com ([::1]) by AcuMS.aculab.com ([::1]) with mapi id 15.00.1497.048; Mon, 6 Nov 2023 11:02:12 +0000 From: David Laight To: 'David Epping' CC: "linux-arm-kernel@lists.infradead.org" , Dinh Nguyen , Lorenzo Pieralisi , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Bjorn Helgaas , =?iso-8859-2?Q?Krzysztof_Wilczy=F1ski?= Subject: RE: mach-socfpga: PCIe Root IO TLP support for Cyclone V Thread-Topic: mach-socfpga: PCIe Root IO TLP support for Cyclone V Thread-Index: AQHaC+rcwX/RJWhaCEGpb3NmFV615LBrmEmQgAGENICAAApRcA== Date: Mon, 6 Nov 2023 11:02:12 +0000 Message-ID: <531d4fadcc694f9582af54f3998720b4@AcuMS.aculab.com> References: In-Reply-To: Accept-Language: en-GB, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: aculab.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231106_030220_538092_8EBBEB8A X-CRM114-Status: GOOD ( 24.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: David Epping > Sent: 06 November 2023 10:15 > > On Sun, Nov 05, 2023 at 11:20:03AM +0000, David Laight wrote: ... > > If you are building the FPGA image then all the logic to convert the > > memory mapped slave cycles (into the fpga logic) is supplied as > > verilog source. > > The CPU subsystem and the PCIe IP are hard IP in silicon and can not be altered. If you look carefully you'll find that the 'hard IP' block stops with a streaming interface that carries the data TLP. All the logic to convert the TLP into Avalon memory cycles is verilog source. So, at least in principle, it is modifiable. With a bit of effort it is possible to trace the TLP into fpga memory. (We had to modify the verilog to expose the TX TLP.) Even allowing for development time it was probably cheaper than buying a PCIe monitor! > They are connected via the FPGA logic, though, and I agree one approach could be to intercept their > communication with custom HDL. > However, Linux uses the exact same PCIe hard IP registers required for IO TLPs to send Config TLPs. > Every TLP requires multiple accesses to multiple registers, so locking between FPGA logic and Linux > transactions would be required. > I'm not saying that this is impossible, but I don't think it can be robust without a Linux software > change. > A software only solution has the benefit of being available to all users of such an FPGA, without > access to that special logic. I saw/checked you'd added a lock, didn't see it was the same one used for config space accesses. > > I thought that all recent endpoints were required [1] to work with > > just memory BARs - even going back to the later PCI versions. > > So I'm surprised a PCIe endpoint need an IO BAR. > > The AX99100 implements a so called "Legacy Endpoint" and is thus allowed to > rely on support for IO space. > I guess this choice was made to stay driver-compatible to the PCI version, > although I don't know the ancestry if this product. A lot of PCI devices solved this by adding a memory BAR that mapped exactly the same registers. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel