From: sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 03/14] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU
Date: Wed, 26 Mar 2014 12:52:40 +0100 [thread overview]
Message-ID: <5332BF88.5020401@gmail.com> (raw)
In-Reply-To: <1395787705-31061-4-git-send-email-gregory.clement@free-electrons.com>
On 03/25/2014 11:48 PM, Gregory CLEMENT wrote:
> ll_set_cpu_coherent is always used on the current CPU, so instead of
> passing the CPU id as argument, ll_set_cpu_coherent() can find it by
> itself.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
[...]
> diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
> index 1f2bcd4b5424..6cb26b919787 100644
> --- a/arch/arm/mach-mvebu/coherency_ll.S
> +++ b/arch/arm/mach-mvebu/coherency_ll.S
> @@ -24,9 +24,7 @@
> #include <asm/cp15.h>
>
> .text
> -/*
> - * r0: HW CPU id
> - */
> +
> ENTRY(ll_set_cpu_coherent)
> mrc p15, 0, r1, c1, c0, 0
> tst r1, #CR_M @ Check MMU bit enabled
> @@ -43,9 +41,11 @@ ENTRY(ll_set_cpu_coherent)
> ldr r0, [r0]
> 2:
> /* Create bit by cpu index */
> - mov r3, #(1 << 24)
> - lsl r1, r3, r1
> -ARM_BE8(rev r1, r1)
> + mrc 15, 0, r1, cr0, cr0, 5
> + and r1, r1, #15
> + mov r2, #(1 << 24)
> + lsl r1, r2, r1
> + ARM_BE8(rev r1, r1)
nit: re-indent ARM_BE8 to the beginning of the line?
Sebastian
next prev parent reply other threads:[~2014-03-26 11:52 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-25 22:48 [PATCH v5 00/14] CPU idle for Armada XP Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 01/14] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 02/14] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 03/14] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-03-26 11:52 ` Sebastian Hesselbarth [this message]
2014-03-26 11:51 ` Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 04/14] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 05/14] ARM: mvebu: Split low level functions to manipulate HW coherency Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 06/14] ARM: mvebu: Low level function to disable HW coherency support Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 07/14] ARM: mvebu: Extend the pmsu registers Gregory CLEMENT
2014-03-26 0:30 ` Jason Cooper
2014-03-26 9:33 ` Gregory CLEMENT
2014-03-26 9:55 ` Sebastian Hesselbarth
2014-03-26 12:04 ` Sebastian Hesselbarth
2014-03-26 12:01 ` Gregory CLEMENT
2014-03-26 12:59 ` Thomas Petazzoni
2014-03-25 22:48 ` [PATCH v5 08/14] ARM: dts: mvebu: Introduce a new compatible for the PMSU node Gregory CLEMENT
2014-03-26 0:32 ` Jason Cooper
2014-03-25 22:48 ` [PATCH v5 09/14] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 10/14] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 11/14] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 12/14] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 13/14] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 14/14] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT
2014-03-26 10:30 ` Ezequiel Garcia
2014-03-26 10:31 ` Thomas Petazzoni
2014-03-26 10:38 ` Gregory CLEMENT
2014-03-26 0:42 ` [PATCH v5 00/14] CPU idle for Armada XP Jason Cooper
2014-03-26 9:53 ` Gregory CLEMENT
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