* [PATCH v4] ARM: mm: fix reporting of read-only PMD bits
@ 2014-03-23 4:20 Kees Cook
2014-03-28 18:45 ` Kees Cook
0 siblings, 1 reply; 3+ messages in thread
From: Kees Cook @ 2014-03-23 4:20 UTC (permalink / raw)
To: linux-arm-kernel
On non-LPAE ARMv6+, read-only PMD bits are defined with the combination
"PMD_SECT_APX | PMD_SECT_AP_WRITE". Adjusted the bit masks to correctly
report this.
Signed-off-by: Kees Cook <keescook@chromium.org>
---
v4:
- clean up defines for CPU versions; Rob Herring.
v3:
- check for pre-v6 CPUs on the page table report.
v2:
- reorder bits, suggested by Olof.
---
arch/arm/mm/dump.c | 47 ++++++++++++++++++++++++++++++++---------------
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index ef69152f9b52..c508f41a43bc 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -120,34 +120,51 @@ static const struct prot_bits pte_bits[] = {
};
static const struct prot_bits section_bits[] = {
-#ifndef CONFIG_ARM_LPAE
- /* These are approximate */
+#ifdef CONFIG_ARM_LPAE
+ {
+ .mask = PMD_SECT_USER,
+ .val = PMD_SECT_USER,
+ .set = "USR",
+ }, {
+ .mask = PMD_SECT_RDONLY,
+ .val = PMD_SECT_RDONLY,
+ .set = "ro",
+ .clear = "RW",
+#elif __LINUX_ARM_ARCH__ >= 6
{
- .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
- .val = 0,
+ .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .val = PMD_SECT_APX | PMD_SECT_AP_WRITE,
.set = " ro",
}, {
- .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_AP_WRITE,
.set = " RW",
}, {
- .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_AP_READ,
.set = "USR ro",
}, {
- .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.set = "USR RW",
-#else
+#else /* ARMv4/ARMv5 */
+ /* These are approximate */
{
- .mask = PMD_SECT_USER,
- .val = PMD_SECT_USER,
- .set = "USR",
+ .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .val = 0,
+ .set = " ro",
}, {
- .mask = PMD_SECT_RDONLY,
- .val = PMD_SECT_RDONLY,
- .set = "ro",
- .clear = "RW",
+ .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .val = PMD_SECT_AP_WRITE,
+ .set = " RW",
+ }, {
+ .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .val = PMD_SECT_AP_READ,
+ .set = "USR ro",
+ }, {
+ .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+ .set = "USR RW",
#endif
}, {
.mask = PMD_SECT_XN,
--
1.7.9.5
--
Kees Cook
Chrome OS Security
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v4] ARM: mm: fix reporting of read-only PMD bits
2014-03-23 4:20 [PATCH v4] ARM: mm: fix reporting of read-only PMD bits Kees Cook
@ 2014-03-28 18:45 ` Kees Cook
2014-03-31 18:12 ` Laura Abbott
0 siblings, 1 reply; 3+ messages in thread
From: Kees Cook @ 2014-03-28 18:45 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Mar 22, 2014 at 9:20 PM, Kees Cook <keescook@chromium.org> wrote:
> On non-LPAE ARMv6+, read-only PMD bits are defined with the combination
> "PMD_SECT_APX | PMD_SECT_AP_WRITE". Adjusted the bit masks to correctly
> report this.
>
> Signed-off-by: Kees Cook <keescook@chromium.org>
> ---
> v4:
> - clean up defines for CPU versions; Rob Herring.
> v3:
> - check for pre-v6 CPUs on the page table report.
> v2:
> - reorder bits, suggested by Olof.
Can anyone give this a test or ack? I've done build tests for all CPU
combinations, and runtime tests on v6 and LPAE.
Thanks!
-Kees
> ---
> arch/arm/mm/dump.c | 47 ++++++++++++++++++++++++++++++++---------------
> 1 file changed, 32 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
> index ef69152f9b52..c508f41a43bc 100644
> --- a/arch/arm/mm/dump.c
> +++ b/arch/arm/mm/dump.c
> @@ -120,34 +120,51 @@ static const struct prot_bits pte_bits[] = {
> };
>
> static const struct prot_bits section_bits[] = {
> -#ifndef CONFIG_ARM_LPAE
> - /* These are approximate */
> +#ifdef CONFIG_ARM_LPAE
> + {
> + .mask = PMD_SECT_USER,
> + .val = PMD_SECT_USER,
> + .set = "USR",
> + }, {
> + .mask = PMD_SECT_RDONLY,
> + .val = PMD_SECT_RDONLY,
> + .set = "ro",
> + .clear = "RW",
> +#elif __LINUX_ARM_ARCH__ >= 6
> {
> - .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> - .val = 0,
> + .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .val = PMD_SECT_APX | PMD_SECT_AP_WRITE,
> .set = " ro",
> }, {
> - .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> .val = PMD_SECT_AP_WRITE,
> .set = " RW",
> }, {
> - .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> .val = PMD_SECT_AP_READ,
> .set = "USR ro",
> }, {
> - .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> .set = "USR RW",
> -#else
> +#else /* ARMv4/ARMv5 */
> + /* These are approximate */
> {
> - .mask = PMD_SECT_USER,
> - .val = PMD_SECT_USER,
> - .set = "USR",
> + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .val = 0,
> + .set = " ro",
> }, {
> - .mask = PMD_SECT_RDONLY,
> - .val = PMD_SECT_RDONLY,
> - .set = "ro",
> - .clear = "RW",
> + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .val = PMD_SECT_AP_WRITE,
> + .set = " RW",
> + }, {
> + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .val = PMD_SECT_AP_READ,
> + .set = "USR ro",
> + }, {
> + .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
> + .set = "USR RW",
> #endif
> }, {
> .mask = PMD_SECT_XN,
> --
> 1.7.9.5
>
>
> --
> Kees Cook
> Chrome OS Security
--
Kees Cook
Chrome OS Security
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v4] ARM: mm: fix reporting of read-only PMD bits
2014-03-28 18:45 ` Kees Cook
@ 2014-03-31 18:12 ` Laura Abbott
0 siblings, 0 replies; 3+ messages in thread
From: Laura Abbott @ 2014-03-31 18:12 UTC (permalink / raw)
To: linux-arm-kernel
On 3/28/2014 11:45 AM, Kees Cook wrote:
> On Sat, Mar 22, 2014 at 9:20 PM, Kees Cook <keescook@chromium.org> wrote:
>> On non-LPAE ARMv6+, read-only PMD bits are defined with the combination
>> "PMD_SECT_APX | PMD_SECT_AP_WRITE". Adjusted the bit masks to correctly
>> report this.
>>
>> Signed-off-by: Kees Cook <keescook@chromium.org>
>> ---
>> v4:
>> - clean up defines for CPU versions; Rob Herring.
>> v3:
>> - check for pre-v6 CPUs on the page table report.
>> v2:
>> - reorder bits, suggested by Olof.
>
> Can anyone give this a test or ack? I've done build tests for all CPU
> combinations, and runtime tests on v6 and LPAE.
>
> Thanks!
>
> -Kees
>
You are welcome to add
Tested-by: Laura Abbott <lauraa@codeaurora.org>
Laura
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-03-23 4:20 [PATCH v4] ARM: mm: fix reporting of read-only PMD bits Kees Cook
2014-03-28 18:45 ` Kees Cook
2014-03-31 18:12 ` Laura Abbott
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