From mboxrd@z Thu Jan  1 00:00:00 1970
From: marc.zyngier@arm.com (Marc Zyngier)
Date: Tue, 15 Apr 2014 13:42:53 +0100
Subject: [PATCH 2/5] ARM: dts: Device tree for AXM55xx.
In-Reply-To: <02c006a6fc64131df82981abbc1c71c7af52254e.1397552154.git.anders.berg@lsi.com>
References: <cover.1397552154.git.anders.berg@lsi.com>
 <02c006a6fc64131df82981abbc1c71c7af52254e.1397552154.git.anders.berg@lsi.com>
Message-ID: <534D294D.7000201@arm.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi Anders,

On 15/04/14 13:06, Anders Berg wrote:
> Add device tree for the Amarillo validation board with an AXM5516 SoC.
> 
> Signed-off-by: Anders Berg <anders.berg@lsi.com>
> ---
>  arch/arm/boot/dts/Makefile             |   1 +
>  arch/arm/boot/dts/axm5516-amarillo.dts |  51 ++++++
>  arch/arm/boot/dts/axm5516-cpus.dtsi    | 204 ++++++++++++++++++++++
>  arch/arm/boot/dts/axm55xx.dtsi         | 306 +++++++++++++++++++++++++++++++++
>  4 files changed, 562 insertions(+)
>  create mode 100644 arch/arm/boot/dts/axm5516-amarillo.dts
>  create mode 100644 arch/arm/boot/dts/axm5516-cpus.dtsi
>  create mode 100644 arch/arm/boot/dts/axm55xx.dtsi
> 

[...]

> +       gic: interrupt-controller at 2001001000 {
> +               compatible = "arm,cortex-a15-gic";
> +               #interrupt-cells = <3>;
> +               #address-cells = <0>;
> +               interrupt-controller;
> +               reg = <0x20 0x01001000 0 0x1000>,
> +                     <0x20 0x01002000 0 0x1000>,
> +                     <0x20 0x01004000 0 0x2000>,
> +                     <0x20 0x01006000 0 0x2000>;
> +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> +                               IRQ_TYPE_LEVEL_HIGH)>;
> +       };

Given how many CPUs this system has, what's the catch regarding the GIC?
Is there a second one shadowing this one at the same address for another
set of 8 CPUs? Is there an additional mechanism to IPI the other CPUs?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...