[PATCH v4 0/4] Adds PMU and S2R support for exynos5420

[PATCH v4 0/4] Adds PMU and S2R support for exynos5420

[Abhilash Kesavan]

Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM
patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch)
merged. 
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
https://lkml.org/lkml/2014/5/10/29

Pankaj's patches have the following dependencies:
	[1] mfd: syscon: Support early initialization
	https://lkml.org/lkml/2014/4/8/239
	[2] Daniel Lezcano's Exynos cpuidle refactor patches
	http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29085
	[3] Allow NULL property in syscon_early_regmap_lookup_by_phandle
	https://lkml.org/lkml/2014/5/10/10 and
	https://lkml.org/lkml/2014/4/29/661

Note: Some of the above patches did not apply cleanly on Kgene's for-next branch.

changes since v3:
Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
Tomasz Figa and Alim Akhtar:
	- Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
	- Merged exynos5420_set_core_flag function into powerdown_conf.
	- Removed XXTI_DURATION3 register setting.
	- Updated the commit message and ordered the clock registers in clock
	  patch.
	- Removed the code for SYS_DISP1_BLK_CFG handling.
	- Modified SoC checks to A9 specific checks in PM code. 
	- Updated some comments in the code and added macros for register offsets.
	- Fixed code which was changing pad retention code for older SoCs.

changes since v2:
        - Addressed comments from Tomasz figa
        - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
        - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
          will be sent separately.

changes since v1:
        - Addressed comments from Tomasz figa.
        - restructured/consolidated as per Tomasz figa's PM consolidations for exynos

Tested on Exynos5420 and Exynos5250 based chromebooks (peach-pit and snow).

Abhilash Kesavan (4):
  arm: exynos5: Add PMU support for 5420
  arm: exynos: Modify code to check for cortex A9 rather than the SoC
  arm: exynos5: Add Suspend-to-RAM support for 5420
  clk: samsung: exynos5420: Setup clocks before system suspend

 arch/arm/mach-exynos/exynos.c        |    1 +
 arch/arm/mach-exynos/pm.c            |  216 ++++++++++++++++++++---
 arch/arm/mach-exynos/pmu.c           |  310 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h      |  239 ++++++++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5420.c |   25 +++
 5 files changed, 769 insertions(+), 22 deletions(-)

-- 
1.7.9.5

[PATCH v4 1/4] arm: exynos5: Add PMU support for 5420

[Abhilash Kesavan]

Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
---
 arch/arm/mach-exynos/exynos.c   |    1 +
 arch/arm/mach-exynos/pmu.c      |  310 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |  238 ++++++++++++++++++++++++++++++
 3 files changed, 549 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index a391e38..c7eda4c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -207,6 +207,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = {
 	{ .compatible = "samsung,exynos4212-pmu" },
 	{ .compatible = "samsung,exynos4412-pmu" },
 	{ .compatible = "samsung,exynos5250-pmu" },
+	{ .compatible = "samsung,exynos5420-pmu" },
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bc3cd3f..c4c363e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/regmap.h>
 
@@ -17,6 +18,8 @@
 #include <linux/slab.h>
 #include <linux/mfd/syscon.h>
 
+#include <asm/cputype.h>
+
 #include "exynos-pmu.h"
 #include "regs-pmu.h"
 
@@ -333,6 +336,151 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
+static struct exynos_pmu_conf exynos5420_pmu_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_ARM_CORE0_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_CORE1_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_CORE2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_CORE3_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE0_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE1_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE3_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ISP_ARM_SYS_PWR_REG,				{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_COMMON_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_COMMON_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_L2_SYS_PWR_REG,				{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_L2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYS_PWR_REG,				{ 0x3, 0x3, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_INTRAM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5420_INTROM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_XUSBXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_XXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GSCL_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_ISP_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MFC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_G3D_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_DISP1_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_MAU_SYS_PWR_REG,				{ 0x7, 0x7, 0x0} },
+	{ EXYNOS5420_G2D_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_MSC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_FSYS_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_FSYS2_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_PSGEN_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_PERIC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_WCORE_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ PMU_TABLE_END,},
+};
+
 static unsigned int const exynos5_list_both_cnt_feed[] = {
 	EXYNOS5_ARM_CORE0_OPTION,
 	EXYNOS5_ARM_CORE1_OPTION,
@@ -353,6 +501,93 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
 	EXYNOS5_ISP_ARM_OPTION,
 };
 
+static unsigned int const exynos5_list_disable_pmu_reg[] = {
+	EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,
+};
+
+static unsigned int const exynos5420_list_disable_pmu_reg[] = {
+	EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
+};
+
+static void exynos5_power_off(void)
+{
+	unsigned int tmp;
+
+	pr_info("Power down.\n");
+	regmap_read(pmu_context->pmu_regmap, EXYNOS_PS_HOLD_CONTROL, &tmp);
+	tmp ^= (1 << 8);
+	regmap_write(pmu_context->pmu_regmap, EXYNOS_PS_HOLD_CONTROL, tmp);
+
+	/* Wait a little so we don't give a false warning below */
+	mdelay(100);
+
+	pr_err("Power down failed, please power off system manually.\n");
+	while (1)
+		;
+}
+
+void exynos5420_powerdown_conf(enum sys_powerdown mode)
+{
+	unsigned int this_cluster;
+	this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+
+	/*
+	 * set the cluster id to IROM register to ensure that we wake
+	 * up with the current cluster.
+	 */
+	regmap_write(pmu_context->pmu_regmap, EXYNOS_IROM_DATA2, this_cluster);
+}
+
 void exynos5_powerdown_conf(enum sys_powerdown mode)
 {
 	unsigned int i;
@@ -430,6 +665,71 @@ static void exynos5250_pmu_init(void)
 	regmap_write(pmu_regmap, EXYNOS5_MASK_WDTRESET_REQUEST, tmp);
 }
 
+static void exynos5420_pmu_init(void)
+{
+	struct regmap *pmu_regmap = pmu_context->pmu_regmap;
+	unsigned int value;
+	int i;
+
+	/*
+	 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
+	 * for local power blocks to Low initially as per Table 8-4:
+	 * "System-Level Power-Down Configuration Registers".
+	 */
+	for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
+		regmap_write(pmu_regmap, exynos5420_list_disable_pmu_reg[i], 0);
+
+	/* Enable USE_STANDBY_WFI for all CORE */
+	regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION,
+			EXYNOS5420_USE_STANDBY_WFI_ALL);
+
+	regmap_read(pmu_regmap, EXYNOS_L2_OPTION(0), &value);
+	value &= ~EXYNOS5_USE_RETENTION;
+	regmap_write(pmu_regmap, EXYNOS_L2_OPTION(0), value);
+
+	regmap_read(pmu_regmap, EXYNOS_L2_OPTION(1), &value);
+	value &= ~EXYNOS5_USE_RETENTION;
+	regmap_write(pmu_regmap, EXYNOS_L2_OPTION(1), value);
+
+	/*
+	 * If L2_COMMON is turned off, clocks related to ATB async
+	 * bridge are gated. Thus, when ISP power is gated, LPI
+	 * may get stuck.
+	 */
+	regmap_read(pmu_regmap, EXYNOS5420_LPI_MASK, &value);
+	value |= EXYNOS5420_ATB_ISP_ARM;
+	regmap_write(pmu_regmap, EXYNOS5420_LPI_MASK, value);
+	regmap_read(pmu_regmap, EXYNOS5420_LPI_MASK1, &value);
+	value |= EXYNOS5420_ATB_KFC;
+	regmap_write(pmu_regmap, EXYNOS5420_LPI_MASK1, value);
+
+	/* Prevent issue of new bus request from L2 memory */
+	regmap_read(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION,
+						&value);
+	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+	regmap_write(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION,
+						value);
+	regmap_read(pmu_regmap, EXYNOS5420_KFC_COMMON_OPTION,
+						&value);
+	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+	regmap_write(pmu_regmap, EXYNOS5420_KFC_COMMON_OPTION, value);
+
+	/* This setting is to reduce suspend/resume time */
+	regmap_write(pmu_regmap, EXYNOS5420_LOGIC_RESET_DURATION3,
+						DUR_WAIT_RESET);
+
+	/* Serialized CPU wakeup of Eagle */
+	regmap_write(pmu_regmap, EXYNOS5420_ARM_INTR_SPREAD_ENABLE,
+						SPREAD_ENABLE);
+	regmap_write(pmu_regmap, EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI,
+					SPREAD_USE_STANDWFI);
+
+	regmap_write(pmu_regmap, EXYNOS5420_UP_SCHEDULER, 0x1);
+
+	pm_power_off = exynos5_power_off;
+	pr_info("EXYNOS5420 PMU initialized\n");
+}
+
 static struct exynos_pmu_data exynos4210_pmu_data = {
 	.pmu_config	= exynos4210_pmu_config,
 };
@@ -449,6 +749,12 @@ static struct exynos_pmu_data exynos5250_pmu_data = {
 	.powerdown_conf	= exynos5_powerdown_conf,
 };
 
+static struct exynos_pmu_data exynos5420_pmu_data = {
+	.pmu_config	= exynos5420_pmu_config,
+	.pmu_init	= exynos5420_pmu_init,
+	.powerdown_conf	= exynos5420_powerdown_conf,
+};
+
 /*
  * PMU platform driver and devicetree bindings.
  */
@@ -469,6 +775,10 @@ static struct of_device_id exynos_pmu_of_device_ids[] = {
 		.compatible = "samsung,exynos5250-pmu",
 		.data = (void *)&exynos5250_pmu_data,
 	},
+	{
+		.compatible = "samsung,exynos5420-pmu",
+		.data = (void *)&exynos5420_pmu_data,
+	},
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d83c7e..8925ab0 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -34,6 +34,7 @@
 #define S5P_INFORM6				0x0818
 #define S5P_INFORM7				0x081C
 
+#define EXYNOS_IROM_DATA2			0x0988
 #define S5P_ARM_CORE0_LOWPWR			0x1000
 #define S5P_DIS_IRQ_CORE0			0x1004
 #define S5P_DIS_IRQ_CENTRAL0			0x1008
@@ -103,6 +104,42 @@
 #define S5P_ARM_CORE1_CONFIGURATION		0x2080
 #define S5P_ARM_CORE1_STATUS			0x2084
 
+#define EXYNOS_ARM_CORE_OPTION(_nr)		(S5P_ARM_CORE0_OPTION \
+						+ ((_nr) * 0x80))
+#define EXYNOS_ARM_CORE_STATUS(_nr)		(S5P_ARM_CORE0_STATUS \
+						+ ((_nr) * 0x80))
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)	\
+			(S5P_ARM_CORE0_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_CORE_LOCAL_PWR_EN		0x3
+
+#define EXYNOS_ARM_COMMON_CONFIGURATION		0x2500
+#define EXYNOS_ARM_COMMON_STATUS		0x2504
+#define EXYNOS_COMMON_CONFIGURATION(_nr)	\
+			(EXYNOS_ARM_COMMON_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_COMMON_STATUS(_nr)		\
+			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_COMMON_OPTION(_nr)		\
+			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
+
+#define EXYNOS_ARM_L2_CONFIGURATION		0x2600
+#define EXYNOS_L2_CONFIGURATION(_nr)		\
+			(EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_L2_STATUS(_nr)			\
+			(EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_L2_OPTION(_nr)			\
+			(EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_L2_COMMON_PWR_EN			0x3
+
+#define EXYNOS_ARM_CORE_X_STATUS_OFFSET		0x4
+
+#define EXYNOS5_APLL_SYSCLK_CONFIGURATION	0x2A00
+#define EXYNOS5_APLL_SYSCLK_STATUS		0x2A04
+
+#define EXYNOS5_ARM_L2_OPTION			0x2608
+#define EXYNOS5_USE_RETENTION			BIT(4)
+
+#define EXYNOS5_L2RSTDISABLE_VALUE		BIT(3)
+
 #define S5P_PAD_RET_MAUDIO_OPTION		0x3028
 #define S5P_PAD_RET_GPIO_OPTION			0x3108
 #define S5P_PAD_RET_UART_OPTION			0x3128
@@ -175,6 +212,7 @@
 #define EXYNOS5_AUTO_WDTRESET_DISABLE				0x0408
 #define EXYNOS5_MASK_WDTRESET_REQUEST				0x040C
 
+#define EXYNOS5_USE_RETENTION			BIT(4)
 #define EXYNOS5_SYS_WDTRESET					(1 << 20)
 
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG				0x1000
@@ -303,4 +341,204 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+/* Only for EXYNOS5420 */
+#define EXYNOS5420_ISP_ARM_OPTION				0x2488
+#define EXYNOS5420_L2RSTDISABLE_VALUE				BIT(3)
+
+#define EXYNOS5420_LPI_MASK					0x0004
+#define EXYNOS5420_LPI_MASK1					0x0008
+#define EXYNOS5420_UFS						BIT(8)
+#define EXYNOS5420_ATB_KFC					BIT(13)
+#define EXYNOS5420_ATB_ISP_ARM					BIT(19)
+#define EXYNOS5420_EMULATION					BIT(31)
+#define ATB_ISP_ARM						BIT(12)
+#define ATB_KFC							BIT(13)
+#define ATB_NOC							BIT(14)
+
+#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE			0x0100
+#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI		0x0104
+#define EXYNOS5420_UP_SCHEDULER					0x0120
+#define SPREAD_ENABLE						0xF
+#define SPREAD_USE_STANDWFI					0xF
+
+#define EXYNOS5420_BB_CON1					0x0784
+#define EXYNOS5420_BB_SEL_EN					BIT(31)
+#define EXYNOS5420_BB_PMOS_EN					BIT(7)
+#define EXYNOS5420_BB_1300X					0XF
+
+#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG			0x1020
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG		0x1024
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG	0x1028
+#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG			0x1030
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG		0x1034
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG	0x1038
+#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG			0x1040
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG		0x1044
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG	0x1048
+#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG			0x1050
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG		0x1054
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG	0x1058
+#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG			0x1060
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG		0x1064
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG	0x1068
+#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG			0x1070
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG		0x1074
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG	0x1078
+#define EXYNOS5420_ISP_ARM_SYS_PWR_REG				0x1090
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG		0x1094
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG		0x1098
+#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG			0x10A0
+#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG			0x10B0
+#define EXYNOS5420_KFC_L2_SYS_PWR_REG				0x10D0
+#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG			0x1158
+#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG			0x115C
+#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG			0x1160
+#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG                      0x1174
+#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG                      0x1178
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG                       0x11B8
+#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG                       0x11BC
+#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR			0x11C0
+#define EXYNOS5420_USBDEV_MEM_SYS_PWR				0x11CC
+#define EXYNOS5420_USBDEV1_MEM_SYS_PWR				0x11D0
+#define EXYNOS5420_SDMMC_MEM_SYS_PWR				0x11D4
+#define EXYNOS5420_CSSYS_MEM_SYS_PWR				0x11D8
+#define EXYNOS5420_SECSS_MEM_SYS_PWR				0x11DC
+#define EXYNOS5420_ROTATOR_MEM_SYS_PWR				0x11E0
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR				0x11E4
+#define EXYNOS5420_INTROM_MEM_SYS_PWR				0x11E8
+#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG		0x1208
+#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG		0x1210
+#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG		0x1214
+#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG		0x1218
+#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG		0x121C
+#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG		0x1220
+#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG		0x1224
+#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG		0x1228
+#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG		0x122C
+#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG		0x1230
+#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG	0x1234
+#define EXYNOS5420_DISP1_SYS_PWR_REG				0x1410
+#define EXYNOS5420_MAU_SYS_PWR_REG				0x1414
+#define EXYNOS5420_G2D_SYS_PWR_REG				0x1418
+#define EXYNOS5420_MSC_SYS_PWR_REG				0x141C
+#define EXYNOS5420_FSYS_SYS_PWR_REG				0x1420
+#define EXYNOS5420_FSYS2_SYS_PWR_REG				0x1424
+#define EXYNOS5420_PSGEN_SYS_PWR_REG				0x1428
+#define EXYNOS5420_PERIC_SYS_PWR_REG				0x142C
+#define EXYNOS5420_WCORE_SYS_PWR_REG				0x1430
+#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG		0x1490
+#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG			0x1494
+#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG			0x1498
+#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG			0x149C
+#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG			0x14A0
+#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG		0x14A4
+#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG		0x14A8
+#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG		0x14AC
+#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG		0x14B0
+#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG		0x14BC
+#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG			0x14D0
+#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG			0x14D4
+#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG			0x14D8
+#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG			0x14DC
+#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG			0x14E0
+#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG			0x14E4
+#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG			0x14E8
+#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG			0x14EC
+#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG			0x14F0
+#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG		0x14F4
+#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG			0x1570
+#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG			0x1574
+#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG			0x1578
+#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG			0x157C
+#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG			0x1590
+#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG			0x1594
+#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG			0x1598
+#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG			0x159C
+#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG			0x15A0
+#define EXYNOS5420_SFR_AXI_CGDIS1				0x15E4
+#define EXYNOS_ARM_CORE2_CONFIGURATION				0x2100
+#define EXYNOS5420_ARM_CORE2_OPTION				0x2108
+#define EXYNOS_ARM_CORE3_CONFIGURATION				0x2180
+#define EXYNOS5420_ARM_CORE3_OPTION				0x2188
+#define EXYNOS5420_ARM_COMMON_STATUS				0x2504
+#define EXYNOS5420_ARM_COMMON_OPTION				0x2508
+#define EXYNOS5420_KFC_COMMON_STATUS				0x2584
+#define EXYNOS5420_KFC_COMMON_OPTION				0x2588
+#define EXYNOS5420_LOGIC_RESET_DURATION3			0x2D1C
+
+#define EXYNOS5420_PAD_RET_GPIO_OPTION				0x30C8
+#define EXYNOS5420_PAD_RET_UART_OPTION				0x30E8
+#define EXYNOS5420_PAD_RET_MMCA_OPTION				0x3108
+#define EXYNOS5420_PAD_RET_MMCB_OPTION				0x3128
+#define EXYNOS5420_PAD_RET_MMCC_OPTION				0x3148
+#define EXYNOS5420_PAD_RET_HSI_OPTION				0x3168
+#define EXYNOS5420_PAD_RET_SPI_OPTION				0x31C8
+#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION			0x31E8
+#define EXYNOS_PAD_RET_DRAM_OPTION				0x3008
+#define EXYNOS_PAD_RET_MAUDIO_OPTION				0x3028
+#define EXYNOS_PAD_RET_JTAG_OPTION				0x3048
+#define EXYNOS_PAD_RET_GPIO_OPTION				0x3108
+#define EXYNOS_PAD_RET_UART_OPTION				0x3128
+#define EXYNOS_PAD_RET_MMCA_OPTION				0x3148
+#define EXYNOS_PAD_RET_MMCB_OPTION				0x3168
+#define EXYNOS_PAD_RET_EBIA_OPTION				0x3188
+#define EXYNOS_PAD_RET_EBIB_OPTION				0x31A8
+
+#define EXYNOS_PS_HOLD_CONTROL					0x330C
+
+/* For SYS_PWR_REG */
+#define EXYNOS_SYS_PWR_CFG					BIT(0)
+
+#define EXYNOS5420_MFC_CONFIGURATION				0x4060
+#define EXYNOS5420_MFC_STATUS					0x4064
+#define EXYNOS5420_MFC_OPTION					0x4068
+#define EXYNOS5420_G3D_CONFIGURATION				0x4080
+#define EXYNOS5420_G3D_STATUS					0x4084
+#define EXYNOS5420_G3D_OPTION					0x4088
+#define EXYNOS5420_DISP0_CONFIGURATION				0x40A0
+#define EXYNOS5420_DISP0_STATUS					0x40A4
+#define EXYNOS5420_DISP0_OPTION					0x40A8
+#define EXYNOS5420_DISP1_CONFIGURATION				0x40C0
+#define EXYNOS5420_DISP1_STATUS					0x40C4
+#define EXYNOS5420_DISP1_OPTION					0x40C8
+#define EXYNOS5420_MAU_CONFIGURATION				0x40E0
+#define EXYNOS5420_MAU_STATUS					0x40E4
+#define EXYNOS5420_MAU_OPTION					0x40E8
+#define EXYNOS5420_FSYS2_OPTION					0x4168
+#define EXYNOS5420_PSGEN_OPTION					0x4188
+
+/* For EXYNOS_CENTRAL_SEQ_OPTION */
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0			BIT(16)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1			BUT(17)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0			BIT(24)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1			BIT(25)
+
+#define EXYNOS5420_ARM_USE_STANDBY_WFI0				BIT(4)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI1				BIT(5)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI2				BIT(6)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI3				BIT(7)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI0				BIT(8)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI1				BIT(9)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI2				BIT(10)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI3				BIT(11)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE0				BIT(16)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE1				BIT(17)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE2				BIT(18)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE3				BIT(19)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE0				BIT(20)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE1				BIT(21)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE2				BIT(22)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE3				BIT(23)
+
+#define DUR_WAIT_RESET				0xF
+
+#define EXYNOS5420_USE_STANDBY_WFI_ALL	(EXYNOS5420_ARM_USE_STANDBY_WFI0    \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI1  \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI2  \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI3  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI0  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI1  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

[PATCH v4 2/4] arm: exynos: Modify code to check for cortex A9 rather than the SoC

[Abhilash Kesavan]

We have an soc check to ensure that the scu and certain A9 specific
registers are not accessed on Exynos5250 (which is A15 based).

Rather than adding another soc specific check for 5420 let us test
for the Cortex A9 primary part number.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/pm.c |   15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 5effd38..95f8086 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -248,7 +248,7 @@ static int exynos_pm_suspend(void)
 	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 	regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, tmp);
 
-	if (!soc_is_exynos5250())
+	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 		exynos_cpu_save_register();
 
 	return 0;
@@ -282,7 +282,7 @@ static void exynos_pm_resume(void)
 	if (exynos_pm_central_resume())
 		goto early_wakeup;
 
-	if (!soc_is_exynos5250())
+	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 		exynos_cpu_restore_register();
 
 	/* For release retention */
@@ -301,7 +301,7 @@ static void exynos_pm_resume(void)
 
 	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-	if (!soc_is_exynos5250())
+	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 		scu_enable(S5P_VA_SCU);
 
 early_wakeup:
@@ -388,15 +388,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,
 	case CPU_PM_ENTER:
 		if (cpu == 0) {
 			exynos_pm_central_suspend();
-			exynos_cpu_save_register();
+			if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
+				exynos_cpu_save_register();
 		}
 		break;
 
 	case CPU_PM_EXIT:
 		if (cpu == 0) {
-			if (!soc_is_exynos5250())
+			if (read_cpuid_part_number() ==
+					ARM_CPU_PART_CORTEX_A9) {
 				scu_enable(S5P_VA_SCU);
-			exynos_cpu_restore_register();
+				exynos_cpu_restore_register();
+			}
 			exynos_pm_central_resume();
 		}
 		break;
-- 
1.7.9.5

[PATCH v4 3/4] arm: exynos5: Add Suspend-to-RAM support for 5420

[Abhilash Kesavan]

Adds Suspend-to-RAM support for EXYNOS5420

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
---
 arch/arm/mach-exynos/pm.c       |  201 +++++++++++++++++++++++++++++++++++----
 arch/arm/mach-exynos/regs-pmu.h |    1 +
 2 files changed, 186 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 95f8086..fddb559 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -22,6 +22,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/regmap.h>
+#include <linux/of_address.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -39,7 +40,13 @@
 #include "regs-sys.h"
 #include "exynos-pmu.h"
 
+#define EXYNOS5420_CPU_ADDR	0x1c
+#define EXYNOS5420_CPU_STATE	0x28
+
 static struct regmap *pmu_regmap;
+static int exynos5420_cpu_state[2];
+static void __iomem *exynos5420_sysram_base;
+static void __iomem *exynos5420_ns_sysram_base;
 
 /**
  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
@@ -64,6 +71,10 @@ static struct sleep_save exynos_core_save[] = {
 	SAVE_ITEM(S5P_SROM_BC3),
 };
 
+static struct sleep_save exynos5420_pmu_reg_save[] = {
+	SAVE_ITEM((void __iomem *)S5P_PMU_SPARE3),
+};
+
 /*
  * GIC wake-up support
  */
@@ -86,7 +97,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 {
 	const struct exynos_wkup_irq *wkup_irq;
 
-	if (soc_is_exynos5250())
+	if (soc_is_exynos5250() || soc_is_exynos5420())
 		wkup_irq = exynos5250_wkup_irq;
 	else
 		wkup_irq = exynos4_wkup_irq;
@@ -187,7 +198,16 @@ static int exynos_cpu_suspend(unsigned long arg)
 	outer_flush_all();
 #endif
 
-	if (soc_is_exynos5250())
+	/*
+	 * Clear sysram register for cpu state so that primary CPU does
+	 * not enter low power start in U-Boot.
+	 * This is specific to exynos5420 SoC only.
+	 */
+	if (soc_is_exynos5420())
+		__raw_writel(0x0,
+			exynos5420_sysram_base + EXYNOS5420_CPU_STATE);
+
+	if (soc_is_exynos5250() || soc_is_exynos5420())
 		flush_cache_all();
 
 	/* issue the standby signal into the pm unit. */
@@ -215,6 +235,24 @@ static void exynos_pm_prepare(void)
 		regmap_read(pmu_regmap, EXYNOS5_JPEG_MEM_OPTION, &tmp);
 		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 		regmap_write(pmu_regmap, EXYNOS5_JPEG_MEM_OPTION, tmp);
+	} else if (soc_is_exynos5420()) {
+		unsigned int i;
+
+		for (i = 0; i < ARRAY_SIZE(exynos5420_pmu_reg_save); i++)
+			regmap_read(pmu_regmap,
+			(unsigned int)exynos5420_pmu_reg_save[i].reg,
+			(unsigned int *)&exynos5420_pmu_reg_save[i].val);
+		/*
+		 * The cpu state needs to be saved and restored so that the
+		 * secondary CPUs will enter low power start. Though the U-Boot
+		 * is setting the cpu state with low power flag, the kernel
+		 * needs to restore it back in case, the primary cpu fails to
+		 * suspend for any reason.
+		 */
+		exynos5420_cpu_state[0] =
+		__raw_readl(exynos5420_sysram_base + EXYNOS5420_CPU_STATE);
+		exynos5420_cpu_state[1] =
+		__raw_readl(exynos5420_ns_sysram_base + EXYNOS5420_CPU_ADDR);
 	}
 
 	/* Set value of power down register for sleep mode */
@@ -225,6 +263,26 @@ static void exynos_pm_prepare(void)
 	/* ensure@least INFORM0 has the resume address */
 
 	regmap_write(pmu_regmap, S5P_INFORM0, virt_to_phys(exynos_cpu_resume));
+
+	if (soc_is_exynos5420()) {
+		regmap_read(pmu_regmap, EXYNOS5_ARM_L2_OPTION, &tmp);
+		tmp &= ~EXYNOS5_USE_RETENTION;
+		regmap_write(pmu_regmap, EXYNOS5_ARM_L2_OPTION, tmp);
+
+		regmap_read(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, &tmp);
+		tmp |= EXYNOS5420_UFS;
+		regmap_write(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, tmp);
+
+		regmap_read(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION, &tmp);
+		tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
+		regmap_write(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION, tmp);
+		regmap_read(pmu_regmap, EXYNOS5420_FSYS2_OPTION, &tmp);
+		tmp |= EXYNOS5420_EMULATION;
+		regmap_write(pmu_regmap, EXYNOS5420_FSYS2_OPTION, tmp);
+		regmap_read(pmu_regmap, EXYNOS5420_PSGEN_OPTION, &tmp);
+		tmp |= EXYNOS5420_EMULATION;
+		regmap_write(pmu_regmap, EXYNOS5420_PSGEN_OPTION, tmp);
+	}
 }
 
 static void exynos_pm_central_suspend(void)
@@ -241,12 +299,22 @@ static int exynos_pm_suspend(void)
 {
 	unsigned int tmp;
 
+	unsigned int this_cluster;
 	exynos_pm_central_suspend();
 
 	/* Setting SEQ_OPTION register */
-
-	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
-	regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, tmp);
+	if (soc_is_exynos5420()) {
+		this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+		if (!this_cluster)
+			regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION,
+					EXYNOS5420_ARM_USE_STANDBY_WFI0);
+		else
+			regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION,
+					EXYNOS5420_KFC_USE_STANDBY_WFI0);
+	} else {
+		tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
+		regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, tmp);
+	}
 
 	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 		exynos_cpu_save_register();
@@ -279,6 +347,19 @@ static int exynos_pm_central_resume(void)
 
 static void exynos_pm_resume(void)
 {
+	unsigned int tmp;
+
+	if (soc_is_exynos5420()) {
+		/* Restore the sysram cpu state register */
+		__raw_writel(exynos5420_cpu_state[0],
+		exynos5420_sysram_base + EXYNOS5420_CPU_STATE);
+		__raw_writel(exynos5420_cpu_state[1],
+		exynos5420_ns_sysram_base + EXYNOS5420_CPU_ADDR);
+
+		regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION,
+				EXYNOS5420_USE_STANDBY_WFI_ALL);
+	}
+
 	if (exynos_pm_central_resume())
 		goto early_wakeup;
 
@@ -287,17 +368,54 @@ static void exynos_pm_resume(void)
 
 	/* For release retention */
 
-	regmap_write(pmu_regmap, S5P_PAD_RET_MAUDIO_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_GPIO_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_UART_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_MMCA_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_MMCB_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_EBIA_OPTION, (1 << 28));
-	regmap_write(pmu_regmap, S5P_PAD_RET_EBIB_OPTION, (1 << 28));
+	if (soc_is_exynos5420()) {
+		regmap_write(pmu_regmap, EXYNOS_PAD_RET_DRAM_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS_PAD_RET_MAUDIO_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS_PAD_RET_JTAG_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_GPIO_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_UART_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCA_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCB_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCC_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_HSI_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS_PAD_RET_EBIA_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS_PAD_RET_EBIB_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_SPI_OPTION,
+								(1 << 28));
+		regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
+								(1 << 28));
+	} else {
+		regmap_write(pmu_regmap, S5P_PAD_RET_MAUDIO_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_GPIO_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_UART_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_MMCA_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_MMCB_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_EBIA_OPTION, (1 << 28));
+		regmap_write(pmu_regmap, S5P_PAD_RET_EBIB_OPTION, (1 << 28));
+	}
 
-	if (soc_is_exynos5250())
+	if (soc_is_exynos5250()) {
 		s3c_pm_do_restore(exynos5_sys_save,
 			ARRAY_SIZE(exynos5_sys_save));
+	} else if (soc_is_exynos5420()) {
+		unsigned int i;
+
+		for (i = 0; i < ARRAY_SIZE(exynos5420_pmu_reg_save); i++)
+			regmap_write(pmu_regmap,
+			(unsigned int)exynos5420_pmu_reg_save[i].reg,
+			(unsigned int)exynos5420_pmu_reg_save[i].val);
+	}
 
 	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
@@ -306,6 +424,18 @@ static void exynos_pm_resume(void)
 
 early_wakeup:
 
+	if (soc_is_exynos5420()) {
+		regmap_read(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, &tmp);
+		tmp &= ~EXYNOS5420_UFS;
+		regmap_write(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, tmp);
+		regmap_read(pmu_regmap, EXYNOS5420_FSYS2_OPTION, &tmp);
+		tmp &= ~EXYNOS5420_EMULATION;
+		regmap_write(pmu_regmap, EXYNOS5420_FSYS2_OPTION, tmp);
+		regmap_read(pmu_regmap, EXYNOS5420_PSGEN_OPTION, &tmp);
+		tmp &= ~EXYNOS5420_EMULATION;
+		regmap_write(pmu_regmap, EXYNOS5420_PSGEN_OPTION, tmp);
+	}
+
 	/* Clear SLEEP mode set in INFORM1 */
 	regmap_write(pmu_regmap, S5P_INFORM1, 0x0);
 
@@ -414,8 +544,41 @@ static struct notifier_block exynos_cpu_pm_notifier_block = {
 
 void __init exynos_pm_init(void)
 {
+	struct device_node *node;
 	u32 tmp;
 
+	if (soc_is_exynos5420()) {
+		node = of_find_compatible_node(NULL, NULL,
+			"samsung,exynos4210-sysram");
+		if (!node) {
+			pr_err("failed to find secure sysram node\n");
+			return;
+		}
+
+		exynos5420_sysram_base = of_iomap(node, 0);
+		of_node_put(node);
+		if (!exynos5420_sysram_base) {
+			pr_err("failed to map secure sysram base address\n");
+			return;
+		}
+
+		node = of_find_compatible_node(NULL, NULL,
+			"samsung,exynos4210-sysram-ns");
+		if (!node) {
+			pr_err("failed to find non-secure sysram node\n");
+			iounmap(exynos5420_sysram_base);
+			return;
+		}
+
+		exynos5420_ns_sysram_base = of_iomap(node, 0);
+		of_node_put(node);
+		if (!exynos5420_ns_sysram_base) {
+			pr_err("failed to map non-secure sysram base address\n");
+			iounmap(exynos5420_sysram_base);
+			return;
+		}
+	}
+
 	pmu_regmap = get_exynos_pmuregmap();
 	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 
@@ -423,9 +586,15 @@ void __init exynos_pm_init(void)
 	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
 	/* All wakeup disable */
-	regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp);
-	tmp |= ((0xFF << 8) | (0x1F << 1));
-	regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp);
+	if (soc_is_exynos5420()) {
+		regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp);
+		tmp |= ((0x7F << 7) | (0x1F << 1));
+		regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp);
+	} else {
+		regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp);
+		tmp |= ((0xFF << 8) | (0x1F << 1));
+		regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp);
+	}
 
 	register_syscore_ops(&exynos_pm_syscore_ops);
 	suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 8925ab0..08a3c00 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -33,6 +33,7 @@
 #define S5P_INFORM5				0x0814
 #define S5P_INFORM6				0x0818
 #define S5P_INFORM7				0x081C
+#define S5P_PMU_SPARE3				0x090c
 
 #define EXYNOS_IROM_DATA2			0x0988
 #define S5P_ARM_CORE0_LOWPWR			0x1000
-- 
1.7.9.5

[PATCH v4 4/4] clk: samsung: exynos5420: Setup clocks before system suspend

[Abhilash Kesavan]

Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.

Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index e576456..dd509d1 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -28,6 +28,7 @@
 #define GATE_BUS_CPU		0x700
 #define GATE_SCLK_CPU		0x800
 #define CLKOUT_CMU_CPU		0xa00
+#define SRC_MASK_CPERI		0x4300
 #define GATE_IP_G2D		0x8800
 #define CPLL_LOCK		0x10020
 #define DPLL_LOCK		0x10030
@@ -66,6 +67,8 @@
 #define SRC_TOP10		0x10280
 #define SRC_TOP11		0x10284
 #define SRC_TOP12		0x10288
+#define SRC_MASK_TOP0		0x10300
+#define SRC_MASK_TOP1		0x10304
 #define SRC_MASK_TOP2		0x10308
 #define SRC_MASK_TOP7		0x1031c
 #define SRC_MASK_DISP10		0x1032c
@@ -73,6 +76,7 @@
 #define SRC_MASK_FSYS		0x10340
 #define SRC_MASK_PERIC0		0x10350
 #define SRC_MASK_PERIC1		0x10354
+#define SRC_MASK_ISP		0x10370
 #define DIV_TOP0		0x10500
 #define DIV_TOP1		0x10504
 #define DIV_TOP2		0x10508
@@ -91,6 +95,7 @@
 #define DIV2_RATIO0		0x10590
 #define DIV4_RATIO		0x105a0
 #define GATE_BUS_TOP		0x10700
+#define GATE_BUS_DISP1		0x10728
 #define GATE_BUS_GEN		0x1073c
 #define GATE_BUS_FSYS0		0x10740
 #define GATE_BUS_FSYS2		0x10748
@@ -115,6 +120,7 @@
 #define GATE_TOP_SCLK_MAU	0x1083c
 #define GATE_TOP_SCLK_FSYS	0x10840
 #define GATE_TOP_SCLK_PERIC	0x10850
+#define GATE_IP_PERIC		0x10950
 #define TOP_SPARE2		0x10b08
 #define BPLL_LOCK		0x20010
 #define BPLL_CON0		0x20110
@@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
 	DIV_KFC0,
 };
 
+static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
+	{ .offset = SRC_MASK_CPERI,		.value = 0xffffffff, },
+	{ .offset = SRC_MASK_TOP0,		.value = 0x11111111, },
+	{ .offset = SRC_MASK_TOP1,		.value = 0x11101111, },
+	{ .offset = SRC_MASK_TOP2,		.value = 0x11111110, },
+	{ .offset = SRC_MASK_TOP7,		.value = 0x00111100, },
+	{ .offset = SRC_MASK_DISP10,		.value = 0x11111110, },
+	{ .offset = SRC_MASK_MAU,		.value = 0x10000000, },
+	{ .offset = SRC_MASK_FSYS,		.value = 0x11111110, },
+	{ .offset = SRC_MASK_PERIC0,		.value = 0x11111110, },
+	{ .offset = SRC_MASK_PERIC1,		.value = 0x11111100, },
+	{ .offset = SRC_MASK_ISP,		.value = 0x11111000, },
+	{ .offset = GATE_BUS_DISP1,		.value = 0xffffffff, },
+	{ .offset = GATE_IP_PERIC,		.value = 0xffffffff, },
+};
+
 static int exynos5420_clk_suspend(void)
 {
 	samsung_clk_save(reg_base, exynos5420_save,
 				ARRAY_SIZE(exynos5420_clk_regs));
 
+	samsung_clk_restore(reg_base, exynos5420_set_clksrc,
+				ARRAY_SIZE(exynos5420_set_clksrc));
+
 	return 0;
 }
 
-- 
1.7.9.5

[PATCH v4 4/4] clk: samsung: exynos5420: Setup clocks before system suspend

[Tomasz Figa]

Hi Abhilash,

On 13.05.2014 14:02, Abhilash Kesavan wrote:
> Prior to suspending the system, we need to ensure that certain
> clock source and gate registers are unmasked.
> 
> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c |   25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index e576456..dd509d1 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -28,6 +28,7 @@
>  #define GATE_BUS_CPU		0x700
>  #define GATE_SCLK_CPU		0x800
>  #define CLKOUT_CMU_CPU		0xa00
> +#define SRC_MASK_CPERI		0x4300
>  #define GATE_IP_G2D		0x8800
>  #define CPLL_LOCK		0x10020
>  #define DPLL_LOCK		0x10030
> @@ -66,6 +67,8 @@
>  #define SRC_TOP10		0x10280
>  #define SRC_TOP11		0x10284
>  #define SRC_TOP12		0x10288
> +#define SRC_MASK_TOP0		0x10300
> +#define SRC_MASK_TOP1		0x10304
>  #define SRC_MASK_TOP2		0x10308
>  #define SRC_MASK_TOP7		0x1031c
>  #define SRC_MASK_DISP10		0x1032c
> @@ -73,6 +76,7 @@
>  #define SRC_MASK_FSYS		0x10340
>  #define SRC_MASK_PERIC0		0x10350
>  #define SRC_MASK_PERIC1		0x10354
> +#define SRC_MASK_ISP		0x10370
>  #define DIV_TOP0		0x10500
>  #define DIV_TOP1		0x10504
>  #define DIV_TOP2		0x10508
> @@ -91,6 +95,7 @@
>  #define DIV2_RATIO0		0x10590
>  #define DIV4_RATIO		0x105a0
>  #define GATE_BUS_TOP		0x10700
> +#define GATE_BUS_DISP1		0x10728
>  #define GATE_BUS_GEN		0x1073c
>  #define GATE_BUS_FSYS0		0x10740
>  #define GATE_BUS_FSYS2		0x10748
> @@ -115,6 +120,7 @@
>  #define GATE_TOP_SCLK_MAU	0x1083c
>  #define GATE_TOP_SCLK_FSYS	0x10840
>  #define GATE_TOP_SCLK_PERIC	0x10850
> +#define GATE_IP_PERIC		0x10950
>  #define TOP_SPARE2		0x10b08
>  #define BPLL_LOCK		0x20010
>  #define BPLL_CON0		0x20110
> @@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
>  	DIV_KFC0,
>  };
>  
> +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
> +	{ .offset = SRC_MASK_CPERI,		.value = 0xffffffff, },
> +	{ .offset = SRC_MASK_TOP0,		.value = 0x11111111, },
> +	{ .offset = SRC_MASK_TOP1,		.value = 0x11101111, },
> +	{ .offset = SRC_MASK_TOP2,		.value = 0x11111110, },
> +	{ .offset = SRC_MASK_TOP7,		.value = 0x00111100, },
> +	{ .offset = SRC_MASK_DISP10,		.value = 0x11111110, },
> +	{ .offset = SRC_MASK_MAU,		.value = 0x10000000, },
> +	{ .offset = SRC_MASK_FSYS,		.value = 0x11111110, },
> +	{ .offset = SRC_MASK_PERIC0,		.value = 0x11111110, },
> +	{ .offset = SRC_MASK_PERIC1,		.value = 0x11111100, },
> +	{ .offset = SRC_MASK_ISP,		.value = 0x11111000, },
> +	{ .offset = GATE_BUS_DISP1,		.value = 0xffffffff, },
> +	{ .offset = GATE_IP_PERIC,		.value = 0xffffffff, },
> +};
> +
>  static int exynos5420_clk_suspend(void)
>  {
>  	samsung_clk_save(reg_base, exynos5420_save,
>  				ARRAY_SIZE(exynos5420_clk_regs));
>  
> +	samsung_clk_restore(reg_base, exynos5420_set_clksrc,
> +				ARRAY_SIZE(exynos5420_set_clksrc));
> +
>  	return 0;
>  }

Don't you also need to add those registers to normal suspend/resume
list, so the values before setting the pre-suspend values are saved on
suspend and then restored on resume?

Otherwise looks good.

Best regards,
Tomasz

[PATCH v4 4/4] clk: samsung: exynos5420: Setup clocks before system suspend

[Abhilash Kesavan]

Hi Tomasz,

On Fri, May 16, 2014 at 2:48 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Abhilash,
>
> On 13.05.2014 14:02, Abhilash Kesavan wrote:
>> Prior to suspending the system, we need to ensure that certain
>> clock source and gate registers are unmasked.
>>
>> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5420.c |   25 +++++++++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index e576456..dd509d1 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -28,6 +28,7 @@
>>  #define GATE_BUS_CPU         0x700
>>  #define GATE_SCLK_CPU                0x800
>>  #define CLKOUT_CMU_CPU               0xa00
>> +#define SRC_MASK_CPERI               0x4300
>>  #define GATE_IP_G2D          0x8800
>>  #define CPLL_LOCK            0x10020
>>  #define DPLL_LOCK            0x10030
>> @@ -66,6 +67,8 @@
>>  #define SRC_TOP10            0x10280
>>  #define SRC_TOP11            0x10284
>>  #define SRC_TOP12            0x10288
>> +#define SRC_MASK_TOP0                0x10300
>> +#define SRC_MASK_TOP1                0x10304
>>  #define SRC_MASK_TOP2                0x10308
>>  #define SRC_MASK_TOP7                0x1031c
>>  #define SRC_MASK_DISP10              0x1032c
>> @@ -73,6 +76,7 @@
>>  #define SRC_MASK_FSYS                0x10340
>>  #define SRC_MASK_PERIC0              0x10350
>>  #define SRC_MASK_PERIC1              0x10354
>> +#define SRC_MASK_ISP         0x10370
>>  #define DIV_TOP0             0x10500
>>  #define DIV_TOP1             0x10504
>>  #define DIV_TOP2             0x10508
>> @@ -91,6 +95,7 @@
>>  #define DIV2_RATIO0          0x10590
>>  #define DIV4_RATIO           0x105a0
>>  #define GATE_BUS_TOP         0x10700
>> +#define GATE_BUS_DISP1               0x10728
>>  #define GATE_BUS_GEN         0x1073c
>>  #define GATE_BUS_FSYS0               0x10740
>>  #define GATE_BUS_FSYS2               0x10748
>> @@ -115,6 +120,7 @@
>>  #define GATE_TOP_SCLK_MAU    0x1083c
>>  #define GATE_TOP_SCLK_FSYS   0x10840
>>  #define GATE_TOP_SCLK_PERIC  0x10850
>> +#define GATE_IP_PERIC                0x10950
>>  #define TOP_SPARE2           0x10b08
>>  #define BPLL_LOCK            0x20010
>>  #define BPLL_CON0            0x20110
>> @@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
>>       DIV_KFC0,
>>  };
>>
>> +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
>> +     { .offset = SRC_MASK_CPERI,             .value = 0xffffffff, },
>> +     { .offset = SRC_MASK_TOP0,              .value = 0x11111111, },
>> +     { .offset = SRC_MASK_TOP1,              .value = 0x11101111, },
>> +     { .offset = SRC_MASK_TOP2,              .value = 0x11111110, },
>> +     { .offset = SRC_MASK_TOP7,              .value = 0x00111100, },
>> +     { .offset = SRC_MASK_DISP10,            .value = 0x11111110, },
>> +     { .offset = SRC_MASK_MAU,               .value = 0x10000000, },
>> +     { .offset = SRC_MASK_FSYS,              .value = 0x11111110, },
>> +     { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
>> +     { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
>> +     { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
>> +     { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
>> +     { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
>> +};
>> +
>>  static int exynos5420_clk_suspend(void)
>>  {
>>       samsung_clk_save(reg_base, exynos5420_save,
>>                               ARRAY_SIZE(exynos5420_clk_regs));
>>
>> +     samsung_clk_restore(reg_base, exynos5420_set_clksrc,
>> +                             ARRAY_SIZE(exynos5420_set_clksrc));
>> +
>>       return 0;
>>  }
>
> Don't you also need to add those registers to normal suspend/resume
> list, so the values before setting the pre-suspend values are saved on
> suspend and then restored on resume?
Yes, I should do that. Will fix and re-send.

Regards,
Abhilash
>
> Otherwise looks good.
>
> Best regards,
> Tomasz
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 0/4] Adds PMU and S2R support for exynos5420

[Tomasz Figa]

Hi Abhilash,

On 13.05.2014 14:01, Abhilash Kesavan wrote:
> Rebased on
> 1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM
> patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch)
> merged. 
> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
> 2] Pankaj Dubey's v4 PMU patchset
> https://lkml.org/lkml/2014/5/10/29

I think this patch is not safe to base on yet. I need to find time to
review the latest version and share my latest view on this with Pankaj,
as I have a bit different design in mind.

In general, I don't like the fact that you end up with using regmap to
access registers that are used exclusively by PMU driver or for accesses
happening at late suspend or early resume, where concurrent accesses
from other drivers simply can't occur.

Best regards,
Tomasz

[PATCH v4 0/4] Adds PMU and S2R support for exynos5420

[Abhilash Kesavan]

Hi Tomasz,

On Fri, May 16, 2014 at 2:52 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Abhilash,
>
> On 13.05.2014 14:01, Abhilash Kesavan wrote:
>> Rebased on
>> 1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM
>> patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch)
>> merged.
>> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
>> 2] Pankaj Dubey's v4 PMU patchset
>> https://lkml.org/lkml/2014/5/10/29
>
> I think this patch is not safe to base on yet. I need to find time to
> review the latest version and share my latest view on this with Pankaj,
> as I have a bit different design in mind.
OK, do you think the PMU series might make it this cycle or should I
drop this as a dependency and re-base my patches just on Daniel's
CPUIdle consolidation.

Regards,
Abhilash
>
> In general, I don't like the fact that you end up with using regmap to
> access registers that are used exclusively by PMU driver or for accesses
> happening at late suspend or early resume, where concurrent accesses
> from other drivers simply can't occur.

>
> Best regards,
> Tomasz
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 0/4] Adds PMU and S2R support for exynos5420

[Tomasz Figa]

On 16.05.2014 07:07, Abhilash Kesavan wrote:
> Hi Tomasz,
> 
> On Fri, May 16, 2014 at 2:52 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Abhilash,
>>
>> On 13.05.2014 14:01, Abhilash Kesavan wrote:
>>> Rebased on
>>> 1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM
>>> patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch)
>>> merged.
>>> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
>>> 2] Pankaj Dubey's v4 PMU patchset
>>> https://lkml.org/lkml/2014/5/10/29
>>
>> I think this patch is not safe to base on yet. I need to find time to
>> review the latest version and share my latest view on this with Pankaj,
>> as I have a bit different design in mind.
> OK, do you think the PMU series might make it this cycle or should I
> drop this as a dependency and re-base my patches just on Daniel's
> CPUIdle consolidation.

I'd say it's too late for 3.16 already, for the PMU series at least.
3.15-rc6 will probably show up in next days and Kukjin still has to send
pull requests to ARM-SoC, so I'd defer this series for 3.17 as well,
especially considering the fact that extending the PMU code in its
current form already met with opposition.

Best regards,
Tomasz