* [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms
@ 2014-05-23 14:27 Thomas Abraham
2014-05-23 14:27 ` [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw)
To: linux-arm-kernel
Changes since v4:
- Various changes in clock code suggested by Tomasz Figa <t.figa@samsung.com>
- This series depends on mutiple other patches
[a] patch that introduces read-only attribute for clock dividers.
- http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259264.html
[b] the series "PM / OPP: move cpufreq specific helpers out of OPP layer"
- https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html
[c] the series "cpufreq: opp: Add device tree based lookup of boost mode frequency"
- http://www.spinics.net/lists/arm-kernel/msg334336.html
Changes since v3:
- Addressed comments from Tomasz Figa <t.figa@samsung.com>
[http://www.spinics.net/lists/cpufreq/msg09290.html]
- Rebased to v3.15-rc4
Changes since v2:
- Safe operating voltage is not required while switching APLL frequency
since the temporary parent's clock is divided down to keep armclk within
permissible limits. Thanks to Heiko Stuebner <heiko@sntech.de> for
suggesting this.
- Rob had suggested to use max frequency for each of the divider clock
outputs instead of divider values. But due to certain SoC specific
characteristics, the divider values corresponding to the input clock
frequency for the CMU_CPU clock blocks have to be used.
Changes since v1:
- Removes Exynos4x12 and Exynos5250 cpufreq driver also.
- Device tree based clock configuration lookup as suggested by Lukasz
Majewski and Tomasz Figa.
- safe operating point binding reworked as suggested by Shawn Guo.
The patch series removes the use of Exynos specific cpufreq driver and enables
the use of cpufreq-cpu0 driver for Exynos4210, Exynos4x12 and Exynos5250 based
platforms. This is being done for few reasons.
(a) The Exynos cpufreq driver reads/writes clock controller registers
bypassing the Exynos CCF driver which is sort of problematic.
(b) Removes the need for having clock controller register definitions
in the cpufreq driver and also removes the need for statically
io-remapping clock controller address space (helps in moving towards
multiplatform kernel).
Thomas Abraham (7):
cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies
clk: samsung: add infrastructure to register cpu clocks
Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5
clk: exynos: use cpu-clock provider type to represent arm clock
ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
ARM: Exynos: switch to using generic cpufreq-cpu0 driver
cpufreq: exynos: remove all exynos specific cpufreq driver support
.../devicetree/bindings/clock/exynos4-clock.txt | 37 ++
.../devicetree/bindings/clock/exynos5250-clock.txt | 36 ++
.../devicetree/bindings/cpufreq/cpufreq-cpu0.txt | 2 +
arch/arm/boot/dts/exynos4210-origen.dts | 6 +
arch/arm/boot/dts/exynos4210-trats.dts | 6 +
arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 +
arch/arm/boot/dts/exynos4210.dtsi | 35 ++
arch/arm/boot/dts/exynos4212.dtsi | 18 +
arch/arm/boot/dts/exynos4412-odroidx.dts | 6 +
arch/arm/boot/dts/exynos4412-origen.dts | 6 +
arch/arm/boot/dts/exynos4412-trats2.dts | 6 +
arch/arm/boot/dts/exynos4412.dtsi | 31 ++
arch/arm/boot/dts/exynos4x12.dtsi | 36 ++
arch/arm/boot/dts/exynos5250-arndale.dts | 6 +
arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 +
arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +
arch/arm/boot/dts/exynos5250.dtsi | 41 ++
arch/arm/mach-exynos/exynos.c | 4 +-
drivers/clk/samsung/Makefile | 2 +-
drivers/clk/samsung/clk-cpu.c | 448 ++++++++++++++++++++
drivers/clk/samsung/clk-exynos4.c | 25 +-
drivers/clk/samsung/clk-exynos5250.c | 16 +-
drivers/clk/samsung/clk.h | 4 +
drivers/cpufreq/Kconfig | 1 +
drivers/cpufreq/Kconfig.arm | 52 ---
drivers/cpufreq/Makefile | 4 -
drivers/cpufreq/cpufreq-cpu0.c | 3 +
drivers/cpufreq/exynos-cpufreq.c | 218 ----------
drivers/cpufreq/exynos-cpufreq.h | 99 -----
drivers/cpufreq/exynos4210-cpufreq.c | 157 -------
drivers/cpufreq/exynos4x12-cpufreq.c | 208 ---------
drivers/cpufreq/exynos5250-cpufreq.c | 183 --------
include/dt-bindings/clock/exynos5250.h | 1 +
33 files changed, 779 insertions(+), 936 deletions(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
delete mode 100644 drivers/cpufreq/exynos-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos-cpufreq.h
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-26 6:12 ` Viresh Kumar 2014-05-23 14:27 ` [PATCH v5 2/7] clk: samsung: add infrastructure to register cpu clocks Thomas Abraham ` (6 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> Lookup for the optional boost-frequency property in cpu0 node and if available, enable support for boost mode frequencies. The frequencies usable in boost mode are determined while preparing the cpufreq table from the list of operating points available. Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt | 2 ++ drivers/cpufreq/Kconfig | 1 + drivers/cpufreq/cpufreq-cpu0.c | 3 +++ 3 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt index f055515..60f321a 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt @@ -19,6 +19,8 @@ Optional properties: - cooling-min-level: - cooling-max-level: Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. +- boost-frequency: + Please refer to Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt Examples: diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index 1fbe11f..52741b9 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -187,6 +187,7 @@ config GENERIC_CPUFREQ_CPU0 tristate "Generic CPU0 cpufreq driver" depends on HAVE_CLK && REGULATOR && OF && THERMAL && CPU_THERMAL select PM_OPP + select CPU_FREQ_BOOST_SW help This adds a generic cpufreq driver for CPU0 frequency management. It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c index 1bf6bba..93d3d6d 100644 --- a/drivers/cpufreq/cpufreq-cpu0.c +++ b/drivers/cpufreq/cpufreq-cpu0.c @@ -194,6 +194,9 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) transition_latency += ret * 1000; } + if (of_find_property(cpu_dev->of_node, "boost-frequencies", NULL)) + cpu0_cpufreq_driver.boost_supported = true; + ret = cpufreq_register_driver(&cpu0_cpufreq_driver); if (ret) { pr_err("failed register driver: %d\n", ret); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies 2014-05-23 14:27 ` [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham @ 2014-05-26 6:12 ` Viresh Kumar 0 siblings, 0 replies; 14+ messages in thread From: Viresh Kumar @ 2014-05-26 6:12 UTC (permalink / raw) To: linux-arm-kernel On 23 May 2014 19:57, Thomas Abraham <thomas.ab@samsung.com> wrote: > From: Thomas Abraham <thomas.ab@samsung.com> > > Lookup for the optional boost-frequency property in cpu0 node and if > available, enable support for boost mode frequencies. The frequencies > usable in boost mode are determined while preparing the cpufreq table > from the list of operating points available. > > Cc: Shawn Guo <shawn.guo@linaro.org> > Cc: Lukasz Majewski <l.majewski@samsung.com> > Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> > --- > .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt | 2 ++ > drivers/cpufreq/Kconfig | 1 + > drivers/cpufreq/cpufreq-cpu0.c | 3 +++ > 3 files changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt > index f055515..60f321a 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt > @@ -19,6 +19,8 @@ Optional properties: > - cooling-min-level: > - cooling-max-level: > Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. > +- boost-frequency: > + Please refer to Documentation/devicetree/bindings/cpufreq/cpufreq-boost.txt > > Examples: > > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig > index 1fbe11f..52741b9 100644 > --- a/drivers/cpufreq/Kconfig > +++ b/drivers/cpufreq/Kconfig > @@ -187,6 +187,7 @@ config GENERIC_CPUFREQ_CPU0 > tristate "Generic CPU0 cpufreq driver" > depends on HAVE_CLK && REGULATOR && OF && THERMAL && CPU_THERMAL > select PM_OPP > + select CPU_FREQ_BOOST_SW Drop this. Select it from your platform driver if you want. > help > This adds a generic cpufreq driver for CPU0 frequency management. > It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) > diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c > index 1bf6bba..93d3d6d 100644 > --- a/drivers/cpufreq/cpufreq-cpu0.c > +++ b/drivers/cpufreq/cpufreq-cpu0.c > @@ -194,6 +194,9 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) > transition_latency += ret * 1000; > } > > + if (of_find_property(cpu_dev->of_node, "boost-frequencies", NULL)) > + cpu0_cpufreq_driver.boost_supported = true; > + > ret = cpufreq_register_driver(&cpu0_cpufreq_driver); > if (ret) { > pr_err("failed register driver: %d\n", ret); > -- > 1.7.9.5 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 2/7] clk: samsung: add infrastructure to register cpu clocks 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Thomas Abraham ` (5 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Cc: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-cpu.c | 448 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 4 + 3 files changed, 453 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/samsung/clk-cpu.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 25646c6..83620a1 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -2,7 +2,7 @@ # Samsung Clock specific Makefile # -obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c new file mode 100644 index 0000000..13fa4c5 --- /dev/null +++ b/drivers/clk/samsung/clk-cpu.c @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Thomas Abraham <thomas.ab@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains the utility functions to register the CPU clocks + * for Samsung platforms. +*/ + +#include <linux/errno.h> +#include "clk.h" + +#define SRC_CPU 0x0 +#define STAT_CPU 0x200 +#define DIV_CPU0 0x300 +#define DIV_CPU1 0x304 +#define DIV_STAT_CPU0 0x400 +#define DIV_STAT_CPU1 0x404 + +#define DIV_CPU0_RATIO0_MASK 0x7 + +#define MAX_DIV 8 + +#define EXYNOS4210_ARM_DIV1(div) ((div & 0x7) + 1) +#define EXYNOS4210_ARM_DIV2(div) (((div >> 28) & 0x7) + 1) + +#define EXYNOS4210_DIV_CPU0(d5, d4, d3, d2, d1, d0) \ + (((d5) << 24) | ((d4) << 20) | ((d3) << 16) | ((d2) << 12) | \ + ((d1) << 8) | ((d0) << 4)) +#define EXYNOS4210_DIV_CPU1(d2, d1, d0) \ + (((d2) << 8) | ((d1) << 4) | ((d0) << 0)) + +#define EXYNOS4210_DIV1_HPM_MASK ((0x7 << 0) | (0x7 << 4)) +#define EXYNOS4210_MUX_HPM_MASK (1 << 20) + +/** + * struct exynos4210_armclk_data: config data to setup exynos4210 cpu clocks. + * @prate: frequency of the parent clock. + * @div0: value to be programmed in the div_cpu0 register. + * @div1: value to be programmed in the div_cpu1 register. + * + * This structure holds the divider configuration data for divider clocks + * belonging to the CMU_CPU clock domain. The parent frequency@which these + * divider values are valid is specified in @prate. + */ +struct exynos4210_armclk_data { + unsigned long prate; + unsigned int div0; + unsigned int div1; +}; + +/** + * struct exynos_cpuclk: information about clock supplied to a CPU core. + * @hw: handle between CCF and CPU clock. + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock. + * @ctrl_base: base address of the clock controller. + * @offset: offset from the ctrl_base address where the CPU clock div/mux + * registers can be accessed. + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock. + * @lock: register access lock. + * @data: optional data which the actual instantiation of this clock + * can use. + */ +struct exynos_cpuclk { + struct clk_hw hw; + struct clk *alt_parent; + void __iomem *ctrl_base; + unsigned long offset; + struct notifier_block clk_nb; + spinlock_t *lock; + void *data; +}; + +#define to_exynos_cpuclk_hw(hw) container_of(hw, struct exynos_cpuclk, hw) +#define to_exynos_cpuclk_nb(nb) container_of(nb, struct exynos_cpuclk, clk_nb) + +/** + * struct exynos_cpuclk_soc_data: soc specific data for cpu clocks. + * @parser: pointer to a function that can parse SoC specific data. + * @ops: clock operations to be used for this clock. + * @offset: optional offset from base of clock controller register base, to + * be used when accessing clock controller registers related to the + * CPU clock. + * @clk_cb: the clock notifier callback to be called for changes in the + * clock rate of the primary parent clock. + * + * This structure provides SoC specific data for ARM clocks. Based on + * the compatible value of the clock controller node, the value of the + * fields in this structure can be populated. + */ +struct exynos_cpuclk_soc_data { + int (*parser)(struct device_node *, void **); + const struct clk_ops *ops; + unsigned int offset; + int (*clk_cb)(struct notifier_block *, unsigned long, void *); +}; + +/* common round rate callback useable for all types of CPU clocks */ +static long exynos_cpuclk_round_rate(struct clk_hw *hw, + unsigned long drate, unsigned long *prate) +{ + struct clk *parent = __clk_get_parent(hw->clk); + *prate = __clk_round_rate(parent, drate); + return *prate; +} + +/* common recalc rate callback useable for all types of CPU clocks */ +static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate; +} + +/* + * Calculates the divider value to be set for deriving drate from prate. + * Divider value is actual divider value - 1. + */ +static unsigned long _calc_div(unsigned long prate, unsigned long drate) +{ + unsigned long div = DIV_ROUND_UP(prate, drate) - 1; + + WARN_ON(div >= MAX_DIV); + return div; +} + +/* helper function to register a cpu clock */ +static int __init exynos_cpuclk_register(struct samsung_clk_provider *ctx, + unsigned int lookup_id, const char *name, const char *parent, + const char *alt_parent, struct device_node *np, + const struct exynos_cpuclk_soc_data *soc_data) +{ + struct exynos_cpuclk *cpuclk; + struct clk_init_data init; + struct clk *clk; + int ret; + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (!cpuclk) { + pr_err("%s: could not allocate memory for %s clock\n", + __func__, name); + return -ENOMEM; + } + + init.name = name; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = &parent; + init.num_parents = 1; + + cpuclk->hw.init = &init; + cpuclk->ctrl_base = ctx->reg_base; + cpuclk->lock = &ctx->lock; + + ret = soc_data->parser(np, &cpuclk->data); + if (ret) { + pr_err("%s: error %d in parsing %s clock data", + __func__, ret, name); + ret = -EINVAL; + goto free_cpuclk; + } + cpuclk->offset = soc_data->offset; + init.ops = soc_data->ops; + + cpuclk->clk_nb.notifier_call = soc_data->clk_cb; + if (clk_notifier_register(__clk_lookup(parent), &cpuclk->clk_nb)) { + pr_err("%s: failed to register clock notifier for %s\n", + __func__, name); + goto free_cpuclk_data; + } + + cpuclk->alt_parent = __clk_lookup(alt_parent); + if (!cpuclk->alt_parent) { + pr_err("%s: could not lookup alternate parent %s\n", + __func__, alt_parent); + ret = -EINVAL; + goto unregister_clk_nb; + } + + clk = clk_register(NULL, &cpuclk->hw); + if (IS_ERR(clk)) { + pr_err("%s: could not register cpuclk %s\n", __func__, name); + ret = PTR_ERR(clk); + goto unregister_clk_nb; + } + + samsung_clk_add_lookup(ctx, clk, lookup_id); + return 0; + +unregister_clk_nb: + clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb); +free_cpuclk_data: + kfree(cpuclk->data); +free_cpuclk: + kfree(cpuclk); + return ret; +} + +static void exynos4210_set_armclk_div(void __iomem *base, unsigned long div) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(10); + unsigned long div0; + + WARN_ON(div >= MAX_DIV); + + div0 = readl(base + DIV_CPU0); + div0 = (div0 & ~DIV_CPU0_RATIO0_MASK) | div; + writel(div0, base + DIV_CPU0); + while (time_before(jiffies, timeout)) + if (!readl(base + DIV_STAT_CPU0)) + return; + pr_err("%s: timeout in divider stablization\n", __func__); +} + +static int exynos4210_armclk_pre_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *armclk, void __iomem *base) +{ + struct exynos4210_armclk_data *armclk_data = armclk->data; + unsigned long alt_prate = clk_get_rate(armclk->alt_parent); + unsigned long alt_div = 0, div0, div1, tdiv0, mux_reg; + unsigned long timeout, flags; + + /* find out the divider values to use for clock data */ + while (armclk_data->prate != ndata->new_rate) { + if (armclk_data->prate == 0) + return -EINVAL; + armclk_data++; + } + + /* For the selected PLL clock frequency, get the pre-defined divider + * values. If the clock for sclk_hpm is not sourced from apll, then + * the values for DIV_COPY and DIV_HPM dividers need not be set. + */ + div0 = armclk_data->div0; + div1 = armclk_data->div1; + if (readl(base + SRC_CPU) & EXYNOS4210_MUX_HPM_MASK) { + div1 = readl(base + DIV_CPU1) & EXYNOS4210_DIV1_HPM_MASK; + div1 |= ((armclk_data->div1) & ~EXYNOS4210_DIV1_HPM_MASK); + } + + spin_lock_irqsave(armclk->lock, flags); + + /* + * if the new and old parent clock speed is less than the clock speed + * of the alternate parent, then it should be ensured that at no point + * the armclk speed is more than the old_prate until the dividers are + * set. + */ + tdiv0 = readl(base + DIV_CPU0); + if (alt_prate > ndata->old_rate) { + alt_div = _calc_div(alt_prate, ndata->old_rate); + exynos4210_set_armclk_div(base, alt_div); + div0 |= alt_div; + } + + /* select sclk_mpll as the alternate parent */ + mux_reg = readl(base + SRC_CPU); + writel(mux_reg | (1 << 16), base + SRC_CPU); + + timeout = jiffies + msecs_to_jiffies(10); + while (time_before(jiffies, timeout)) + if (((readl(base + STAT_CPU) >> 16) & 0x7) == 2) + break; + + if (((readl(base + STAT_CPU) >> 16) & 0x7) != 2) + pr_err("%s: re-parenting to sclk_mpll failed\n", __func__); + + /* alternate parent is active now. set the dividers */ + writel(div0, base + DIV_CPU0); + timeout = jiffies + msecs_to_jiffies(10); + while (time_before(jiffies, timeout)) + if (!readl(base + DIV_STAT_CPU0)) + break; + + if (readl(base + DIV_STAT_CPU0)) + pr_err("%s: timeout in divider0 stablization\n", __func__); + + writel(div1, base + DIV_CPU1); + timeout = jiffies + msecs_to_jiffies(10); + while (time_before(jiffies, timeout)) + if (!readl(base + DIV_STAT_CPU1)) + break; + if (readl(base + DIV_STAT_CPU1)) + pr_err("%s: timeout in divider1 stablization\n", __func__); + + spin_unlock_irqrestore(armclk->lock, flags); + return 0; +} + +static int exynos4210_armclk_post_rate_change(struct exynos_cpuclk *armclk, + void __iomem *base) +{ + unsigned long mux_reg, flags; + unsigned long timeout = jiffies + msecs_to_jiffies(10); + + spin_lock_irqsave(armclk->lock, flags); + + mux_reg = readl(base + SRC_CPU); + writel(mux_reg & ~(1 << 16), base + SRC_CPU); + while (time_before(jiffies, timeout)) + if (((readl(base + STAT_CPU) >> 16) & 0x7) == 1) + break; + if (((readl(base + STAT_CPU) >> 16) & 0x7) != 1) + pr_err("%s: re-parenting to mout_apll failed\n", __func__); + + spin_unlock_irqrestore(armclk->lock, flags); + return 0; +} + +/* + * This clock notifier is called when the frequency of the parent clock + * of armclk is to be changed. This notifier handles the setting up all + * the divider clocks, remux to temporary parent and handling the safe + * frequency levels when using temporary parent. + */ +static int exynos4210_armclk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct exynos_cpuclk *armclk = to_exynos_cpuclk_nb(nb); + void __iomem *base = armclk->ctrl_base + armclk->offset; + int err = 0; + + if (event == PRE_RATE_CHANGE) + err = exynos4210_armclk_pre_rate_change(ndata, armclk, base); + else if (event == POST_RATE_CHANGE) + err = exynos4210_armclk_post_rate_change(armclk, base); + + return notifier_from_errno(err); +} + +static int exynos4210_armclk_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct exynos_cpuclk *armclk = to_exynos_cpuclk_hw(hw); + void __iomem *base = armclk->ctrl_base + armclk->offset; + unsigned long flags; + + spin_lock_irqsave(armclk->lock, flags); + exynos4210_set_armclk_div(base, 0); + spin_unlock_irqrestore(armclk->lock, flags); + return 0; +} + +static const struct clk_ops exynos4210_armclk_clk_ops = { + .recalc_rate = exynos_cpuclk_recalc_rate, + .round_rate = exynos_cpuclk_round_rate, + .set_rate = exynos4210_armclk_set_rate, +}; + +/* + * parse divider configuration data from dt for all the cpu clock domain + * clocks in exynos4210 and compatible SoC's. + */ +static int __init exynos4210_armclk_parser(struct device_node *np, void **data) +{ + struct exynos4210_armclk_data *tdata; + u32 cfg[10], num_rows, row, col; + struct property *prop; + const __be32 *ptr = NULL; + u32 cells; + int len; + + if (of_property_read_u32(np, "samsung,armclk-cells", &cells)) + return -EINVAL; + prop = of_find_property(np, "samsung,armclk-divider-table", &len); + if (!prop) + return -EINVAL; + if ((len / sizeof(u32)) % cells) + return -EINVAL; + num_rows = (len / sizeof(u32)) / cells; + + /* allocate a zero terminated table */ + *data = kzalloc(sizeof(*tdata) * (num_rows + 1), GFP_KERNEL); + if (!*data) + return -ENOMEM; + tdata = *data; + + for (row = 0; row < num_rows; row++, tdata++) { + for (col = 0; col < cells; col++) + ptr = of_prop_next_u32(prop, ptr, &cfg[col]); + + tdata->prate = cfg[0] * 1000; + tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5], cfg[4], + cfg[3], cfg[2], cfg[1]); + tdata->div1 = cells == 10 ? + EXYNOS4210_DIV_CPU1(cfg[9], cfg[8], cfg[7]) : + EXYNOS4210_DIV_CPU1(0, cfg[8], cfg[7]); + } + tdata->prate = 0; + return 0; +} + +static const struct exynos_cpuclk_soc_data exynos4210_cpuclk_soc_data = { + .parser = exynos4210_armclk_parser, + .ops = &exynos4210_armclk_clk_ops, + .offset = 0x14200, + .clk_cb = exynos4210_armclk_notifier_cb, +}; + +static const struct exynos_cpuclk_soc_data exynos5250_cpuclk_soc_data = { + .parser = exynos4210_armclk_parser, + .ops = &exynos4210_armclk_clk_ops, + .offset = 0x200, + .clk_cb = exynos4210_armclk_notifier_cb, +}; + +static const struct of_device_id exynos_clock_ids_armclk[] = { + { .compatible = "samsung,exynos4210-clock", + .data = &exynos4210_cpuclk_soc_data, }, + { .compatible = "samsung,exynos4412-clock", + .data = &exynos4210_cpuclk_soc_data, }, + { .compatible = "samsung,exynos5250-clock", + .data = &exynos5250_cpuclk_soc_data, }, + { }, +}; + +/** + * exynos_register_arm_clock: register arm clock with ccf. + * @lookup_id: armclk clock output id for the clock controller. + * @parent_names: name of the parent clock for armclk. + * @num_parents: number of parents in the @parent_names array. + * @base: base address of the clock controller from which armclk is generated. + * @np: device tree node pointer of the clock controller (optional). + * @ops: clock ops for this clock (optional). + * @lock: register access lock. + */ +int __init exynos_register_arm_clock(struct samsung_clk_provider *ctx, + unsigned int lookup_id, const char *parent, + const char *alt_parent, struct device_node *np) +{ + const struct of_device_id *match; + const struct exynos_cpuclk_soc_data *data = NULL; + + if (!np) + return -EINVAL; + + match = of_match_node(exynos_clock_ids_armclk, np); + if (!match) + return -EINVAL; + + data = match->data; + return exynos_cpuclk_register(ctx, lookup_id, "armclk", parent, + alt_parent, np, data); +} diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 9693b80..43da899 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -372,4 +372,8 @@ extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( const unsigned long *rdump, unsigned long nr_rdump); +extern int __init exynos_register_arm_clock(struct samsung_clk_provider *ctx, + unsigned int lookup_id, const char *parent, + const char *alt_parent, struct device_node *np); + #endif /* __SAMSUNG_CLK_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 2/7] clk: samsung: add infrastructure to register cpu clocks Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 4/7] clk: exynos: use cpu-clock provider type to represent arm clock Thomas Abraham ` (4 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa <t.figa@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property should be 9. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +44,24 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 4/7] clk: exynos: use cpu-clock provider type to represent arm clock 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham ` (2 preceding siblings ...) 2014-05-23 14:27 ` [PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 5/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data Thomas Abraham ` (3 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type and the independent clock blocks that made up the arm clock can be removed. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 25 +++++++++++++++++-------- drivers/clk/samsung/clk-exynos5250.c | 16 +++++++++++----- include/dt-bindings/clock/exynos5250.h | 1 + 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index c4df294..fd235e4 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -471,7 +471,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), @@ -530,7 +531,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), @@ -572,8 +574,10 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { /* list of divider clocks supported in all exynos4 soc's */ static struct samsung_div_clock exynos4_div_clks[] __initdata = { - DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), - DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), + DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_core2", "div_core", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), @@ -619,8 +623,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3), - DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), + DIV_F(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, @@ -1005,7 +1011,6 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { static struct samsung_clock_alias exynos4_aliases[] __initdata = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), - ALIAS(CLK_ARM_CLK, NULL, "armclk"), ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), }; @@ -1244,6 +1249,8 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_gate_clks)); samsung_clk_register_alias(ctx, exynos4210_aliases, ARRAY_SIZE(exynos4210_aliases)); + exynos_register_arm_clock(ctx, CLK_ARM_CLK, mout_core_p4210[0], + mout_core_p4210[1], np); } else { samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); @@ -1253,6 +1260,8 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4x12_gate_clks)); samsung_clk_register_alias(ctx, exynos4x12_aliases, ARRAY_SIZE(exynos4x12_aliases)); + exynos_register_arm_clock(ctx, CLK_ARM_CLK, mout_core_p4x12[0], + mout_core_p4x12[1], np); } samsung_clk_register_alias(ctx, exynos4_aliases, @@ -1265,7 +1274,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", _get_rate("sclk_apll"), _get_rate("sclk_mpll"), _get_rate("sclk_epll"), _get_rate("sclk_vpll"), - _get_rate("arm_clk")); + _get_rate("armclk")); } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 1fad4c5..6e91b97 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -292,7 +292,8 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { */ MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0, "mout_apll"), - MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_FA(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, + 0, CLK_MUX_READ_ONLY, "mout_cpu"), /* * CMU_CORE @@ -379,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { /* * CMU_CPU */ - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), /* * CMU_TOP @@ -797,6 +801,8 @@ static void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks)); samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + exynos_register_arm_clock(ctx, CLK_ARM_CLK, mout_cpu_p[0], + mout_cpu_p[1], np); /* * Enable arm clock down (in idle) and set arm divider @@ -821,6 +827,6 @@ static void __init exynos5250_clk_init(struct device_node *np) exynos5250_clk_sleep_init(); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", - _get_rate("div_arm2")); + _get_rate("armclk")); } CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index be6e97c..d3565be 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -21,6 +21,7 @@ #define CLK_FOUT_CPLL 6 #define CLK_FOUT_EPLL 7 #define CLK_FOUT_VPLL 8 +#define CLK_ARM_CLK 12 /* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128 -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 5/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham ` (3 preceding siblings ...) 2014-05-23 14:27 ` [PATCH v5 4/7] clk: exynos: use cpu-clock provider type to represent arm clock Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver Thomas Abraham ` (2 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> For all Exynos based platforms, add CPU nodes, operating points and cpu clock data for migrating from Exynos specific cpufreq driver to using generic cpufreq-cpu0 driver. Cc: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- arch/arm/boot/dts/exynos4210-origen.dts | 6 ++++ arch/arm/boot/dts/exynos4210-trats.dts | 6 ++++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 ++++ arch/arm/boot/dts/exynos4210.dtsi | 35 +++++++++++++++++++ arch/arm/boot/dts/exynos4212.dtsi | 18 ++++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++++ arch/arm/boot/dts/exynos4412-origen.dts | 6 ++++ arch/arm/boot/dts/exynos4412-trats2.dts | 6 ++++ arch/arm/boot/dts/exynos4412.dtsi | 31 +++++++++++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 36 ++++++++++++++++++++ arch/arm/boot/dts/exynos5250-arndale.dts | 6 ++++ arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 ++++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 ++++ arch/arm/boot/dts/exynos5250.dtsi | 41 +++++++++++++++++++++++ 14 files changed, 215 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 72fb11f..4324b25 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,6 +32,12 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck1_reg>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index f516da9..fe32b6a 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,6 +30,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu: cpu at 0 { + cpu0-supply = <&varm_breg>; + }; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d50eb3a..8ab12d6 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + cpus { + cpu: cpu at 0 { + cpu0-supply = <&vdd_arm_reg>; + }; + }; + sysram at 02020000 { smp-sysram at 0 { status = "disabled"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index ee3001f..e42b87c 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,33 @@ pinctrl2 = &pinctrl_2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + sysram at 02020000 { compatible = "mmio-sram"; reg = <0x02020000 0x20000>; @@ -91,6 +118,14 @@ compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; pmu { diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 3c00e6e..87847d5 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,24 @@ / { compatible = "samsung,exynos4212", "samsung,exynos4"; + clock: clock-controller at 10030000 { + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1500000 3 7 0 6 1 2 6 0>, + <1400000 3 7 0 6 1 2 6 0>, + <1300000 3 7 0 5 1 2 5 0>, + <1200000 3 7 0 5 1 2 5 0>, + <1100000 3 6 0 4 1 2 4 0>, + <1000000 2 5 0 4 1 1 4 0>, + < 900000 2 5 0 3 1 1 3 0>, + < 800000 2 5 0 3 1 1 3 0>, + < 700000 2 4 0 3 1 1 3 0>, + < 600000 2 4 0 3 1 1 3 0>, + < 500000 2 4 0 3 1 1 3 0>, + < 400000 2 4 0 3 1 1 3 0>, + < 300000 2 4 0 2 1 1 3 0>, + < 200000 1 3 0 1 1 1 3 0>; + }; + combiner: interrupt-controller at 10440000 { samsung,combiner-nr = <18>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 31db28a..4671714 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,6 +22,12 @@ reg = <0x40000000 0x40000000>; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + leds { compatible = "gpio-leds"; led1 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e2c0dca..442bf90 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -27,6 +27,12 @@ bootargs ="console=ttySAC2,115200"; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware at 0203F000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 7787844..3d9258d 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -32,6 +32,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware at 0204F000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index c42a3e1..c14b4f5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,37 @@ / { compatible = "samsung,exynos4412", "samsung,exynos4"; + cpus { + cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + clock: clock-controller at 10030000 { + samsung,armclk-cells = <10>; + samsung,armclk-divider-table = <1500000 3 7 0 6 1 2 6 0 7>, + <1400000 3 7 0 6 1 2 6 0 6>, + <1300000 3 7 0 5 1 2 5 0 6>, + <1200000 3 7 0 5 1 2 5 0 5>, + <1100000 3 6 0 4 1 2 4 0 5>, + <1000000 2 5 0 4 1 1 4 0 4>, + < 900000 2 5 0 3 1 1 3 0 4>, + < 800000 2 5 0 3 1 1 3 0 3>, + < 700000 2 4 0 3 1 1 3 0 3>, + < 600000 2 4 0 3 1 1 3 0 2>, + < 500000 2 4 0 3 1 1 3 0 2>, + < 400000 2 4 0 3 1 1 3 0 1>, + < 300000 2 4 0 2 1 1 3 0 1>, + < 200000 1 3 0 1 1 1 3 0 0>; + }; + combiner: interrupt-controller at 10440000 { samsung,combiner-nr = <20>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c5a943d..6b43f71 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -31,6 +31,42 @@ mshc0 = &mshc_0; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + + operating-points = < + 1500000 1350000 + 1400000 1287500 + 1300000 1250000 + 1200000 1187500 + 1100000 1137500 + 1000000 1087500 + 900000 1037500 + 800000 1000000 + 700000 987500 + 600000 975000 + 500000 950000 + 400000 925000 + 300000 900000 + 200000 900000 + >; + clock-latency = <200000>; + boost-frequencies = <1500000>; + }; + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&combiner>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index cde19c8..6367538 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -25,6 +25,12 @@ bootargs = "console=ttySAC2,115200"; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + rtc at 101E0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 89ac90f..34bb31c 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -19,6 +19,12 @@ chosen { }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + pinctrl at 11400000 { /* * Disabled pullups since external part has its own pullups and diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index a794a70..3632f7a 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -27,6 +27,12 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu at 0 { + cpu0-supply = <&buck2_reg>; + }; + }; + rtc at 101E0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 834fb5a..5d4c650 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -63,6 +63,29 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + clock-latency = <200000>; }; cpu at 1 { device_type = "cpu"; @@ -104,6 +127,24 @@ compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; clock_audss: audss-clock-controller at 3810000 { -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham ` (4 preceding siblings ...) 2014-05-23 14:27 ` [PATCH v5 5/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-26 6:17 ` Viresh Kumar 2014-05-23 14:27 ` [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support Thomas Abraham 2014-05-25 22:50 ` [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Kukjin Kim 7 siblings, 1 reply; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> Remove the platform device instantiation for Exynos specific cpufreq driver and add the platform device for cpufreq-cpu0 driver. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- arch/arm/mach-exynos/exynos.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 93507ee..2193061 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -184,7 +184,9 @@ void __init exynos_cpuidle_init(void) void __init exynos_cpufreq_init(void) { - platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); + if (!(of_machine_is_compatible("samsung,exynos5420")) && + !(of_machine_is_compatible("samsung,exynos5440"))) + platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); } void __init exynos_init_late(void) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver 2014-05-23 14:27 ` [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver Thomas Abraham @ 2014-05-26 6:17 ` Viresh Kumar 0 siblings, 0 replies; 14+ messages in thread From: Viresh Kumar @ 2014-05-26 6:17 UTC (permalink / raw) To: linux-arm-kernel On 23 May 2014 19:57, Thomas Abraham <thomas.ab@samsung.com> wrote: > From: Thomas Abraham <thomas.ab@samsung.com> > > Remove the platform device instantiation for Exynos specific cpufreq > driver and add the platform device for cpufreq-cpu0 driver. > > Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> > --- > arch/arm/mach-exynos/exynos.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Acked-by: Viresh Kumar <viresh.kumar@linaro.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham ` (5 preceding siblings ...) 2014-05-23 14:27 ` [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver Thomas Abraham @ 2014-05-23 14:27 ` Thomas Abraham 2014-05-26 6:18 ` Viresh Kumar 2014-05-25 22:50 ` [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Kukjin Kim 7 siblings, 1 reply; 14+ messages in thread From: Thomas Abraham @ 2014-05-23 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Thomas Abraham <thomas.ab@samsung.com> Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> --- drivers/cpufreq/Kconfig.arm | 52 -------- drivers/cpufreq/Makefile | 4 - drivers/cpufreq/exynos-cpufreq.c | 218 ---------------------------------- drivers/cpufreq/exynos-cpufreq.h | 99 --------------- drivers/cpufreq/exynos4210-cpufreq.c | 157 ------------------------ drivers/cpufreq/exynos4x12-cpufreq.c | 208 -------------------------------- drivers/cpufreq/exynos5250-cpufreq.c | 183 ---------------------------- 7 files changed, 921 deletions(-) delete mode 100644 drivers/cpufreq/exynos-cpufreq.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 5805035..9721674 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -24,43 +24,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ This add the CPUfreq driver support for Versatile Express big.LITTLE platforms using SPC for power management. - -config ARM_EXYNOS_CPUFREQ - bool - -config ARM_EXYNOS4210_CPUFREQ - bool "SAMSUNG EXYNOS4210" - depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4210 - SoC (S5PV310 or S5PC210). - - If in doubt, say N. - -config ARM_EXYNOS4X12_CPUFREQ - bool "SAMSUNG EXYNOS4x12" - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4X12 - SoC (EXYNOS4212 or EXYNOS4412). - - If in doubt, say N. - -config ARM_EXYNOS5250_CPUFREQ - bool "SAMSUNG EXYNOS5250" - depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS5250 - SoC. - - If in doubt, say N. - config ARM_EXYNOS5440_CPUFREQ bool "SAMSUNG EXYNOS5440" depends on SOC_EXYNOS5440 @@ -75,21 +38,6 @@ config ARM_EXYNOS5440_CPUFREQ If in doubt, say N. -config ARM_EXYNOS_CPU_FREQ_BOOST_SW - bool "EXYNOS Frequency Overclocking - Software" - depends on ARM_EXYNOS_CPUFREQ - select CPU_FREQ_BOOST_SW - select EXYNOS_THERMAL - help - This driver supports software managed overclocking (BOOST). - It allows usage of special frequencies for Samsung Exynos - processors if thermal conditions are appropriate. - - It reguires, for safe operation, thermal framework with properly - defined trip points. - - If in doubt, say N. - config ARM_HIGHBANK_CPUFREQ tristate "Calxeda Highbank-based" depends on ARCH_HIGHBANK && GENERIC_CPUFREQ_CPU0 && REGULATOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 738c8b7..8a75419 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -51,10 +51,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c deleted file mode 100644 index e8a4a7e..0000000 --- a/drivers/cpufreq/exynos-cpufreq.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - CPU frequency scaling support for EXYNOS series - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/regulator/consumer.h> -#include <linux/cpufreq.h> -#include <linux/platform_device.h> -#include <linux/of.h> - -#include <plat/cpu.h> - -#include "exynos-cpufreq.h" - -static struct exynos_dvfs_info *exynos_info; -static struct regulator *arm_regulator; -static unsigned int locking_frequency; - -static int exynos_cpufreq_get_index(unsigned int freq) -{ - struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; - int index; - - for (index = 0; - freq_table[index].frequency != CPUFREQ_TABLE_END; index++) - if (freq_table[index].frequency == freq) - break; - - if (freq_table[index].frequency == CPUFREQ_TABLE_END) - return -EINVAL; - - return index; -} - -static int exynos_cpufreq_scale(unsigned int target_freq) -{ - struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; - unsigned int *volt_table = exynos_info->volt_table; - struct cpufreq_policy *policy = cpufreq_cpu_get(0); - unsigned int arm_volt, safe_arm_volt = 0; - unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; - unsigned int old_freq; - int index, old_index; - int ret = 0; - - old_freq = policy->cur; - - /* - * The policy max have been changed so that we cannot get proper - * old_index with cpufreq_frequency_table_target(). Thus, ignore - * policy and get the index from the raw frequency table. - */ - old_index = exynos_cpufreq_get_index(old_freq); - if (old_index < 0) { - ret = old_index; - goto out; - } - - index = exynos_cpufreq_get_index(target_freq); - if (index < 0) { - ret = index; - goto out; - } - - /* - * ARM clock source will be changed APLL to MPLL temporary - * To support this level, need to control regulator for - * required voltage level - */ - if (exynos_info->need_apll_change != NULL) { - if (exynos_info->need_apll_change(old_index, index) && - (freq_table[index].frequency < mpll_freq_khz) && - (freq_table[old_index].frequency < mpll_freq_khz)) - safe_arm_volt = volt_table[exynos_info->pll_safe_idx]; - } - arm_volt = volt_table[index]; - - /* When the new frequency is higher than current frequency */ - if ((target_freq > old_freq) && !safe_arm_volt) { - /* Firstly, voltage up to increase frequency */ - ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt); - if (ret) { - pr_err("%s: failed to set cpu voltage to %d\n", - __func__, arm_volt); - return ret; - } - } - - if (safe_arm_volt) { - ret = regulator_set_voltage(arm_regulator, safe_arm_volt, - safe_arm_volt); - if (ret) { - pr_err("%s: failed to set cpu voltage to %d\n", - __func__, safe_arm_volt); - return ret; - } - } - - exynos_info->set_freq(old_index, index); - - /* When the new frequency is lower than current frequency */ - if ((target_freq < old_freq) || - ((target_freq > old_freq) && safe_arm_volt)) { - /* down the voltage after frequency change */ - ret = regulator_set_voltage(arm_regulator, arm_volt, - arm_volt); - if (ret) { - pr_err("%s: failed to set cpu voltage to %d\n", - __func__, arm_volt); - goto out; - } - } - -out: - cpufreq_cpu_put(policy); - - return ret; -} - -static int exynos_target(struct cpufreq_policy *policy, unsigned int index) -{ - return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency); -} - -static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) -{ - policy->clk = exynos_info->cpu_clk; - policy->suspend_freq = locking_frequency; - return cpufreq_generic_init(policy, exynos_info->freq_table, 100000); -} - -static struct cpufreq_driver exynos_driver = { - .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, - .verify = cpufreq_generic_frequency_table_verify, - .target_index = exynos_target, - .get = cpufreq_generic_get, - .init = exynos_cpufreq_cpu_init, - .name = "exynos_cpufreq", - .attr = cpufreq_generic_attr, -#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW - .boost_supported = true, -#endif -#ifdef CONFIG_PM - .suspend = cpufreq_generic_suspend, -#endif -}; - -static int exynos_cpufreq_probe(struct platform_device *pdev) -{ - int ret = -EINVAL; - - exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL); - if (!exynos_info) - return -ENOMEM; - - if (of_machine_is_compatible("samsung,exynos4210")) { - exynos_info->type = EXYNOS_SOC_4210; - ret = exynos4210_cpufreq_init(exynos_info); - } else if (of_machine_is_compatible("samsung,exynos4212")) { - exynos_info->type = EXYNOS_SOC_4212; - ret = exynos4x12_cpufreq_init(exynos_info); - } else if (of_machine_is_compatible("samsung,exynos4412")) { - exynos_info->type = EXYNOS_SOC_4412; - ret = exynos4x12_cpufreq_init(exynos_info); - } else if (of_machine_is_compatible("samsung,exynos5250")) { - exynos_info->type = EXYNOS_SOC_5250; - ret = exynos5250_cpufreq_init(exynos_info); - } else { - pr_err("%s: Unknown SoC type\n", __func__); - return -ENODEV; - } - - if (ret) - goto err_vdd_arm; - - if (exynos_info->set_freq == NULL) { - pr_err("%s: No set_freq function (ERR)\n", __func__); - goto err_vdd_arm; - } - - arm_regulator = regulator_get(NULL, "vdd_arm"); - if (IS_ERR(arm_regulator)) { - pr_err("%s: failed to get resource vdd_arm\n", __func__); - goto err_vdd_arm; - } - - /* Done here as we want to capture boot frequency */ - locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000; - - if (!cpufreq_register_driver(&exynos_driver)) - return 0; - - pr_err("%s: failed to register cpufreq driver\n", __func__); - regulator_put(arm_regulator); -err_vdd_arm: - kfree(exynos_info); - return -EINVAL; -} - -static struct platform_driver exynos_cpufreq_platdrv = { - .driver = { - .name = "exynos-cpufreq", - .owner = THIS_MODULE, - }, - .probe = exynos_cpufreq_probe, -}; -module_platform_driver(exynos_cpufreq_platdrv); diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h deleted file mode 100644 index f189547..0000000 --- a/drivers/cpufreq/exynos-cpufreq.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - CPUFreq support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -enum cpufreq_level_index { - L0, L1, L2, L3, L4, - L5, L6, L7, L8, L9, - L10, L11, L12, L13, L14, - L15, L16, L17, L18, L19, - L20, -}; - -enum exynos_soc_type { - EXYNOS_SOC_4210, - EXYNOS_SOC_4212, - EXYNOS_SOC_4412, - EXYNOS_SOC_5250, -}; - -#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \ - { \ - .freq = (f) * 1000, \ - .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \ - (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \ - .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \ - .mps = ((m) << 16 | (p) << 8 | (s)), \ - } - -struct apll_freq { - unsigned int freq; - u32 clk_div_cpu0; - u32 clk_div_cpu1; - u32 mps; -}; - -struct exynos_dvfs_info { - enum exynos_soc_type type; - unsigned long mpll_freq_khz; - unsigned int pll_safe_idx; - struct clk *cpu_clk; - unsigned int *volt_table; - struct cpufreq_frequency_table *freq_table; - void (*set_freq)(unsigned int, unsigned int); - bool (*need_apll_change)(unsigned int, unsigned int); -}; - -#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ -extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *); -#else -static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) -{ - return -EOPNOTSUPP; -} -#endif -#ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ -extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *); -#else -static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) -{ - return -EOPNOTSUPP; -} -#endif -#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ -extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *); -#else -static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) -{ - return -EOPNOTSUPP; -} -#endif - -#include <plat/cpu.h> -#include <mach/map.h> - -#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200) -#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400) - -#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500) -#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504) -#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604) - -#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) - -#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000) -#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) -#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400) -#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500) -#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604) diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c deleted file mode 100644 index 6384e5b..0000000 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4210 - CPU frequency scaling support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/cpufreq.h> - -#include "exynos-cpufreq.h" - -static struct clk *cpu_clk; -static struct clk *moutcore; -static struct clk *mout_mpll; -static struct clk *mout_apll; - -static unsigned int exynos4210_volt_table[] = { - 1250000, 1150000, 1050000, 975000, 950000, -}; - -static struct cpufreq_frequency_table exynos4210_freq_table[] = { - {0, L0, 1200 * 1000}, - {0, L1, 1000 * 1000}, - {0, L2, 800 * 1000}, - {0, L3, 500 * 1000}, - {0, L4, 200 * 1000}, - {0, 0, CPUFREQ_TABLE_END}, -}; - -static struct apll_freq apll_freq_4210[] = { - /* - * values: - * freq - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED - * clock divider for COPY, HPM, RESERVED - * PLL M, P, S - */ - APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1), - APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1), - APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1), - APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2), - APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3), -}; - -static void exynos4210_set_clkdiv(unsigned int div_index) -{ - unsigned int tmp; - - /* Change Divider - CPU0 */ - - tmp = apll_freq_4210[div_index].clk_div_cpu0; - - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU); - } while (tmp & 0x1111111); - - /* Change Divider - CPU1 */ - - tmp = apll_freq_4210[div_index].clk_div_cpu1; - - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); - } while (tmp & 0x11); -} - -static void exynos4210_set_apll(unsigned int index) -{ - unsigned int tmp, freq = apll_freq_4210[index].freq; - - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ - clk_set_parent(moutcore, mout_mpll); - - do { - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); - tmp &= 0x7; - } while (tmp != 0x2); - - clk_set_rate(mout_apll, freq * 1000); - - /* MUX_CORE_SEL = APLL */ - clk_set_parent(moutcore, mout_apll); - - do { - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); -} - -static void exynos4210_set_frequency(unsigned int old_index, - unsigned int new_index) -{ - if (old_index > new_index) { - exynos4210_set_clkdiv(new_index); - exynos4210_set_apll(new_index); - } else if (old_index < new_index) { - exynos4210_set_apll(new_index); - exynos4210_set_clkdiv(new_index); - } -} - -int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) -{ - unsigned long rate; - - cpu_clk = clk_get(NULL, "armclk"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - moutcore = clk_get(NULL, "moutcore"); - if (IS_ERR(moutcore)) - goto err_moutcore; - - mout_mpll = clk_get(NULL, "mout_mpll"); - if (IS_ERR(mout_mpll)) - goto err_mout_mpll; - - rate = clk_get_rate(mout_mpll) / 1000; - - mout_apll = clk_get(NULL, "mout_apll"); - if (IS_ERR(mout_apll)) - goto err_mout_apll; - - info->mpll_freq_khz = rate; - /* 800Mhz */ - info->pll_safe_idx = L2; - info->cpu_clk = cpu_clk; - info->volt_table = exynos4210_volt_table; - info->freq_table = exynos4210_freq_table; - info->set_freq = exynos4210_set_frequency; - - return 0; - -err_mout_apll: - clk_put(mout_mpll); -err_mout_mpll: - clk_put(moutcore); -err_moutcore: - clk_put(cpu_clk); - - pr_debug("%s: failed initialization\n", __func__); - return -EINVAL; -} diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c deleted file mode 100644 index 63a3907..0000000 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4X12 - CPU frequency scaling support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/cpufreq.h> - -#include "exynos-cpufreq.h" - -static struct clk *cpu_clk; -static struct clk *moutcore; -static struct clk *mout_mpll; -static struct clk *mout_apll; - -static unsigned int exynos4x12_volt_table[] = { - 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500, - 1000000, 987500, 975000, 950000, 925000, 900000, 900000 -}; - -static struct cpufreq_frequency_table exynos4x12_freq_table[] = { - {CPUFREQ_BOOST_FREQ, L0, 1500 * 1000}, - {0, L1, 1400 * 1000}, - {0, L2, 1300 * 1000}, - {0, L3, 1200 * 1000}, - {0, L4, 1100 * 1000}, - {0, L5, 1000 * 1000}, - {0, L6, 900 * 1000}, - {0, L7, 800 * 1000}, - {0, L8, 700 * 1000}, - {0, L9, 600 * 1000}, - {0, L10, 500 * 1000}, - {0, L11, 400 * 1000}, - {0, L12, 300 * 1000}, - {0, L13, 200 * 1000}, - {0, 0, CPUFREQ_TABLE_END}, -}; - -static struct apll_freq *apll_freq_4x12; - -static struct apll_freq apll_freq_4212[] = { - /* - * values: - * freq - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2 - * clock divider for COPY, HPM, RESERVED - * PLL M, P, S - */ - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0), - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0), - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0), - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0), - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0), - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0), - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0), - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0), - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1), - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1), - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1), - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1), - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2), - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2), -}; - -static struct apll_freq apll_freq_4412[] = { - /* - * values: - * freq - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2 - * clock divider for COPY, HPM, CORES - * PLL M, P, S - */ - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0), - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0), - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0), - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0), - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0), - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0), - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0), - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0), - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1), - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1), - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1), - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1), - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2), - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2), -}; - -static void exynos4x12_set_clkdiv(unsigned int div_index) -{ - unsigned int tmp; - - /* Change Divider - CPU0 */ - - tmp = apll_freq_4x12[div_index].clk_div_cpu0; - - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); - - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111) - cpu_relax(); - - /* Change Divider - CPU1 */ - tmp = apll_freq_4x12[div_index].clk_div_cpu1; - - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); - - do { - cpu_relax(); - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); - } while (tmp != 0x0); -} - -static void exynos4x12_set_apll(unsigned int index) -{ - unsigned int tmp, freq = apll_freq_4x12[index].freq; - - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ - clk_set_parent(moutcore, mout_mpll); - - do { - cpu_relax(); - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); - tmp &= 0x7; - } while (tmp != 0x2); - - clk_set_rate(mout_apll, freq * 1000); - - /* MUX_CORE_SEL = APLL */ - clk_set_parent(moutcore, mout_apll); - - do { - cpu_relax(); - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); -} - -static void exynos4x12_set_frequency(unsigned int old_index, - unsigned int new_index) -{ - if (old_index > new_index) { - exynos4x12_set_clkdiv(new_index); - exynos4x12_set_apll(new_index); - } else if (old_index < new_index) { - exynos4x12_set_apll(new_index); - exynos4x12_set_clkdiv(new_index); - } -} - -int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) -{ - unsigned long rate; - - cpu_clk = clk_get(NULL, "armclk"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - moutcore = clk_get(NULL, "moutcore"); - if (IS_ERR(moutcore)) - goto err_moutcore; - - mout_mpll = clk_get(NULL, "mout_mpll"); - if (IS_ERR(mout_mpll)) - goto err_mout_mpll; - - rate = clk_get_rate(mout_mpll) / 1000; - - mout_apll = clk_get(NULL, "mout_apll"); - if (IS_ERR(mout_apll)) - goto err_mout_apll; - - if (info->type == EXYNOS_SOC_4212) - apll_freq_4x12 = apll_freq_4212; - else - apll_freq_4x12 = apll_freq_4412; - - info->mpll_freq_khz = rate; - /* 800Mhz */ - info->pll_safe_idx = L7; - info->cpu_clk = cpu_clk; - info->volt_table = exynos4x12_volt_table; - info->freq_table = exynos4x12_freq_table; - info->set_freq = exynos4x12_set_frequency; - - return 0; - -err_mout_apll: - clk_put(mout_mpll); -err_mout_mpll: - clk_put(moutcore); -err_moutcore: - clk_put(cpu_clk); - - pr_debug("%s: failed initialization\n", __func__); - return -EINVAL; -} diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c deleted file mode 100644 index 363a0b3..0000000 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2010-20122Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5250 - CPU frequency scaling support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/cpufreq.h> - -#include <mach/map.h> - -#include "exynos-cpufreq.h" - -static struct clk *cpu_clk; -static struct clk *moutcore; -static struct clk *mout_mpll; -static struct clk *mout_apll; - -static unsigned int exynos5250_volt_table[] = { - 1300000, 1250000, 1225000, 1200000, 1150000, - 1125000, 1100000, 1075000, 1050000, 1025000, - 1012500, 1000000, 975000, 950000, 937500, - 925000 -}; - -static struct cpufreq_frequency_table exynos5250_freq_table[] = { - {0, L0, 1700 * 1000}, - {0, L1, 1600 * 1000}, - {0, L2, 1500 * 1000}, - {0, L3, 1400 * 1000}, - {0, L4, 1300 * 1000}, - {0, L5, 1200 * 1000}, - {0, L6, 1100 * 1000}, - {0, L7, 1000 * 1000}, - {0, L8, 900 * 1000}, - {0, L9, 800 * 1000}, - {0, L10, 700 * 1000}, - {0, L11, 600 * 1000}, - {0, L12, 500 * 1000}, - {0, L13, 400 * 1000}, - {0, L14, 300 * 1000}, - {0, L15, 200 * 1000}, - {0, 0, CPUFREQ_TABLE_END}, -}; - -static struct apll_freq apll_freq_5250[] = { - /* - * values: - * freq - * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 - * clock divider for COPY, HPM, RESERVED - * PLL M, P, S - */ - APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0), - APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0), - APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0), - APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0), - APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0), - APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0), - APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0), - APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0), - APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0), - APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0), - APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1), - APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1), - APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1), - APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1), - APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2), - APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2), -}; - -static void set_clkdiv(unsigned int div_index) -{ - unsigned int tmp; - - /* Change Divider - CPU0 */ - - tmp = apll_freq_5250[div_index].clk_div_cpu0; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); - - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111) - cpu_relax(); - - /* Change Divider - CPU1 */ - tmp = apll_freq_5250[div_index].clk_div_cpu1; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); - - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11) - cpu_relax(); -} - -static void set_apll(unsigned int index) -{ - unsigned int tmp; - unsigned int freq = apll_freq_5250[index].freq; - - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ - clk_set_parent(moutcore, mout_mpll); - - do { - cpu_relax(); - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16); - tmp &= 0x7; - } while (tmp != 0x2); - - clk_set_rate(mout_apll, freq * 1000); - - /* MUX_CORE_SEL = APLL */ - clk_set_parent(moutcore, mout_apll); - - do { - cpu_relax(); - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU); - tmp &= (0x7 << 16); - } while (tmp != (0x1 << 16)); -} - -static void exynos5250_set_frequency(unsigned int old_index, - unsigned int new_index) -{ - if (old_index > new_index) { - set_clkdiv(new_index); - set_apll(new_index); - } else if (old_index < new_index) { - set_apll(new_index); - set_clkdiv(new_index); - } -} - -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) -{ - unsigned long rate; - - cpu_clk = clk_get(NULL, "armclk"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - moutcore = clk_get(NULL, "mout_cpu"); - if (IS_ERR(moutcore)) - goto err_moutcore; - - mout_mpll = clk_get(NULL, "mout_mpll"); - if (IS_ERR(mout_mpll)) - goto err_mout_mpll; - - rate = clk_get_rate(mout_mpll) / 1000; - - mout_apll = clk_get(NULL, "mout_apll"); - if (IS_ERR(mout_apll)) - goto err_mout_apll; - - info->mpll_freq_khz = rate; - /* 800Mhz */ - info->pll_safe_idx = L9; - info->cpu_clk = cpu_clk; - info->volt_table = exynos5250_volt_table; - info->freq_table = exynos5250_freq_table; - info->set_freq = exynos5250_set_frequency; - - return 0; - -err_mout_apll: - clk_put(mout_mpll); -err_mout_mpll: - clk_put(moutcore); -err_moutcore: - clk_put(cpu_clk); - - pr_err("%s: failed initialization\n", __func__); - return -EINVAL; -} -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support 2014-05-23 14:27 ` [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support Thomas Abraham @ 2014-05-26 6:18 ` Viresh Kumar 0 siblings, 0 replies; 14+ messages in thread From: Viresh Kumar @ 2014-05-26 6:18 UTC (permalink / raw) To: linux-arm-kernel On 23 May 2014 19:57, Thomas Abraham <thomas.ab@samsung.com> wrote: > From: Thomas Abraham <thomas.ab@samsung.com> > > Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over > to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos > specific cpufreq drivers for these platforms can be removed. > > Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> > --- > drivers/cpufreq/Kconfig.arm | 52 -------- > drivers/cpufreq/Makefile | 4 - > drivers/cpufreq/exynos-cpufreq.c | 218 ---------------------------------- > drivers/cpufreq/exynos-cpufreq.h | 99 --------------- > drivers/cpufreq/exynos4210-cpufreq.c | 157 ------------------------ > drivers/cpufreq/exynos4x12-cpufreq.c | 208 -------------------------------- > drivers/cpufreq/exynos5250-cpufreq.c | 183 ---------------------------- > 7 files changed, 921 deletions(-) > delete mode 100644 drivers/cpufreq/exynos-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos-cpufreq.h > delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c Acked-by: Viresh Kumar <viresh.kumar@linaro.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham ` (6 preceding siblings ...) 2014-05-23 14:27 ` [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support Thomas Abraham @ 2014-05-25 22:50 ` Kukjin Kim 2014-05-26 1:12 ` Tomasz Figa 7 siblings, 1 reply; 14+ messages in thread From: Kukjin Kim @ 2014-05-25 22:50 UTC (permalink / raw) To: linux-arm-kernel On 05/23/14 23:27, Thomas Abraham wrote: > Changes since v4: > - Various changes in clock code suggested by Tomasz Figa<t.figa@samsung.com> > - This series depends on mutiple other patches > [a] patch that introduces read-only attribute for clock dividers. > - http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259264.html > [b] the series "PM / OPP: move cpufreq specific helpers out of OPP layer" > - https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html > [c] the series "cpufreq: opp: Add device tree based lookup of boost mode frequency" > - http://www.spinics.net/lists/arm-kernel/msg334336.html > This series looks good to me after quick loking at but as I replied on other thread, I'm not sure above changes are ready for 3.16 or not... Maybe we can revisit this series for 3.17?...hmm... - Kukjin > Changes since v3: > - Addressed comments from Tomasz Figa<t.figa@samsung.com> > [http://www.spinics.net/lists/cpufreq/msg09290.html] > - Rebased to v3.15-rc4 > > Changes since v2: > - Safe operating voltage is not required while switching APLL frequency > since the temporary parent's clock is divided down to keep armclk within > permissible limits. Thanks to Heiko Stuebner<heiko@sntech.de> for > suggesting this. > - Rob had suggested to use max frequency for each of the divider clock > outputs instead of divider values. But due to certain SoC specific > characteristics, the divider values corresponding to the input clock > frequency for the CMU_CPU clock blocks have to be used. > > Changes since v1: > - Removes Exynos4x12 and Exynos5250 cpufreq driver also. > - Device tree based clock configuration lookup as suggested by Lukasz > Majewski and Tomasz Figa. > - safe operating point binding reworked as suggested by Shawn Guo. > > The patch series removes the use of Exynos specific cpufreq driver and enables > the use of cpufreq-cpu0 driver for Exynos4210, Exynos4x12 and Exynos5250 based > platforms. This is being done for few reasons. > > (a) The Exynos cpufreq driver reads/writes clock controller registers > bypassing the Exynos CCF driver which is sort of problematic. > (b) Removes the need for having clock controller register definitions > in the cpufreq driver and also removes the need for statically > io-remapping clock controller address space (helps in moving towards > multiplatform kernel). > > Thomas Abraham (7): > cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies > clk: samsung: add infrastructure to register cpu clocks > Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 > clk: exynos: use cpu-clock provider type to represent arm clock > ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data > ARM: Exynos: switch to using generic cpufreq-cpu0 driver > cpufreq: exynos: remove all exynos specific cpufreq driver support > > .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++ > .../devicetree/bindings/clock/exynos5250-clock.txt | 36 ++ > .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt | 2 + > arch/arm/boot/dts/exynos4210-origen.dts | 6 + > arch/arm/boot/dts/exynos4210-trats.dts | 6 + > arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 + > arch/arm/boot/dts/exynos4210.dtsi | 35 ++ > arch/arm/boot/dts/exynos4212.dtsi | 18 + > arch/arm/boot/dts/exynos4412-odroidx.dts | 6 + > arch/arm/boot/dts/exynos4412-origen.dts | 6 + > arch/arm/boot/dts/exynos4412-trats2.dts | 6 + > arch/arm/boot/dts/exynos4412.dtsi | 31 ++ > arch/arm/boot/dts/exynos4x12.dtsi | 36 ++ > arch/arm/boot/dts/exynos5250-arndale.dts | 6 + > arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 + > arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 + > arch/arm/boot/dts/exynos5250.dtsi | 41 ++ > arch/arm/mach-exynos/exynos.c | 4 +- > drivers/clk/samsung/Makefile | 2 +- > drivers/clk/samsung/clk-cpu.c | 448 ++++++++++++++++++++ > drivers/clk/samsung/clk-exynos4.c | 25 +- > drivers/clk/samsung/clk-exynos5250.c | 16 +- > drivers/clk/samsung/clk.h | 4 + > drivers/cpufreq/Kconfig | 1 + > drivers/cpufreq/Kconfig.arm | 52 --- > drivers/cpufreq/Makefile | 4 - > drivers/cpufreq/cpufreq-cpu0.c | 3 + > drivers/cpufreq/exynos-cpufreq.c | 218 ---------- > drivers/cpufreq/exynos-cpufreq.h | 99 ----- > drivers/cpufreq/exynos4210-cpufreq.c | 157 ------- > drivers/cpufreq/exynos4x12-cpufreq.c | 208 --------- > drivers/cpufreq/exynos5250-cpufreq.c | 183 -------- > include/dt-bindings/clock/exynos5250.h | 1 + > 33 files changed, 779 insertions(+), 936 deletions(-) > create mode 100644 drivers/clk/samsung/clk-cpu.c > delete mode 100644 drivers/cpufreq/exynos-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos-cpufreq.h > delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c > delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms 2014-05-25 22:50 ` [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Kukjin Kim @ 2014-05-26 1:12 ` Tomasz Figa 2014-05-26 1:37 ` Kukjin Kim 0 siblings, 1 reply; 14+ messages in thread From: Tomasz Figa @ 2014-05-26 1:12 UTC (permalink / raw) To: linux-arm-kernel Hi Kukjin, On 26.05.2014 00:50, Kukjin Kim wrote: > On 05/23/14 23:27, Thomas Abraham wrote: >> Changes since v4: >> - Various changes in clock code suggested by Tomasz >> Figa<t.figa@samsung.com> >> - This series depends on mutiple other patches >> [a] patch that introduces read-only attribute for clock dividers. >> - >> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259264.html >> >> [b] the series "PM / OPP: move cpufreq specific helpers out of OPP >> layer" >> - >> https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html >> [c] the series "cpufreq: opp: Add device tree based lookup of boost >> mode frequency" >> - http://www.spinics.net/lists/arm-kernel/msg334336.html >> > This series looks good to me after quick loking at but as I replied on > other thread, I'm not sure above changes are ready for 3.16 or not... > > Maybe we can revisit this series for 3.17?...hmm... Also two more issues: 1) DT bindings are not acked by DT maintainers, 2) there are my comments to DT bindings from v4 not addressed. There are also several comments about the code of v4 not addressed, but this is not that important, as opposed to DT bindings which are supposed to be stable ABI. Still, I don't think this is a big deal anymore, as we can have cpufreq working with multiplatform with my hack patch and polish the implementation of this series without any hurry. Best regards, Tomasz ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms 2014-05-26 1:12 ` Tomasz Figa @ 2014-05-26 1:37 ` Kukjin Kim 0 siblings, 0 replies; 14+ messages in thread From: Kukjin Kim @ 2014-05-26 1:37 UTC (permalink / raw) To: linux-arm-kernel Tomasz Figa wrote: > > Hi Kukjin, > Hi, > On 26.05.2014 00:50, Kukjin Kim wrote: > > On 05/23/14 23:27, Thomas Abraham wrote: > >> Changes since v4: > >> - Various changes in clock code suggested by Tomasz > >> Figa<t.figa@samsung.com> > >> - This series depends on mutiple other patches > >> [a] patch that introduces read-only attribute for clock dividers. > >> - > >> http://lists.infradead.org/pipermail/linux-arm-kernel/2014- > May/259264.html > >> > >> [b] the series "PM / OPP: move cpufreq specific helpers out of OPP > >> layer" > >> - > >> https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html > >> [c] the series "cpufreq: opp: Add device tree based lookup of boost > >> mode frequency" > >> - http://www.spinics.net/lists/arm-kernel/msg334336.html > >> > > This series looks good to me after quick loking at but as I replied on > > other thread, I'm not sure above changes are ready for 3.16 or not... > > > > Maybe we can revisit this series for 3.17?...hmm... > > Also two more issues: > > 1) DT bindings are not acked by DT maintainers, > 2) there are my comments to DT bindings from v4 not addressed. > > There are also several comments about the code of v4 not addressed, but > this is not that important, as opposed to DT bindings which are supposed > to be stable ABI. > > Still, I don't think this is a big deal anymore, as we can have cpufreq > working with multiplatform with my hack patch and polish the > implementation of this series without any hurry. > Yeah, I'm waiting for Viresh's ack on your v2 exynos-cpufreq changes for multiplatform... - Kukjin ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2014-05-26 6:18 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-05-23 14:27 [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 1/7] cpufreq: cpufreq-cpu0: allow use of optional boost mode frequencies Thomas Abraham 2014-05-26 6:12 ` Viresh Kumar 2014-05-23 14:27 ` [PATCH v5 2/7] clk: samsung: add infrastructure to register cpu clocks Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 4/7] clk: exynos: use cpu-clock provider type to represent arm clock Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 5/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data Thomas Abraham 2014-05-23 14:27 ` [PATCH v5 6/7] ARM: Exynos: switch to using generic cpufreq-cpu0 driver Thomas Abraham 2014-05-26 6:17 ` Viresh Kumar 2014-05-23 14:27 ` [PATCH v5 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support Thomas Abraham 2014-05-26 6:18 ` Viresh Kumar 2014-05-25 22:50 ` [PATCH v5 0/7] cpufreq: use cpufreq-cpu0 driver for exynos based platforms Kukjin Kim 2014-05-26 1:12 ` Tomasz Figa 2014-05-26 1:37 ` Kukjin Kim
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