From mboxrd@z Thu Jan  1 00:00:00 1970
From: kishon@ti.com (Kishon Vijay Abraham I)
Date: Thu, 19 Jun 2014 18:53:30 +0530
Subject: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks
 used for PHY
In-Reply-To: <53A2C690.1060106@ti.com>
References: <1401345500-20188-1-git-send-email-kishon@ti.com>
 <1401345500-20188-11-git-send-email-kishon@ti.com> <53A2C690.1060106@ti.com>
Message-ID: <53A2E452.5020109@ti.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi Tero,

On Thursday 19 June 2014 04:46 PM, Tero Kristo wrote:
> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>> Added missing 32khz clock used by PCIe PHY.
>> The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
> 
> You can drop the node documentation ref, and rather add a TRM reference about
> hardware details. Other than that, looks good to me.

You mean something like why 32KHz clock is used (**PRCM.PCIE_32K_GFCLK (based
on PRM.SYS_32K) for debounce and wakeup logic inside the PCIe1_PHY_RX**)? Or
something like **Figure 26-19. PCIe PHY Subsystem Integration of DRA TRM vE
shows how 32KHz clock is being used** ?

Thanks
Kishon

> 
> -Tero
> 
>>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Rajendra Nayak <rnayak@ti.com>
>> Cc: Tero Kristo <t-kristo@ti.com>
>> Cc: Paul Walmsley <paul@pwsan.com>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7xx-clocks.dtsi |    8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 44993ec..e1bd052 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1165,6 +1165,14 @@
>>           reg = <0x021c>, <0x0220>;
>>       };
>>
>> +    optfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 {
>> +        compatible = "ti,gate-clock";
>> +        clocks = <&sys_32k_ck>;
>> +        #clock-cells = <0>;
>> +        reg = <0x13b0>;
>> +        ti,bit-shift = <8>;
>> +    };
>> +
>>       optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
>>           compatible = "ti,divider-clock";
>>           clocks = <&apll_pcie_ck>;
>>
>