From mboxrd@z Thu Jan  1 00:00:00 1970
From: t-kristo@ti.com (Tero Kristo)
Date: Thu, 19 Jun 2014 16:24:33 +0300
Subject: [PATCH v2 07/18] ARM: dts: DRA7: Change the parent of
 apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
In-Reply-To: <53A2DEDA.5050104@ti.com>
References: <1401345500-20188-1-git-send-email-kishon@ti.com>
 <1401345500-20188-8-git-send-email-kishon@ti.com> <53A2C5B4.9080300@ti.com>
 <53A2DEDA.5050104@ti.com>
Message-ID: <53A2E491.5040406@ti.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On 06/19/2014 04:00 PM, Kishon Vijay Abraham I wrote:
> Hi Tero,
>
> On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote:
>> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>>> From: Keerthy <j-keerthy@ti.com>
>>>
>>> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
>>> from dpll_pcie_ref_ck.
>>
>> Why? Needs a better changelog also.
>
> Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
> shows the signal name for the output of post divider (M2) is CLKOUTLDO.
>
> Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
> input to apll mux.
>
> So the actual output of dpll should be dpll_pcie_ref_m2ldo_ck instead of
> dpll_pcie_ref_ck (which is the input of apll mux).

Yep, this is what I want to see in the changelog, so please repost. The 
original changelog had no info on it whatsoever.

-Tero

>
> Thanks
> Kishon
>>
>> -Tero
>>
>>>
>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>> Cc: Tero Kristo <t-kristo@ti.com>
>>> Cc: Paul Walmsley <paul@pwsan.com>
>>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>>    arch/arm/boot/dts/dra7xx-clocks.dtsi |    2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>>> index 55e95c5..44993ec 100644
>>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>>> @@ -1152,7 +1152,7 @@
>>>
>>>        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
>>>            compatible = "ti,mux-clock";
>>> -        clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
>>> +        clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
>>>            #clock-cells = <0>;
>>>            reg = <0x021c 0x4>;
>>>            ti,bit-shift = <7>;
>>>
>>