[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Rahul Sharma]

Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
Based on Kukjin's for-next branch.

 drivers/clk/samsung/clk-exynos5250.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
 	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
 	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-			GATE_IP_DISP1, 2, 0, 0),
+			GATE_IP_DISP1, 9, 0, 0),
 	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
 			GATE_IP_DISP1, 8, 0, 0),
 	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
-- 
1.7.9.5

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Sachin Kamat]

On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> Change bit from 2 to 9 for tv (mixer) sysmmu clock.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
> Based on Kukjin's for-next branch.
>
>  drivers/clk/samsung/clk-exynos5250.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 1fad4c5..184f642 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>         GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
>         GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
>         GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
> -                       GATE_IP_DISP1, 2, 0, 0),
> +                       GATE_IP_DISP1, 9, 0, 0),

SysMMU TV corresponds to bit 9 as per user manual of 5250.
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Rahul Sharma]

Hi Kukjin,

Please take this fix in your tree.

Regards,
Rahul Sharma

On 19 June 2014 11:35, Sachin Kamat <sachin.kamat@samsung.com> wrote:
> On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> Change bit from 2 to 9 for tv (mixer) sysmmu clock.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> ---
>> Based on Kukjin's for-next branch.
>>
>>  drivers/clk/samsung/clk-exynos5250.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>> index 1fad4c5..184f642 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>>         GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
>>         GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
>>         GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
>> -                       GATE_IP_DISP1, 2, 0, 0),
>> +                       GATE_IP_DISP1, 9, 0, 0),
>
> SysMMU TV corresponds to bit 9 as per user manual of 5250.
> Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Tomasz Figa]

Hi Rahul,

On 25.06.2014 13:22, Rahul Sharma wrote:
> Hi Kukjin,
> 
> Please take this fix in your tree.

This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.

Best regards,
Tomasz

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Kukjin Kim]

Tomasz Figa wrote:
> 
> Hi Rahul,
> 
> On 25.06.2014 13:22, Rahul Sharma wrote:
> > Hi Kukjin,
> >
> > Please take this fix in your tree.
> 
> This is a patch for Samsung clock drivers, so I'll apply it when about
> to send fixes pull request to Mike.
> 
Yes, I also checked the datasheet and this change is correct.

If you want, please add my ack on the patch.

Thanks,
Kukjin

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Rahul Sharma]

Sure Tomasz, Kukjin.
Thanks for the update.

Regards.

On 25 June 2014 16:56, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Tomasz Figa wrote:
>>
>> Hi Rahul,
>>
>> On 25.06.2014 13:22, Rahul Sharma wrote:
>> > Hi Kukjin,
>> >
>> > Please take this fix in your tree.
>>
>> This is a patch for Samsung clock drivers, so I'll apply it when about
>> to send fixes pull request to Mike.
>>
> Yes, I also checked the datasheet and this change is correct.
>
> If you want, please add my ack on the patch.
>
> Thanks,
> Kukjin
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

[Tomasz Figa]

On 19.06.2014 07:47, Rahul Sharma wrote:
> Change bit from 2 to 9 for tv (mixer) sysmmu clock.
> 
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
> Based on Kukjin's for-next branch.
> 
>  drivers/clk/samsung/clk-exynos5250.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 1fad4c5..184f642 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>  	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
>  	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
>  	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
> -			GATE_IP_DISP1, 2, 0, 0),
> +			GATE_IP_DISP1, 9, 0, 0),
>  	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
>  			GATE_IP_DISP1, 8, 0, 0),
>  	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
> 

Applied as a fix for 3.16.

Best regards,
Tomasz