From: cov@codeaurora.org (Christopher Covington)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 5/5] arm64: add runtime system sanity checks
Date: Thu, 26 Jun 2014 16:29:10 -0400 [thread overview]
Message-ID: <53AC8296.808@codeaurora.org> (raw)
In-Reply-To: <1403795926-17139-6-git-send-email-mark.rutland@arm.com>
Hi Mark,
On 06/26/2014 11:18 AM, Mark Rutland wrote:
> Unexpected variation in certain system register values across CPUs is an
> indicator of potential problems with a system. The kernel expects CPUs
> to be mostly identical in terms of supported features, even in systems
> with heterogeneous CPUs, with uniform instruction set support being
> critical for the correct operation of userspace.
>
> To help detect issues early where hardware violates the expectations of
> the kernel, this patch adds simple runtime sanity checks on important ID
> registers in the bring up path of each CPU.
>
> Where CPUs are fundamentally mismatched, set TAINT_CPU_OUT_OF_SPEC.
> Given that the kernel assumes CPUs are identical feature wise, let's not
> pretend that we expect such configurations to work. Supporting such
> configurations would require massive rework, and hopefully they will
> never exist.
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---
> arch/arm64/kernel/cpuinfo.c | 92 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> + /* If different, timekeeping will be broken (especially with KVM) */
> + diff |= CHECK(cntfrq, boot, cur, cpu);
You're calling this a "CPU feature" but I thought this was purely a firmware
setting. Does the architecture even allow hardware to program this register?
Additionally, in arch_timer_detect_rate it appears that a device tree setting
takes precedence, but you're not checking that.
> + /*
> + * Mismatched CPU features are a recipe for disaster. Don't even
> + * pretend to support them.
> + */
> + WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
> + "Unsupported CPU feature variation.");
> +}
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.
next prev parent reply other threads:[~2014-06-26 20:29 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-26 15:18 [PATCHv3 0/5] arm64: handle heterogeneous system register values Mark Rutland
2014-06-26 15:18 ` [PATCHv3 1/5] arm64: add MIDR_EL1 field accessors Mark Rutland
2014-06-27 14:01 ` Will Deacon
2014-06-27 14:06 ` Russell King - ARM Linux
2014-06-27 14:07 ` Will Deacon
2014-06-26 15:18 ` [PATCHv3 2/5] arm64: cpuinfo: record cpu system register values Mark Rutland
2014-06-27 15:34 ` Will Deacon
2014-06-27 16:34 ` Mark Rutland
2014-06-26 15:18 ` [PATCHv3 3/5] arm64: cpuinfo: print info for all CPUs Mark Rutland
2014-06-27 17:35 ` Ard Biesheuvel
2014-06-26 15:18 ` [PATCHv3 4/5] arm64: cachetype: report weakest cache policy Mark Rutland
2014-06-26 15:18 ` [PATCHv3 5/5] arm64: add runtime system sanity checks Mark Rutland
2014-06-26 20:29 ` Christopher Covington [this message]
2014-06-27 8:58 ` Will Deacon
2014-06-27 9:56 ` Mark Rutland
2014-06-27 16:56 ` Christopher Covington
2014-06-27 17:35 ` Mark Rutland
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