From: ttynkkynen@nvidia.com (Tuomas Tynkkynen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124
Date: Fri, 11 Jul 2014 18:11:41 +0300 [thread overview]
Message-ID: <53BFFEAD.7000405@nvidia.com> (raw)
In-Reply-To: <20140711145735.GB6523@ulmo>
On 11/07/14 17:57, Thierry Reding wrote:
>> I don't think that's going to work? The voltage scaling is handled in hw.
>
> Do we have to handle it in hardware or can we opt to do it in software,
> too?
>
With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
it's possible to stay in open-loop mode and do it in SW, but there's
not much point in that.
--
nvpublic
next prev parent reply other threads:[~2014-07-11 15:11 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-10 21:42 [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-07-11 16:28 ` Andrew Bresticker
2014-07-11 16:48 ` Tuomas Tynkkynen
2014-07-11 17:08 ` Andrew Bresticker
2014-07-11 17:21 ` Tuomas Tynkkynen
2014-07-14 8:38 ` Thierry Reding
2014-07-14 9:12 ` Mark Brown
2014-07-14 9:24 ` Thierry Reding
2014-07-14 10:22 ` Mark Brown
2014-07-15 20:23 ` Tuomas Tynkkynen
2014-07-15 22:52 ` Mark Brown
2014-07-16 8:01 ` Thierry Reding
2014-07-16 11:00 ` Mark Brown
2014-07-10 21:42 ` [PATCH 02/13] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 03/13] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 04/13] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 05/13] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 06/13] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 07/13] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 08/13] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 09/13] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 10/13] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-07-11 7:14 ` Mikko Perttunen
2014-07-10 21:42 ` [PATCH 11/13] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
2014-07-11 4:35 ` Viresh Kumar
2014-07-11 9:12 ` Peter De Schrijver
2014-07-11 9:14 ` Viresh Kumar
2014-07-11 14:57 ` Thierry Reding
2014-07-11 15:11 ` Tuomas Tynkkynen [this message]
2014-07-11 15:15 ` Thierry Reding
2014-07-11 15:29 ` Tuomas Tynkkynen
2014-07-11 16:33 ` Andrew Bresticker
2014-07-11 14:14 ` Tuomas Tynkkynen
2014-07-11 14:37 ` Viresh Kumar
2014-07-10 21:42 ` [PATCH 13/13] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-07-11 15:32 ` [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Mike Turquette
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