From mboxrd@z Thu Jan  1 00:00:00 1970
From: f.fainelli@gmail.com (Florian Fainelli)
Date: Wed, 13 Aug 2014 11:41:05 -0700
Subject: PL310 cache initialization/fixup for BCM63138
In-Reply-To: <20140813182435.GM30401@n2100.arm.linux.org.uk>
References: <53EBA9CF.4030902@gmail.com>
 <20140813182435.GM30401@n2100.arm.linux.org.uk>
Message-ID: <53EBB141.7050206@gmail.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On 08/13/2014 11:24 AM, Russell King - ARM Linux wrote:
> On Wed, Aug 13, 2014 at 11:09:19AM -0700, Florian Fainelli wrote:
>> Hi Russell, Arnd,
>>
>> The PL310 cache present on BCM63138 comes up with wrong values out of
>> reset in particular, I need to at least override the way-size to be
>> 32KiB otherwise.
>>
>> Right now, I am overriding the auxiliary control register by supplying a
>> non 0xffffffff aux_ctrl_mask to l2x0_of_init().
>>
>> Should I rather use a separate compatible string for it and perform the
>> "fixup" in a separate of_parse() callback, or in a separate fixup()
>> callback?
>>
>> Or is it recommended to keep overriding the aux_ctrl_mask as part of the
>> call to l2x0_of_init()?
> 
> The correct answer is to research how to specify cache attributes in DT,
> and create an appropriate set of properties described by that, and have
> the l2x0 OF init code parse those, and create the appropriate aux control
> register values from those.
> 
> I forget exactly what they are, but I do know that there is a standardised
> set of DT properties to describe the geometry of caches - I came across
> them about six months back when I worked on the L2 code.

Alright, I will take a stab at using the ePAPR cache properties.

How about PL310 specific properties such as instruction prefetc and
non-secure access, would boolean properties work for these?

Thanks!
--
Florian