[PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend

[nm@ti.com (Nishanth Menon)]

On 08/27/2014 01:58 PM, Kevin Hilman wrote:
> Nishanth Menon <nm@ti.com> writes:
> 
>> From: Rajendra Nayak <rnayak@ti.com>
>>
>> On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
>> and instead attempt a CPU RET and side effect, MPU RET in suspend.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>> [nm at ti.com: update to do save_state only on DRA7]
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> ---
>>  arch/arm/mach-omap2/omap-mpuss-lowpower.c |    4 ++++
>>  arch/arm/mach-omap2/omap-wakeupgen.c      |    2 +-
>>  arch/arm/mach-omap2/pm44xx.c              |    9 +++++++--
>>  3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
>> index 207fce2..0d640eb 100644
>> --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
>> +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
>> @@ -242,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
>>  		save_state = 1;
>>  		break;
>>  	case PWRDM_POWER_RET:
>> +		if (soc_is_omap54xx() || soc_is_dra7xx()) {
> 
> Aren't we trying to get away from these soc_* checks for anything other
> than init code?

I would expect that to take place in stages as part of which the next
level of cleanup is to move PRM into drivers. Currently our wakeupgen,
prm code does have quiet a few needs of dealing with soc_is checks
primarily from having to re-architect code in two different directions
- we want to move into just one direction eventually - to prm drivers
and as less code in mach-omap2 which is already in the works.


-- 
Regards,
Nishanth Menon