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From: tomasz.figa@gmail.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 4/7] ARM: l2c: Add support for overriding prefetch settings
Date: Wed, 24 Sep 2014 13:19:45 +0200	[thread overview]
Message-ID: <5422A8D1.1000507@gmail.com> (raw)
In-Reply-To: <20140924111446.GE5729@leverpostej>

On 24.09.2014 13:14, Mark Rutland wrote:
> On Wed, Sep 24, 2014 at 12:05:38PM +0100, Marek Szyprowski wrote:
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
>> settings configured in registers leading to crashes if L2C is enabled
>> without overriding them. This patch introduces bindings to enable
>> prefetch settings to be specified from DT and necessary support in the
>> driver.
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>  Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++++++
>>  arch/arm/mm/cache-l2x0.c                       | 39 ++++++++++++++++++++++++++
>>  2 files changed, 49 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
>> index af527ee111c2..3443d2d76788 100644
>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>> @@ -47,6 +47,16 @@ Optional properties:
>>  - cache-id-part: cache id part number to be used if it is not present
>>    on hardware
>>  - wt-override: If present then L2 is forced to Write through mode
>> +- arm,double-linefill : Override double linefill enable setting. Enable if
>> +  non-zero, disable if zero.
>> +- arm,double-linefill-incr : Override double linefill on INCR read. Enable
>> +  if non-zero, disable if zero.
>> +- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
>> +  if non-zero, disable if zero.
>> +- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
>> +  disable if zero.
> 
> I'm not too keen on tristate properties. Is this level of flexibility
> really required?
> 
> What exact overrides do you need for boards you know of? Why do these
> cause crashes if not overridden?

Well, this is all thanks to broken firmware, which doesn't initialize
those values properly on certain systems and they must be overridden. On
the other side, there are systems with firmware that does it correctly
and for those the boot defaults should be preferred. I don't see any
other reasonable option of handling this.

As for why they cause crashes, I'm not an expert if it is about L2C
internals, so I can't really tell, but apparently the cache can work
correctly only on certain settings.

Best regards,
Tomasz

  reply	other threads:[~2014-09-24 11:19 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-24 11:05 [PATCH v5 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 1/7] ARM: l2c: Refactor the driver to use commit-like interface Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 4/7] ARM: l2c: Add support for overriding prefetch settings Marek Szyprowski
2014-09-24 11:14   ` Mark Rutland
2014-09-24 11:19     ` Tomasz Figa [this message]
2014-09-24 12:10       ` Mark Rutland
2014-09-24 22:12         ` Russell King - ARM Linux
2014-09-24 11:05 ` [PATCH v5 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume Marek Szyprowski
2014-09-24 11:05 ` [PATCH v5 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Marek Szyprowski
2015-01-14 15:46 ` [PATCH v5 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Alexandre Belloni
2015-01-14 16:21   ` Russell King - ARM Linux
2015-01-14 16:49     ` Alexandre Belloni

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