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Tue, 08 Jun 2021 07:01:02 -0700 (PDT) Subject: Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs To: Kewei Xu , wsa@the-dreams.de Cc: robh+dt@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, leilk.liu@mediatek.com, qii.wang@mediatek.com, qiangming.xia@mediatek.com References: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> <1623122200-1896-3-git-send-email-kewei.xu@mediatek.com> From: Matthias Brugger Message-ID: <54301510-e0d5-0762-1979-b194b8fd5eb8@gmail.com> Date: Tue, 8 Jun 2021 16:01:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <1623122200-1896-3-git-send-email-kewei.xu@mediatek.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210608_070204_704577_824A2B1B X-CRM114-Status: GOOD ( 21.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08/06/2021 05:16, Kewei Xu wrote: > From: "Kewei.Xu" > > When a timeout error occurs in i2c transter, it is usually related > to the i2c/dma IP hardware configuration. Therefore, the purpose of > this patch is to dump the key register values of i2c/dma when a > timeout occurs in i2c for debugging. > > Signed-off-by: Kewei.Xu > --- > drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 95 insertions(+), 2 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c > index 5ddfa4e..e65a41e 100644 > --- a/drivers/i2c/busses/i2c-mt65xx.c > +++ b/drivers/i2c/busses/i2c-mt65xx.c > @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET { > OFFSET_HS, > OFFSET_SOFTRESET, > OFFSET_DCM_EN, > + OFFSET_MULTI_DMA, > OFFSET_PATH_DIR, > OFFSET_DEBUGSTAT, > OFFSET_DEBUGCTRL, > @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET { > [OFFSET_TRANSFER_LEN_AUX] = 0x44, > [OFFSET_CLOCK_DIV] = 0x48, > [OFFSET_SOFTRESET] = 0x50, > + [OFFSET_MULTI_DMA] = 0x84, > [OFFSET_SCL_MIS_COMP_POINT] = 0x90, > - [OFFSET_DEBUGSTAT] = 0xe0, > + [OFFSET_DEBUGSTAT] = 0xe4, Is this offset only for mt8192 or also for mt8183? In any case that should go in as another patch. Either a fix or a new mt_i2c_regs_v3[] Regards, Matthias > [OFFSET_DEBUGCTRL] = 0xe8, > [OFFSET_FIFO_STAT] = 0xf4, > [OFFSET_FIFO_THRESH] = 0xf8, > @@ -828,6 +830,96 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) > return 0; > } > > +static void i2c_dump_register(struct mtk_i2c *i2c) > +{ > + dev_err(i2c->dev, "SLAVE_ADDR[0x%x]: 0x%x, INTR_MASK[0x%x]: 0x%x\n", > + OFFSET_SLAVE_ADDR, > + (mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR)), > + OFFSET_INTR_MASK, > + (mtk_i2c_readw(i2c, OFFSET_INTR_MASK))); > + dev_err(i2c->dev, "INTR_STAT[0x%x]: 0x%x, CONTROL[0x%x]: 0x%x\n", > + OFFSET_INTR_STAT, > + (mtk_i2c_readw(i2c, OFFSET_INTR_STAT)), > + OFFSET_CONTROL, > + (mtk_i2c_readw(i2c, OFFSET_CONTROL))); > + dev_err(i2c->dev, "TRANSFER_LEN[0x%x]: 0x%x, TRANSAC_LEN[0x%x]: 0x%x\n", > + OFFSET_TRANSFER_LEN, > + (mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN)), > + OFFSET_TRANSAC_LEN, > + (mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN))); > + dev_err(i2c->dev, "DELAY_LEN[0x%x]: 0x%x, HTIMING[0x%x]: 0x%x\n", > + OFFSET_DELAY_LEN, > + (mtk_i2c_readw(i2c, OFFSET_DELAY_LEN)), > + OFFSET_TIMING, > + (mtk_i2c_readw(i2c, OFFSET_TIMING))); > + dev_err(i2c->dev, "OFFSET_START[0x%x]: 0x%x\n", > + OFFSET_START, > + mtk_i2c_readw(i2c, OFFSET_START)); > + dev_err(i2c->dev, "OFFSET_EXT_CONF[0x%x]: 0x%x\n", > + OFFSET_EXT_CONF, > + mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); > + dev_err(i2c->dev, "OFFSET_HS[0x%x]: 0x%x\n", > + OFFSET_HS, > + mtk_i2c_readw(i2c, OFFSET_HS)); > + dev_err(i2c->dev, "OFFSET_IO_CONFIG[0x%x]: 0x%x\n", > + OFFSET_IO_CONFIG, > + mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); > + dev_err(i2c->dev, "OFFSET_FIFO_ADDR_CLR[0x%x]: 0x%x\n", > + OFFSET_FIFO_ADDR_CLR, > + mtk_i2c_readw(i2c, OFFSET_FIFO_ADDR_CLR)); > + dev_err(i2c->dev, "TRANSFER_LEN_AUX[0x%x]: 0x%x\n", > + OFFSET_TRANSFER_LEN_AUX, > + mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); > + dev_err(i2c->dev, "CLOCK_DIV[0x%x]: 0x%x\n", > + OFFSET_CLOCK_DIV, > + mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV)); > + dev_err(i2c->dev, "FIFO_STAT[0x%x]: 0x%x, FIFO_THRESH[0x%x]: 0x%x\n", > + OFFSET_FIFO_STAT, > + mtk_i2c_readw(i2c, OFFSET_FIFO_STAT), > + OFFSET_FIFO_THRESH, > + mtk_i2c_readw(i2c, OFFSET_FIFO_THRESH)); > + dev_err(i2c->dev, "DCM_EN[0x%x] 0x%x\n", > + OFFSET_DCM_EN, > + mtk_i2c_readw(i2c, OFFSET_DCM_EN)); > + dev_err(i2c->dev, "DEBUGSTAT[0x%x]: 0x%x, DEBUGCTRL[0x%x]: 0x%x\n", > + OFFSET_DEBUGSTAT, > + (mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)), > + OFFSET_DEBUGCTRL, > + (mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL))); > + > + if (i2c->dev_comp->regs == mt_i2c_regs_v2) { > + dev_err(i2c->dev, "OFFSET_LTIMING[0x%x]: 0x%x\n", > + OFFSET_LTIMING, > + mtk_i2c_readw(i2c, OFFSET_LTIMING)); > + dev_err(i2c->dev, "MULTI_DMA[0x%x]: 0x%x\n", > + OFFSET_MULTI_DMA, > + (mtk_i2c_readw(i2c, OFFSET_MULTI_DMA))); > + } > + > + dev_err(i2c->dev, "OFFSET_INT_FLAG = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_INT_FLAG)); > + dev_err(i2c->dev, "OFFSET_INT_EN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_INT_EN)); > + dev_err(i2c->dev, "OFFSET_EN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_EN)); > + dev_err(i2c->dev, "OFFSET_RST = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RST)); > + dev_err(i2c->dev, "OFFSET_CON = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_CON)); > + dev_err(i2c->dev, "OFFSET_TX_MEM_ADDR = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR)); > + dev_err(i2c->dev, "OFFSET_RX_MEM_ADDR = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); > + dev_err(i2c->dev, "OFFSET_TX_LEN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_LEN)); > + dev_err(i2c->dev, "OFFSET_RX_LEN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_LEN)); > + dev_err(i2c->dev, "OFFSET_TX_4G_MODE = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_4G_MODE)); > + dev_err(i2c->dev, "OFFSET_RX_4G_MODE = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); > +} > + > static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, > int num, int left_num) > { > @@ -1034,7 +1126,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, > } > > if (ret == 0) { > - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); > + dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); > + i2c_dump_register(i2c); > mtk_i2c_init_hw(i2c); > return -ETIMEDOUT; > } > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel