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Thu, 27 Nov 2025 19:48:39 +0800 (CST) Received: from [10.67.120.103] (10.67.120.103) by kwepemr100010.china.huawei.com (7.202.195.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Thu, 27 Nov 2025 19:48:38 +0800 Message-ID: <54558610-1062-4632-a44c-d06443bdc736@huawei.com> Date: Thu, 27 Nov 2025 19:48:38 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] arm64/sysreg: Add HDBSS related register information To: Marc Zyngier , Tian Zheng CC: , , , , , , , , , , , , , , , , References: <20251121092342.3393318-1-zhengtian10@huawei.com> <20251121092342.3393318-2-zhengtian10@huawei.com> <86wm3iqlz8.wl-maz@kernel.org> From: Tian Zheng In-Reply-To: <86wm3iqlz8.wl-maz@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.120.103] X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr100010.china.huawei.com (7.202.195.125) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251127_034854_529305_A2A9A98D X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2025/11/22 20:40, Marc Zyngier wrote: > On Fri, 21 Nov 2025 09:23:38 +0000, > Tian Zheng wrote: >> >> From: eillon >> >> The ARM architecture added the HDBSS feature and descriptions of >> related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version, >> add them to Linux. >> >> Signed-off-by: eillon >> Signed-off-by: Tian Zheng >> --- >> arch/arm64/include/asm/esr.h | 2 ++ >> arch/arm64/include/asm/kvm_arm.h | 1 + >> arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ >> 3 files changed, 31 insertions(+) >> >> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h >> index e1deed824464..a6f3cf0b9b86 100644 >> --- a/arch/arm64/include/asm/esr.h >> +++ b/arch/arm64/include/asm/esr.h >> @@ -159,6 +159,8 @@ >> #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) >> >> /* ISS2 field definitions for Data Aborts */ >> +#define ESR_ELx_HDBSSF_SHIFT (11) >> +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) >> #define ESR_ELx_TnD_SHIFT (10) >> #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) >> #define ESR_ELx_TagAccess_SHIFT (9) >> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h >> index 1da290aeedce..b71122680a03 100644 >> --- a/arch/arm64/include/asm/kvm_arm.h >> +++ b/arch/arm64/include/asm/kvm_arm.h >> @@ -124,6 +124,7 @@ >> TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) >> >> /* VTCR_EL2 Registers bits */ >> +#define VTCR_EL2_HDBSS (1UL << 45) > > I think it is time to convert VTCR_EL2 to the sysreg infrastructure > instead of adding extra bits here. > Sure, I will move VTCR_EL2_HDBSS into the sysreg description file alongside VTCR_EL2. > M.