From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 4/6] arm64: Add DTS support for FSL's LS2085A SoC
Date: Wed, 26 Nov 2014 10:17:04 +0000 [thread overview]
Message-ID: <5475A8A0.2090405@arm.com> (raw)
In-Reply-To: <BY1PR0301MB1303F8B412AFF14129DA564E82700@BY1PR0301MB1303.namprd03.prod.outlook.com>
On 26/11/14 05:11, bhupesh.sharma at freescale.com wrote:
> Hi Marc,
>
> [big snip..]
>
>>
>>> + timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
>>> + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
>>> + <1 11 0x1>, /* Virtual PPI, edge triggered */
>>> + <1 10 0x1>; /* Hypervisor PPI, edge triggered */
>>
>> Are you sure about this "edge triggered"? The A57 TRM suggests otherwise:
>>
>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1
>> 382454511590.html
>>
>
> Actually I did read the TRM but was confused by the "edge triggered" conventions
> used by Juno ARMv8 DTSI (see [1]). I see other ARMv8 DTSI also using the "edge triggered"
> notion, so I was wondering if I am missing some A57 errata or these DTSI also need fixing.
Yeah, the Juno DT is wrong as well. Funny how only the wrong bits get
copied over and over... I'll get Juno fixed.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2014-11-26 10:17 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <BY1PR0301MB13037E20B2B52E612A6EBC0182700@BY1PR0301MB1303.namprd03.prod.outlook.com>
2014-11-26 5:11 ` [PATCH v5 4/6] arm64: Add DTS support for FSL's LS2085A SoC bhupesh.sharma at freescale.com
2014-11-26 10:17 ` Marc Zyngier [this message]
2014-11-15 10:46 [PATCH v5 0/6] ARM64: Add " Bhupesh Sharma
2014-11-15 10:46 ` [PATCH v5 4/6] arm64: Add DTS " Bhupesh Sharma
2014-11-16 18:39 ` Marc Zyngier
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