From mboxrd@z Thu Jan 1 00:00:00 1970 From: pankaj.dubey@samsung.com (Pankaj Dubey) Date: Tue, 09 Dec 2014 11:35:27 +0530 Subject: [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain In-Reply-To: <1417510196-6714-9-git-send-email-cw00.choi@samsung.com> References: <1417510196-6714-1-git-send-email-cw00.choi@samsung.com> <1417510196-6714-9-git-send-email-cw00.choi@samsung.com> Message-ID: <54869127.6030307@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: > This patch adds the mux/divider/gate clocks for CMU_AUD domain which > includes the clocks of Cortex-A6/Bus/Audio clocks. Cortex-A6? I think it should be Cortex-A5? > > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Signed-off-by: Chanwoo Choi > Acked-by: Inki Dae > Acked-by: Geunsik Lim > --- > .../devicetree/bindings/clock/exynos5433-clock.txt | 7 + > drivers/clk/samsung/clk-exynos5433.c | 173 +++++++++++++++++++++ > include/dt-bindings/clock/exynos5433.h | 53 +++++++ > 3 files changed, 233 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > index 8d3dad4..9a6ae75 100644 > --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > @@ -23,6 +23,8 @@ Required Properties: > which generates clocks for G2D/MDMA IPs. > - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP > which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. > + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD > + which generates clocks for Cortex-A5/BUS/AUDIO clocks. Commit message says Cortex-A6? > > - reg: physical base address of the controller and length of memory mapped > region. > @@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed below. > #clock-cells = <1>; > }; > > + cmu_aud: clock-controller at 0x114c0000 { > + compatible = "samsung,exynos5433-cmu-aud"; > + reg = <0x114c0000 0x0b04>; > + #clock-cells = <1>; > + }; > > Example 2: UART controller node that consumes the clock generated by the clock > controller. > diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c > index ec23e97..99262e0 100644 > --- a/drivers/clk/samsung/clk-exynos5433.c > +++ b/drivers/clk/samsung/clk-exynos5433.c > @@ -2454,3 +2454,176 @@ static void __init exynos5433_cmu_disp_init(struct device_node *np) > > CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", > exynos5433_cmu_disp_init); > + > +/* > + * Register offset definitions for CMU_AUD > + */ > +#define MUX_SEL_AUD0 0x0200 > +#define MUX_SEL_AUD1 0x0204 > +#define MUX_ENABLE_AUD0 0x0300 > +#define MUX_ENABLE_AUD1 0x0304 > +#define MUX_STAT_AUD0 0x0400 > +#define DIV_AUD0 0x0600 > +#define DIV_AUD1 0x0604 > +#define DIV_STAT_AUD0 0x0700 > +#define DIV_STAT_AUD1 0x0704 > +#define ENABLE_ACLK_AUD 0x0800 > +#define ENABLE_PCLK_AUD 0x0900 > +#define ENABLE_SCLK_AUD0 0x0a00 > +#define ENABLE_SCLK_AUD1 0x0a04 > +#define ENABLE_IP_AUD0 0x0b00 > +#define ENABLE_IP_AUD1 0x0b04 > + > +static unsigned long aud_clk_regs[] __initdata = { > + MUX_SEL_AUD0, > + MUX_SEL_AUD1, > + MUX_ENABLE_AUD0, > + MUX_ENABLE_AUD1, > + MUX_STAT_AUD0, > + DIV_AUD0, > + DIV_AUD1, > + DIV_STAT_AUD0, > + DIV_STAT_AUD1, > + ENABLE_ACLK_AUD, > + ENABLE_PCLK_AUD, > + ENABLE_SCLK_AUD0, > + ENABLE_SCLK_AUD1, > + ENABLE_IP_AUD0, > + ENABLE_IP_AUD1, > +}; > + > +/* list of all parent clock list */ > +PNAME(mout_aud_pll_user_aud_p) = { "fin_pll", "fout_aud_pll", }; > +PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; > +PNAME(mout_sclk_aud_i2s_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; Above two lines can be clubbed with some common name as both has same parent clocks. > + > +static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { > + FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 188000000), > + FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 188000000), > + FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 188000000), Are you sure about these clock rates? As per UM I have, these are having rates as 33 MHz, 25 MHz and 50 MHz respectively. > +}; > + > +static struct samsung_mux_clock aud_mux_clks[] __initdata = { > + /* MUX_SEL_AUD0 */ > + MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", > + mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), > + > + /* MUX_SEL_AUD1 */ > + MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, > + MUX_SEL_AUD1, 8, 1), > + MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, > + MUX_SEL_AUD1, 0, 1), > +}; > + Thanks, Pankaj Dubey