[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Dmitry Osipenko]

Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
location storing from late to early and as result broke suspend on tegra20.
PMC scratch register 41 was used by tegra lp1 suspend core code for storing
physical memory address of common resume function and in the same time used by
tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
strict order of scratch register use. Fix it by using scratch 40 instead of 41
for tegra_resume() location store.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: <stable@vger.kernel.org> # v3.17+
---
I see 2 other solutions:

1) Replace PMC driver PM ops with syscore
2) Move tegra_resume() storing back to tegra arch suspend code

For me originally proposed solution looks best, but I'm not aware of any special
use of scratch 40 outside kernel and bootloader, so please let me know if there
is any issue with it. It works just fine on my tablet.

 arch/arm/mach-tegra/sleep-tegra20.S | 4 ++--
 arch/arm/mach-tegra/sleep-tegra30.S | 4 ++--
 arch/arm/mach-tegra/sleep.h         | 1 +
 drivers/soc/tegra/pmc.c             | 6 +++---
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index be4bc5f..3574785 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -327,7 +327,7 @@ tegra20_iram_start:
  * system clock running on the same PLL that it suspended at), and
  * jumps to tegra_resume to restore virtual addressing and PLLX.
  * The physical address of tegra_resume expected to be stored in
- * PMC_SCRATCH41.
+ * PMC_SCRATCH40.
  *
  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
  */
@@ -401,7 +401,7 @@ exit_selfrefresh_loop:
 	str	r1, [r0, #EMC_REQ_CTRL]
 
 	mov32	r0, TEGRA_PMC_BASE
-	ldr	r0, [r0, #PMC_SCRATCH41]
+	ldr	r0, [r0, #PMC_SCRATCH40]
 	ret	r0			@ jump to tegra_resume
 ENDPROC(tegra20_lp1_reset)
 
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 5d8d13a..234959c 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -314,7 +314,7 @@ tegra30_iram_start:
  * system clock running on the same PLL that it suspended at), and
  * jumps to tegra_resume to restore virtual addressing.
  * The physical address of tegra_resume expected to be stored in
- * PMC_SCRATCH41.
+ * PMC_SCRATCH40.
  *
  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
  */
@@ -529,7 +529,7 @@ zcal_done:
 __no_dual_emc_chanl:
 
 	mov32	r0, TEGRA_PMC_BASE
-	ldr	r0, [r0, #PMC_SCRATCH41]
+	ldr	r0, [r0, #PMC_SCRATCH40]
 	ret	r0			@ jump to tegra_resume
 ENDPROC(tegra30_lp1_reset)
 
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 92d46ec..23c42d0 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -33,6 +33,7 @@
 #define PMC_SCRATCH37	0x130
 #define PMC_SCRATCH38	0x134
 #define PMC_SCRATCH39	0x138
+#define PMC_SCRATCH40	0x13C
 #define PMC_SCRATCH41	0x140
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index a2c0ceb..51bfdeb 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -68,7 +68,7 @@
 #define PMC_CPUPWRGOOD_TIMER		0xc8
 #define PMC_CPUPWROFF_TIMER		0xcc
 
-#define PMC_SCRATCH41			0x140
+#define PMC_SCRATCH40			0x13C
 
 #define IO_DPD_REQ			0x1b8
 #define  IO_DPD_REQ_CODE_IDLE		(0 << 30)
@@ -742,14 +742,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
 #ifdef CONFIG_PM_SLEEP
 static int tegra_pmc_suspend(struct device *dev)
 {
-	tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
+	tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH40);
 
 	return 0;
 }
 
 static int tegra_pmc_resume(struct device *dev)
 {
-	tegra_pmc_writel(0x0, PMC_SCRATCH41);
+	tegra_pmc_writel(0x0, PMC_SCRATCH40);
 
 	return 0;
 }
-- 
2.2.0

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Stephen Warren]

On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume()
> location storing from late to early and as result broke suspend on tegra20.
> PMC scratch register 41 was used by tegra lp1 suspend core code for storing
> physical memory address of common resume function and in the same time used by
> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
> strict order of scratch register use. Fix it by using scratch 40 instead of 41
> for tegra_resume() location store.

You likely can't simply change the PMC scratch register usage 
arbitrarily; specific registers are designated for specific purposes, 
and code outside the Linux kernel (bootloaders, LP0 resume code, secure 
monitors, etc.) may depend on those specific values being in those 
registers. Without significant research, I'd suggest not changing the 
PMC scratch register usage.

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Dmitry Osipenko]

22.12.2014 19:17, Stephen Warren ?????:
> On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
>> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
>> tegra_resume()
>> location storing from late to early and as result broke suspend on tegra20.
>> PMC scratch register 41 was used by tegra lp1 suspend core code for storing
>> physical memory address of common resume function and in the same time used by
>> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
>> strict order of scratch register use. Fix it by using scratch 40 instead of 41
>> for tegra_resume() location store.
> 
> You likely can't simply change the PMC scratch register usage arbitrarily;
> specific registers are designated for specific purposes, and code outside the
> Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
> those specific values being in those registers. Without significant research,
> I'd suggest not changing the PMC scratch register usage.

Sure, that's why I asked to verify if scratch register 40 is in use in the
comment after commit message. I've checked that u-boot doesn't use it (since
upstream kernel doesn't care about any other bootloader), but no idea about
secure monitor. It's definitely safer to avoid changing scratch regs usage, I
thought that proposed solution would be best from the pure code point of view.
So, I'm considering your answer as a rejection of the patch (please, let me know
if I'm wrong) and will prepare another one. Btw, it would be nice to have
scratch registers usage publicly documented somewhere (on "Tegra Public
Application Notes" webpage for example), if it's possible, of course.

-- 
Dmitry

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Stephen Warren]

On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
> 22.12.2014 19:17, Stephen Warren ?????:
>> On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
>>> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
>>> tegra_resume()
>>> location storing from late to early and as result broke suspend on tegra20.
>>> PMC scratch register 41 was used by tegra lp1 suspend core code for storing
>>> physical memory address of common resume function and in the same time used by
>>> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
>>> strict order of scratch register use. Fix it by using scratch 40 instead of 41
>>> for tegra_resume() location store.
>>
>> You likely can't simply change the PMC scratch register usage arbitrarily;
>> specific registers are designated for specific purposes, and code outside the
>> Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
>> those specific values being in those registers. Without significant research,
>> I'd suggest not changing the PMC scratch register usage.
>
> Sure, that's why I asked to verify if scratch register 40 is in use in the
> comment after commit message.

Sorry, I didn't notice that.

> I've checked that u-boot doesn't use it (since
> upstream kernel doesn't care about any other bootloader), but no idea about
> secure monitor. It's definitely safer to avoid changing scratch regs usage, I
> thought that proposed solution would be best from the pure code point of view.
> So, I'm considering your answer as a rejection of the patch (please, let me know
> if I'm wrong) and will prepare another one. Btw, it would be nice to have
> scratch registers usage publicly documented somewhere (on "Tegra Public
> Application Notes" webpage for example), if it's possible, of course.

At this stage in Tegra20 development, I think it'd be best to avoid 
changing any scratch register usage if at all possible.

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Thierry Reding]

On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
> On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
> >22.12.2014 19:17, Stephen Warren ?????:
> >>On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
> >>>Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
> >>>tegra_resume()
> >>>location storing from late to early and as result broke suspend on tegra20.
> >>>PMC scratch register 41 was used by tegra lp1 suspend core code for storing
> >>>physical memory address of common resume function and in the same time used by
> >>>tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
> >>>strict order of scratch register use. Fix it by using scratch 40 instead of 41
> >>>for tegra_resume() location store.
> >>
> >>You likely can't simply change the PMC scratch register usage arbitrarily;
> >>specific registers are designated for specific purposes, and code outside the
> >>Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
> >>those specific values being in those registers. Without significant research,
> >>I'd suggest not changing the PMC scratch register usage.
> >
> >Sure, that's why I asked to verify if scratch register 40 is in use in the
> >comment after commit message.
> 
> Sorry, I didn't notice that.
> 
> >I've checked that u-boot doesn't use it (since
> >upstream kernel doesn't care about any other bootloader), but no idea about
> >secure monitor. It's definitely safer to avoid changing scratch regs usage, I
> >thought that proposed solution would be best from the pure code point of view.
> >So, I'm considering your answer as a rejection of the patch (please, let me know
> >if I'm wrong) and will prepare another one. Btw, it would be nice to have
> >scratch registers usage publicly documented somewhere (on "Tegra Public
> >Application Notes" webpage for example), if it's possible, of course.
> 
> At this stage in Tegra20 development, I think it'd be best to avoid changing
> any scratch register usage if at all possible.

Sorry, I had completely missed this discussion. When looking at the code
it doesn't look like this particular "resettable" status needs to be
stored in a PMC scratch register. It can't be stored in RAM because that
goes into self-refresh as part of LP1, but how about just putting it
into IRAM? That stays on in both LP1 and LP2, so should be suitable for
this use-case. It would make the code slightly more complex but using a
single scratch register for multiple purposes sounds brittle and easy to
break (as evidenced by the offending commit).

Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
configuration data across LP0 suspend/resume, so I wouldn't think it'd
cause problems if we used that instead of PMC_SCRATCH41 to store the
"resettable" state.

Changing the storage location for tegra_resume() isn't such a good idea
since that's a documented use of PMC_SCRATCH41.

Thierry
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[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Peter De Schrijver]

On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
> > On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
> > >22.12.2014 19:17, Stephen Warren ?????:
> > >>On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
> > >>>Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
> > >>>tegra_resume()
> > >>>location storing from late to early and as result broke suspend on tegra20.
> > >>>PMC scratch register 41 was used by tegra lp1 suspend core code for storing
> > >>>physical memory address of common resume function and in the same time used by
> > >>>tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
> > >>>strict order of scratch register use. Fix it by using scratch 40 instead of 41
> > >>>for tegra_resume() location store.
> > >>
> > >>You likely can't simply change the PMC scratch register usage arbitrarily;
> > >>specific registers are designated for specific purposes, and code outside the
> > >>Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
> > >>those specific values being in those registers. Without significant research,
> > >>I'd suggest not changing the PMC scratch register usage.
> > >
> > >Sure, that's why I asked to verify if scratch register 40 is in use in the
> > >comment after commit message.
> > 
> > Sorry, I didn't notice that.
> > 
> > >I've checked that u-boot doesn't use it (since
> > >upstream kernel doesn't care about any other bootloader), but no idea about
> > >secure monitor. It's definitely safer to avoid changing scratch regs usage, I
> > >thought that proposed solution would be best from the pure code point of view.
> > >So, I'm considering your answer as a rejection of the patch (please, let me know
> > >if I'm wrong) and will prepare another one. Btw, it would be nice to have
> > >scratch registers usage publicly documented somewhere (on "Tegra Public
> > >Application Notes" webpage for example), if it's possible, of course.
> > 
> > At this stage in Tegra20 development, I think it'd be best to avoid changing
> > any scratch register usage if at all possible.
> 
> Sorry, I had completely missed this discussion. When looking at the code
> it doesn't look like this particular "resettable" status needs to be
> stored in a PMC scratch register. It can't be stored in RAM because that
> goes into self-refresh as part of LP1, but how about just putting it
> into IRAM? That stays on in both LP1 and LP2, so should be suitable for
> this use-case. It would make the code slightly more complex but using a
> single scratch register for multiple purposes sounds brittle and easy to
> break (as evidenced by the offending commit).
> 
> Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
> configuration data across LP0 suspend/resume, so I wouldn't think it'd
> cause problems if we used that instead of PMC_SCRATCH41 to store the
> "resettable" state.
> 

No. Usually the scratch registers for EMC config data are setup once by the
bootloader and never touched by the kernel after that. So I would not
recommend reusing those registers for different purposes.

Cheers,

Peter.

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Thierry Reding]

On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote:
> On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
> > > On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
> > > >22.12.2014 19:17, Stephen Warren ?????:
> > > >>On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
> > > >>>Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
> > > >>>tegra_resume()
> > > >>>location storing from late to early and as result broke suspend on tegra20.
> > > >>>PMC scratch register 41 was used by tegra lp1 suspend core code for storing
> > > >>>physical memory address of common resume function and in the same time used by
> > > >>>tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
> > > >>>strict order of scratch register use. Fix it by using scratch 40 instead of 41
> > > >>>for tegra_resume() location store.
> > > >>
> > > >>You likely can't simply change the PMC scratch register usage arbitrarily;
> > > >>specific registers are designated for specific purposes, and code outside the
> > > >>Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
> > > >>those specific values being in those registers. Without significant research,
> > > >>I'd suggest not changing the PMC scratch register usage.
> > > >
> > > >Sure, that's why I asked to verify if scratch register 40 is in use in the
> > > >comment after commit message.
> > > 
> > > Sorry, I didn't notice that.
> > > 
> > > >I've checked that u-boot doesn't use it (since
> > > >upstream kernel doesn't care about any other bootloader), but no idea about
> > > >secure monitor. It's definitely safer to avoid changing scratch regs usage, I
> > > >thought that proposed solution would be best from the pure code point of view.
> > > >So, I'm considering your answer as a rejection of the patch (please, let me know
> > > >if I'm wrong) and will prepare another one. Btw, it would be nice to have
> > > >scratch registers usage publicly documented somewhere (on "Tegra Public
> > > >Application Notes" webpage for example), if it's possible, of course.
> > > 
> > > At this stage in Tegra20 development, I think it'd be best to avoid changing
> > > any scratch register usage if at all possible.
> > 
> > Sorry, I had completely missed this discussion. When looking at the code
> > it doesn't look like this particular "resettable" status needs to be
> > stored in a PMC scratch register. It can't be stored in RAM because that
> > goes into self-refresh as part of LP1, but how about just putting it
> > into IRAM? That stays on in both LP1 and LP2, so should be suitable for
> > this use-case. It would make the code slightly more complex but using a
> > single scratch register for multiple purposes sounds brittle and easy to
> > break (as evidenced by the offending commit).
> > 
> > Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
> > configuration data across LP0 suspend/resume, so I wouldn't think it'd
> > cause problems if we used that instead of PMC_SCRATCH41 to store the
> > "resettable" state.
> > 
> 
> No. Usually the scratch registers for EMC config data are setup once by the
> bootloader and never touched by the kernel after that. So I would not
> recommend reusing those registers for different purposes.

Right, I misread the code in the downstream kernel. Though it's not the
bootloader that does it (at least on Tegra20), but some early code in
the kernel.

IRAM sounds like a good candidate still. Or do you know of anything that
would exclude IRAM as storage location for this data?

Thierry
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[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Peter De Schrijver]

On Fri, Jan 09, 2015 at 10:51:35AM +0100, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote:
> > On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
> > > > Old Signed by an unknown key
> > > 
> > > On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
> > > > On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
> > > > >22.12.2014 19:17, Stephen Warren ?????:
> > > > >>On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
> > > > >>>Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
> > > > >>>tegra_resume()
> > > > >>>location storing from late to early and as result broke suspend on tegra20.
> > > > >>>PMC scratch register 41 was used by tegra lp1 suspend core code for storing
> > > > >>>physical memory address of common resume function and in the same time used by
> > > > >>>tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
> > > > >>>strict order of scratch register use. Fix it by using scratch 40 instead of 41
> > > > >>>for tegra_resume() location store.
> > > > >>
> > > > >>You likely can't simply change the PMC scratch register usage arbitrarily;
> > > > >>specific registers are designated for specific purposes, and code outside the
> > > > >>Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
> > > > >>those specific values being in those registers. Without significant research,
> > > > >>I'd suggest not changing the PMC scratch register usage.
> > > > >
> > > > >Sure, that's why I asked to verify if scratch register 40 is in use in the
> > > > >comment after commit message.
> > > > 
> > > > Sorry, I didn't notice that.
> > > > 
> > > > >I've checked that u-boot doesn't use it (since
> > > > >upstream kernel doesn't care about any other bootloader), but no idea about
> > > > >secure monitor. It's definitely safer to avoid changing scratch regs usage, I
> > > > >thought that proposed solution would be best from the pure code point of view.
> > > > >So, I'm considering your answer as a rejection of the patch (please, let me know
> > > > >if I'm wrong) and will prepare another one. Btw, it would be nice to have
> > > > >scratch registers usage publicly documented somewhere (on "Tegra Public
> > > > >Application Notes" webpage for example), if it's possible, of course.
> > > > 
> > > > At this stage in Tegra20 development, I think it'd be best to avoid changing
> > > > any scratch register usage if at all possible.
> > > 
> > > Sorry, I had completely missed this discussion. When looking at the code
> > > it doesn't look like this particular "resettable" status needs to be
> > > stored in a PMC scratch register. It can't be stored in RAM because that
> > > goes into self-refresh as part of LP1, but how about just putting it
> > > into IRAM? That stays on in both LP1 and LP2, so should be suitable for
> > > this use-case. It would make the code slightly more complex but using a
> > > single scratch register for multiple purposes sounds brittle and easy to
> > > break (as evidenced by the offending commit).
> > > 
> > > Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
> > > configuration data across LP0 suspend/resume, so I wouldn't think it'd
> > > cause problems if we used that instead of PMC_SCRATCH41 to store the
> > > "resettable" state.
> > > 
> > 
> > No. Usually the scratch registers for EMC config data are setup once by the
> > bootloader and never touched by the kernel after that. So I would not
> > recommend reusing those registers for different purposes.
> 
> Right, I misread the code in the downstream kernel. Though it's not the
> bootloader that does it (at least on Tegra20), but some early code in
> the kernel.
> 
> IRAM sounds like a good candidate still. Or do you know of anything that
> would exclude IRAM as storage location for this data?

No. I can't think of a reason this flag could not be in IRAM.

Cheers,

Peter.

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Dmitry Osipenko]

09.01.2015 13:29, Peter De Schrijver ?????:
> On Fri, Jan 09, 2015 at 10:51:35AM +0100, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote:
>>> On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
>>>>> Old Signed by an unknown key
>>>>
>>>> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
>>>>> On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
>>>>>> 22.12.2014 19:17, Stephen Warren ?????:
>>>>>>> On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
>>>>>>>> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
>>>>>>>> tegra_resume()
>>>>>>>> location storing from late to early and as result broke suspend on tegra20.
>>>>>>>> PMC scratch register 41 was used by tegra lp1 suspend core code for storing
>>>>>>>> physical memory address of common resume function and in the same time used by
>>>>>>>> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
>>>>>>>> strict order of scratch register use. Fix it by using scratch 40 instead of 41
>>>>>>>> for tegra_resume() location store.
>>>>>>>
>>>>>>> You likely can't simply change the PMC scratch register usage arbitrarily;
>>>>>>> specific registers are designated for specific purposes, and code outside the
>>>>>>> Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
>>>>>>> those specific values being in those registers. Without significant research,
>>>>>>> I'd suggest not changing the PMC scratch register usage.
>>>>>>
>>>>>> Sure, that's why I asked to verify if scratch register 40 is in use in the
>>>>>> comment after commit message.
>>>>>
>>>>> Sorry, I didn't notice that.
>>>>>
>>>>>> I've checked that u-boot doesn't use it (since
>>>>>> upstream kernel doesn't care about any other bootloader), but no idea about
>>>>>> secure monitor. It's definitely safer to avoid changing scratch regs usage, I
>>>>>> thought that proposed solution would be best from the pure code point of view.
>>>>>> So, I'm considering your answer as a rejection of the patch (please, let me know
>>>>>> if I'm wrong) and will prepare another one. Btw, it would be nice to have
>>>>>> scratch registers usage publicly documented somewhere (on "Tegra Public
>>>>>> Application Notes" webpage for example), if it's possible, of course.
>>>>>
>>>>> At this stage in Tegra20 development, I think it'd be best to avoid changing
>>>>> any scratch register usage if at all possible.
>>>>
>>>> Sorry, I had completely missed this discussion. When looking at the code
>>>> it doesn't look like this particular "resettable" status needs to be
>>>> stored in a PMC scratch register. It can't be stored in RAM because that
>>>> goes into self-refresh as part of LP1, but how about just putting it
>>>> into IRAM? That stays on in both LP1 and LP2, so should be suitable for
>>>> this use-case. It would make the code slightly more complex but using a
>>>> single scratch register for multiple purposes sounds brittle and easy to
>>>> break (as evidenced by the offending commit).
>>>>
>>>> Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
>>>> configuration data across LP0 suspend/resume, so I wouldn't think it'd
>>>> cause problems if we used that instead of PMC_SCRATCH41 to store the
>>>> "resettable" state.
>>>>
>>>
>>> No. Usually the scratch registers for EMC config data are setup once by the
>>> bootloader and never touched by the kernel after that. So I would not
>>> recommend reusing those registers for different purposes.
>>
>> Right, I misread the code in the downstream kernel. Though it's not the
>> bootloader that does it (at least on Tegra20), but some early code in
>> the kernel.
>>
>> IRAM sounds like a good candidate still. Or do you know of anything that
>> would exclude IRAM as storage location for this data?
> 
> No. I can't think of a reason this flag could not be in IRAM.
> 
> Cheers,
> 
> Peter.
> 

IRAM is a good candidate. Just tested draft patch version in QEMU, will give it
more testing and polish during weekend and send next week.

-- 
Dmitry

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Stephen Warren]

On 01/09/2015 03:29 AM, Peter De Schrijver wrote:
> On Fri, Jan 09, 2015 at 10:51:35AM +0100, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote:
>>> On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
>>>>> Old Signed by an unknown key
>>>>
>>>> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
>>>>> On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
>>>>>> 22.12.2014 19:17, Stephen Warren ?????:
>>>>>>> On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
>>>>>>>> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
>>>>>>>> tegra_resume()
>>>>>>>> location storing from late to early and as result broke suspend on tegra20.
>>>>>>>> PMC scratch register 41 was used by tegra lp1 suspend core code for storing
>>>>>>>> physical memory address of common resume function and in the same time used by
>>>>>>>> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
>>>>>>>> strict order of scratch register use. Fix it by using scratch 40 instead of 41
>>>>>>>> for tegra_resume() location store.
>>>>>>>
>>>>>>> You likely can't simply change the PMC scratch register usage arbitrarily;
>>>>>>> specific registers are designated for specific purposes, and code outside the
>>>>>>> Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may depend on
>>>>>>> those specific values being in those registers. Without significant research,
>>>>>>> I'd suggest not changing the PMC scratch register usage.
>>>>>>
>>>>>> Sure, that's why I asked to verify if scratch register 40 is in use in the
>>>>>> comment after commit message.
>>>>>
>>>>> Sorry, I didn't notice that.
>>>>>
>>>>>> I've checked that u-boot doesn't use it (since
>>>>>> upstream kernel doesn't care about any other bootloader), but no idea about
>>>>>> secure monitor. It's definitely safer to avoid changing scratch regs usage, I
>>>>>> thought that proposed solution would be best from the pure code point of view.
>>>>>> So, I'm considering your answer as a rejection of the patch (please, let me know
>>>>>> if I'm wrong) and will prepare another one. Btw, it would be nice to have
>>>>>> scratch registers usage publicly documented somewhere (on "Tegra Public
>>>>>> Application Notes" webpage for example), if it's possible, of course.
>>>>>
>>>>> At this stage in Tegra20 development, I think it'd be best to avoid changing
>>>>> any scratch register usage if at all possible.
>>>>
>>>> Sorry, I had completely missed this discussion. When looking at the code
>>>> it doesn't look like this particular "resettable" status needs to be
>>>> stored in a PMC scratch register. It can't be stored in RAM because that
>>>> goes into self-refresh as part of LP1, but how about just putting it
>>>> into IRAM? That stays on in both LP1 and LP2, so should be suitable for
>>>> this use-case. It would make the code slightly more complex but using a
>>>> single scratch register for multiple purposes sounds brittle and easy to
>>>> break (as evidenced by the offending commit).
>>>>
>>>> Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
>>>> configuration data across LP0 suspend/resume, so I wouldn't think it'd
>>>> cause problems if we used that instead of PMC_SCRATCH41 to store the
>>>> "resettable" state.
>>>>
>>>
>>> No. Usually the scratch registers for EMC config data are setup once by the
>>> bootloader and never touched by the kernel after that. So I would not
>>> recommend reusing those registers for different purposes.
>>
>> Right, I misread the code in the downstream kernel. Though it's not the
>> bootloader that does it (at least on Tegra20), but some early code in
>> the kernel.
>>
>> IRAM sounds like a good candidate still. Or do you know of anything that
>> would exclude IRAM as storage location for this data?
>
> No. I can't think of a reason this flag could not be in IRAM.

The only thing you might want to watch out for is whether something else 
is using IRAM. For example, our product SW stacks use the AVP as a media 
co-processor and that runs at least some of its code from IRAM. To 
support something similar, you'd need to make sure to save/restore the 
IRAM content when using it for other purposes rather than just blindly 
over-writing it (and of course synchronize with any driver for the AVP 
execution, to ensure it was shut down first and brought back up last 
after any power saving event). Of course, we don't actually support 
loading code onto the AVP upstream at the moment, so perhaps we can 
defer handling that for now.

[PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store

[Dmitry Osipenko]

09.01.2015 19:57, Stephen Warren ?????:
> On 01/09/2015 03:29 AM, Peter De Schrijver wrote:
>> On Fri, Jan 09, 2015 at 10:51:35AM +0100, Thierry Reding wrote:
>>> * PGP Signed by an unknown key
>>>
>>> On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote:
>>>> On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
>>>>>> Old Signed by an unknown key
>>>>>
>>>>> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
>>>>>> On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
>>>>>>> 22.12.2014 19:17, Stephen Warren ?????:
>>>>>>>> On 12/21/2014 03:52 PM, Dmitry Osipenko wrote:
>>>>>>>>> Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
>>>>>>>>> tegra_resume()
>>>>>>>>> location storing from late to early and as result broke suspend on
>>>>>>>>> tegra20.
>>>>>>>>> PMC scratch register 41 was used by tegra lp1 suspend core code for
>>>>>>>>> storing
>>>>>>>>> physical memory address of common resume function and in the same time
>>>>>>>>> used by
>>>>>>>>> tegra20 cpuidle driver for storing cpu1 "resettable" status, so it implied
>>>>>>>>> strict order of scratch register use. Fix it by using scratch 40
>>>>>>>>> instead of 41
>>>>>>>>> for tegra_resume() location store.
>>>>>>>>
>>>>>>>> You likely can't simply change the PMC scratch register usage arbitrarily;
>>>>>>>> specific registers are designated for specific purposes, and code
>>>>>>>> outside the
>>>>>>>> Linux kernel (bootloaders, LP0 resume code, secure monitors, etc.) may
>>>>>>>> depend on
>>>>>>>> those specific values being in those registers. Without significant
>>>>>>>> research,
>>>>>>>> I'd suggest not changing the PMC scratch register usage.
>>>>>>>
>>>>>>> Sure, that's why I asked to verify if scratch register 40 is in use in the
>>>>>>> comment after commit message.
>>>>>>
>>>>>> Sorry, I didn't notice that.
>>>>>>
>>>>>>> I've checked that u-boot doesn't use it (since
>>>>>>> upstream kernel doesn't care about any other bootloader), but no idea about
>>>>>>> secure monitor. It's definitely safer to avoid changing scratch regs
>>>>>>> usage, I
>>>>>>> thought that proposed solution would be best from the pure code point of
>>>>>>> view.
>>>>>>> So, I'm considering your answer as a rejection of the patch (please, let
>>>>>>> me know
>>>>>>> if I'm wrong) and will prepare another one. Btw, it would be nice to have
>>>>>>> scratch registers usage publicly documented somewhere (on "Tegra Public
>>>>>>> Application Notes" webpage for example), if it's possible, of course.
>>>>>>
>>>>>> At this stage in Tegra20 development, I think it'd be best to avoid changing
>>>>>> any scratch register usage if at all possible.
>>>>>
>>>>> Sorry, I had completely missed this discussion. When looking at the code
>>>>> it doesn't look like this particular "resettable" status needs to be
>>>>> stored in a PMC scratch register. It can't be stored in RAM because that
>>>>> goes into self-refresh as part of LP1, but how about just putting it
>>>>> into IRAM? That stays on in both LP1 and LP2, so should be suitable for
>>>>> this use-case. It would make the code slightly more complex but using a
>>>>> single scratch register for multiple purposes sounds brittle and easy to
>>>>> break (as evidenced by the offending commit).
>>>>>
>>>>> Otherwise it would seem that PMC_SCRATCH40 is only used to store EMC
>>>>> configuration data across LP0 suspend/resume, so I wouldn't think it'd
>>>>> cause problems if we used that instead of PMC_SCRATCH41 to store the
>>>>> "resettable" state.
>>>>>
>>>>
>>>> No. Usually the scratch registers for EMC config data are setup once by the
>>>> bootloader and never touched by the kernel after that. So I would not
>>>> recommend reusing those registers for different purposes.
>>>
>>> Right, I misread the code in the downstream kernel. Though it's not the
>>> bootloader that does it (at least on Tegra20), but some early code in
>>> the kernel.
>>>
>>> IRAM sounds like a good candidate still. Or do you know of anything that
>>> would exclude IRAM as storage location for this data?
>>
>> No. I can't think of a reason this flag could not be in IRAM.
> 
> The only thing you might want to watch out for is whether something else is
> using IRAM. For example, our product SW stacks use the AVP as a media
> co-processor and that runs at least some of its code from IRAM. To support
> something similar, you'd need to make sure to save/restore the IRAM content when
> using it for other purposes rather than just blindly over-writing it (and of
> course synchronize with any driver for the AVP execution, to ensure it was shut
> down first and brought back up last after any power saving event). Of course, we
> don't actually support loading code onto the AVP upstream at the moment, so
> perhaps we can defer handling that for now.
> 

Sure, currently I placed "resettable" variable in IRAM reset handler area for
that reason. As I wrote before, I'll give patch more polish and send after.

-- 
Dmitry